CLP

CLP : Conformal Low Power is a formal verification tool used to verify power-
aware designs. It ensures that your RTL and gate-level implementations
are functionally equivalent, especially when low power techniques such
as power gating, clock gating, multi-voltage domains, and isolation cells are
introduced.

its perform power intent checks (upf)

Tool : Conformal Low Power (CLP)

Inputs :

 RTL netlist
 Gate-level netlist
 UPF files (power intent)
 Constraints (SDF, SDC)
 Feature Description

Tool Conformal Low Power (CLP)

Vendor Synopsys

Use Power-aware formal equivalence checking

Importance Ensures correctness of low-power design techniques

Example Use Case Scenario

Scenario What CLP does

Power gating added after Verifies if isolation and retention are properly
synthesis applied and don’t alter behavior
Checks level shifters, domain crossings, and
Multiple voltage domains
ensures data integrity
Clock gating insertion Ensures that gating doesn't break functionality

Checks:

Conformal Low Power (CLP) performs two main categories of checks:

✅ A. Power-Aware Equivalence Checks

✅ B. Structural & Static Power Intent Checks

✅ A. Power-Aware Equivalence Checks

These checks ensure that the gate-level netlist (with power logic) is
functionally equivalent to the RTL (without explicit power logic), based
on the UPF.

1. RTL vs Gate-Level Equivalence with UPF

Purpose: Verifies if the insertion of low-power cells (isolation, retention,

etc.) preserves original functionality.

Method: Formal verification compares both designs cycle-by-cycle

across all power states
2. Power State Coverage

 CLP simulates multiple power states:

I. All domains ON
II. One or more domains OFF
III. Retention state on power down/up

 Verifies expected behavior under all power combinations defined in

UPF.

3. Sequential Equivalence with Retention

Checks whether retained registers restore the same values after power
cycling.

Ensures register state is correctly saved and restored using

the set_retention and related UPF commands.

4. Clock Gating Equivalence

Verifies that clock gating does not alter functional behavior.

Ensures that gated clocks don't result in data loss or glitches.

✅ B. Structural & Static Power Intent Checks

These are structural rule-based checks that analyze the power

intent (defined in UPF) against the netlist.

1. Isolation Cell Checks

What is checked? CLP verifies:

Presence Isolation cells are instantiated where needed.
Correct Domain Isolation logic is in the right power domains.
Polarity and function of isolation control are
Enable Signal
correct.
Cell is placed at the domain crossing
Correct Location
boundary.
2. Retention Register Checks

CLP ensures:
Proper declaration in UPF.
Retention logic correctly inserted into gate-level netlist.
Save/restore signals are defined and used correctly.
Retained values match expectations post power-up.

3. Power Switch Checks

Ensures power switches:

Are connected to the correct power rails.

Are controllable via enable signals.

Are declared and instantiated as per UPF.

4. Level Shifter Checks

Checks performed:
Presence at domain crossings.
Proper orientation (up/down shifting).
Proper voltage domain assignments.
Timing-safe connectivity.

5. Power Domain and Net Connectivity

CLP ensures:

Every module is within a defined power domain.

Proper voltage net connections exist.

Cross-domain signals are properly isolated or level-shifted.

6. Supply Network Checks

Verifies:

Power/ground nets are connected correctly.

No floating supplies or unconnected domains.

Bulk connections for analog/digital separation.

7. Domain Crossing Checks

Ensures that signals crossing voltage or power domains:

Are isolated or level shifted.

Do not cause X-propagation or undefined behavior.

What CLP Checks Address:

Isolation:

CLP verifies that isolation cells (like isolation latches) are correctly
implemented to prevent signal propagation between power domains when
they are not supposed to be active. This is crucial when a domain is powered
down, and signals from an active domain should not leak into the off domain.

Level Shifters:

CLP checks that level shifters are appropriately placed to handle voltage level
differences between power domains. This ensures that signals can be
transmitted safely between different voltage levels, preventing voltage
mismatches and potential damage.

Retention Cells:

CLP verifies that retention cells (like retention flip-flops) correctly hold the
state of the design when a power domain is powered down. This is important
for maintaining the integrity of critical data when power is removed.

level shifter

level shifter cell can be of the following two types:

 High-to-Low – Converts a high-voltage level to a low-voltage level. It is

inserted when the source power domain operates at a higher voltage and the
sink power domain operates at a lower voltage.
 Low-to-High – Converts a low-voltage level to a high-voltage level. It is
inserted when the source power domain operates at a lower voltage and the
sink power domain operates at a higher voltage.
Retention cells & Checks

Consider you have a power domain, which is powered-down. When the

domain is powered-up again, all the state information from before the domain
was powered-down is lost. To avoid this, designers place retention cells in
power domains, which stores the state value of the power domain. Retaining
the state value helps the power domain become operational sooner.

A design may have multiple power domains that are powered-down, which
may lead to many retention issues. The simulator runs various retention
checks on the design to find out the retention issues, and flags an error in
case of a violation.

Back-to-Back Checks

 Sometimes your design has back-to-back cells, which might be any of

the following types:
 Isolation and level shifter cell
 Level shifter and isolation cell
 Isolation and isolation cell
 Level shifter and level shifter cell

Other checks

 The design cells have missing liberty attributes.

 The isolation, level shifter, or retention supply is powered-down during
the active isolation, level shifting, or retention period.
 The power signal of a power domain gets corrupted.
 The input of a power domain toggles when the power domain is
powered-down.
 The power state table or the supply port reaches an illegal or undefined
state.
Common CLP Issues and Fixes:

Missing or Incorrect Isolation Cells:

If there is a domain crossing from OFF to ON, an isolation cell with the correct
control signal and clamp value needs to be added.

Missing or Incorrect Level Shifters:

If there is a voltage mismatch crossing, a level shifter cell based on the

voltage values needs to be added.

Invalid Power State Transitions:

CLP checks for invalid power state transitions and ensures that power
domains are powered down in the correct order.

Incorrect Clamp Values:

The clamp value of the isolation cell in the design should match the
corresponding strategy specified in the UPF file.

Tools for CLP Checks:

Cadence's Conformal Low Power is a widely used tool for performing CLP
checks.

There can be different types of clp issues.

main clp issues are crossing issues.

If there are is domain crossing from OFF to ON then you need to add one
isolation cell with proper control signal and calmp value.

Now if there is any voltage mismatch crossover you need to add Level shifter
cell based on volatge values. It can be either LH, HL or LH_HL type.
1. Understanding CLP Issues:

Power Domain Crossing:

CLP checks for potential issues when signals cross between different power domains
(e.g., an "ON" domain and an "OFF" domain).

Voltage Mismatches:

CLP also identifies problems when signals cross between different voltage levels.

2. Common CLP Solutions:

Isolation Cells:

When a signal crosses from an "OFF" domain to an "ON" domain, an isolation cell is
added to prevent unintended current flow. This cell uses a control signal and a clamp
value to isolate the "OFF" domain.

Level Shifters:

If there's a voltage mismatch between domains, a level shifter is needed to translate

the signal to the correct voltage level. These can be High-to-Low (HL) or Low-to-
High (LH) shifters, or even HL/LH shifters.

Enable Level Shifters:

When both domain crossing and voltage mismatch occur, an enable level shifter is
used, which combines the functions of an isolation cell and a level shifter.

3. Additional Considerations:

PNR Issues:

Incorrect buffering or supply voltages in the Placement and Routing (PNR) netlist can
also cause CLP problems.

UPF Updates:

Addressing these issues might require updates to the University of Pennsylvania

Framework (UPF) file.

Always-On Buffers:

When communicating between different domains, it's crucial to ensure that the correct
type of buffer (e.g., always-on buffer) is used to prevent CLP issues.
Unified Power Format (UPF)
UPF is used to define and manage power saving strategies in IC designs,
ensuring low-power techniques are applied consistently

Example:

In sleep mode, a laptop reduces power consumption by turning off certain

components while keeping others in a low power state.

Some Terminologies:

1. Power Rails: These are the physical lines or networks that distribute power
across different parts of the IC.

2. Power Domains: Logical sections of the IC that can be powered on or off

independently. For example, different functional blocks like CPUs, GPUs, or
memory units can be assigned to different power domains.

3. Primary Power Supply: The primary power supply is the main voltage
source for a
power domain. It is the default power supply that powers the logic within the
domain when
the domain is active.
3. Power Control Network (PCN): PCN is a network that includes the power
switches, level shifters, and isolation cells used to control and manage the
power states of different power domains.

5. power mode/State : A power mode defines the operational state of a power

domain or multiple domains. It specifies which domains are active (powered
on) and which are inactive
(powered off).

6. Voltage Island: A voltage island is another term for a power domain,

particularly when it operates at a different voltage level from the rest of the
chip
7. Low Power Cells: low power cells are specialized cells designed to reduce
power consumption in integrated circuits. These cells include Isolation Cells,
level shifters, Retention Cells, Power Switch and Always on cell.

8. Level Shifter: A level shifter is a circuit used to interface signals between

two power domains operating at different voltage levels.

9. Isolation Cell: Isolation cells are used to prevent floating signals when a
power domain is
powered down while the neighbouring domain remains active

10.Retention Cell: Retention cells are special flip-flops or memory

elements that retain their state (data) even when the power supply to their
power domain is turned off.

11.Power Switch: a power switch is a key component used to control the

supply of power to different sections of a circuit. Power switches are
crucial for implementing power gating.

10.Always On Cells: always on cells are components of a design that need to

be continuously powered, regardless of the power states of other parts of
the circuit.