Computer Organization and Architecture

CEA201
CH01-Introduction:
1.1 What, in general terms, is the distinction between computer organization and
computer architecture?

Computer architecture refers to the fundamental design of a computer system, including

the instruction set architecture (ISA), memory hierarchy, and the interfaces between the
CPU, memory, and I/O devices. It defines the hardware/software interface and determines
what a computer is capable of doing and how it does it.

1.2 What, in general terms, is the distinction between computer structure and computer
function?
Structure is how devices are interrelated, while function is the individual
characteristics of each one.
- Structure: The way in which components relate to each other
- Function: The operation of individual components as part of the structure

1.3 What are the four main functions of a computer?

1- Data processing
2- Data movement
3- Data storage
4- Control
A general purpose computer has four main components: the arithmetic and logic unit (ALU), the
control unit, the memory, and the input and output devices (collectively termed I/O).

1.4 List and briefly define the main structural components of a computer.
 CPU (Central processing unit): known as processor as well, it’s the main computer component,
responsible for the main functions of the computer.
 I/O: responsible for the communication between the computer and the external world.
 Data storage: device responsible for data saving.
 System bus: responsible for the interconnection between data storage, CPU and I/O.

1.5 List and briefly define the main structural components of a processor.
 Control unit: Controls the operation of the CPU and hence the computer itself.
 ALU: make logical and arithmetic operations.
 Registers: temporally storage for data while processor operations.
 Internal bus: interconnect control unit, ALU and registers inside processor.
CH02-ComputerEvolutionAndPerformace:
2.1 What is a stored program computer?
A computer which stores its program in memory, like it stores data. Instructions are read from
the memory and executed

2.2 What are the four main components of any general-purpose computer?
- Main memory
- Arithmetic-logic unit
- Program Control unit
- I/O equipment

2.3 At the integrated circuit level, what are the three principal constituents of a computer
system?
- Transistors
- Resistors
- Capacitors

2.4 Explain Moore’s law.

Moore observed that the number of transistors that could be put on a single chip was doubling
every year. The pace continued until the 1970s when it slowed down to a doubling every 18
months

2.5 List and explain the key characteristics of a computer family.

- Compatibility: a program written for one member should work on any computer of
the family
- Similar instruction set
- Similar operating system
- Increasing speed, I/O ports, memory, cost

2.6 What is the key distinguishing feature of a microprocessor?

- All the components of the CPU were on a single chip.
Refer to the table 2.1
CH03-TopLevelView:
3.1 What general categories of functions are specified by computer instructions?
- Processor-Memory data transfer
- Processor-I/O data transfer
- Data processing
- Control

3.2 List and briefly define the possible states that define an instruction execution.
- Instruction address calculation: Determine the address of the next instruction
to be executed.
- Instruction fetch: Read instruction from its memory location into the processor.
- Instruction operation decoding: Analyze instruction to determine the type of
operation to be performed and operands to be used.
- Operand address calculation: If the operation involves reference to an operand
in memory or available via I/O, then determine the address of the operand.
- Operand fetch: Fetch the operand from memory or read it in from I/O.
- Data operation: Perform the operation indicated in the instruction.
- Operand store: Write the result into memory or out to I/O

3.3 List and briefly define two approaches to dealing with multiple interrupts.
Disabling interrupts: the processor has the ability to and will ignore specific
interrupts. Those interrupts remain pending and will be checked after the
processor has enabled interrupts.
Interrupt service routine (ISR): priorities assigned to the different types of
interrupts. ISRs with higher priorities can interrupt ones with lower priority, in
which case the ISR with the lower priority is put on the stack until that ISR is
completed.
3.4 What types of transfers must a computer’s interconnection structure (e.g., bus) support?
• Memory to processor: The processor reads an instruction or a unit of data
from memory.
• Processor to memory: The processor writes a unit of data to memory.
• I/O to processor: The processor reads data from an I/O device via an I/O
module.
• Processor to I/O: The processor sends data to the I/O device.
• I/O to or from memory: For these two cases, an I/O module is allowed to
exchange data directly with memory, without going through the processor,
using direct memory access.

3.5 What is the benefit of using a multiple-bus architecture compared to a single-bus

architecture?
The single-bus architecture has 2 problems:
1. The more devices attached to the bus, the greater the bus length and hence
the greater the propagation delay.
2. The bus may become a bottleneck as the aggregate data transfer demand
approaches the capacity of the bus.
CH04-CacheMemory:
4.1- What are the differences among sequential access, direct access, and random access?
+ Sequential access: Memory is organized into units of data, called records. Accessmust be made
in a specific linear sequence.
+ Direct access: Individual blocks orrecords have a unique address based on physical location.
+ Random access: Each addressable location inmemory has a unique, physically wired-in
addressing mechanism. The time toaccess a given location is independent of the sequence of
prior accesses and isconstant

4.2-What is the general relationship among access time, memory cost, and capacity?
Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater
capacity, slower access time.
Faster access time, greater cost per bit; greater capacity, smaller cost per bit; greater capacity,
slower access time.

4.3- How does the principle of locality relate to the use of multiple memory levels?
It is possible to organize data across a memory hierarchy such that the percentage
of accesses to each successively lower level is substantially less than that of the
level above.

4.4- What are the differences among direct mapping and associative mapping?
In a cache system, direct mapping maps each block of main memory into only one
possible cache line. Associative mapping permits each main memory block to be
loaded into any line of the cache.

4.5- For a direct-mapped cache, a main memory address is viewed as consisting of three fields.
List and define the three fields.
One field identifies a unique word or byte within a block of main memory. The
remaining two fields specify one of the blocks of main memory. These two fields
are a line field, which identifies one of the lines of the cache, and a tag field, which
identifies one of the blocks that can fit into that line

4.6- For an associative cache, a main memory address is viewed as consisting of two fields. List
and define the two fields.
A tag field uniquely identifies a block of main memory. A word field identifies a
unique word or byte within a block of main memory.
CH05-InternalMemory:
5.1 What are the key properties of semiconductor memory?
• it has two (semi)stable states which can be used to represent binary 1 and 0
• it supports read/write operations

5.2 What are two interpretations of the term random-access memory?

• DRAM
• SRAM
5.3 What is the difference between DRAM and SRAM in terms of application?
- SRAM is used for cache memory
- DRAM is used for main memory

5.4 What is the difference between DRAM and SRAM in terms of characteristics such as speed,
size, and cost?
- speed: SRAM is faster
- size: SRAM takes more space, DRAM is denser
- cost: SRAM is more expensive than DRAM

5.5 Explain why one type of RAM is considered to be analog and the other digital.
- DRAM: analog device because it stores charge and uses a threshold to determine the binary
value
- SRAM: digital because it uses flip-flop logic gates

5.6 What are some applications for ROM?

• Microprogramming
• Library subroutines for frequently wanted functions
• System programs
• Function tables

5.7 What are the differences among EPROM, EEPROM, and flash memory?
EPROM is erasable programmable memory. It is read only but can be erased with ultraviolet
light, allowing the memory to then be rewritten.
EEPROM is like EPROM, but can be erased with an electrical charge, it can also be written into
without erasing prior contents, with only the byte or bytes addressed being updated.
Flash memory is the intermediate between EPROM and EEPROM. It is electronically erasable
like EEPROM, and allows for blocks of memory to be erased, not just the entire chip, though it
cannot be erased at the byte level.
EPROM:
- read/written electrically
- before writing, all cells must be erased by exposure to UV light
EEPROM:
- can be written to any time, without erasing contents
Flash memoy:
- electrical erasing (in seconds), faster than EPROM

5.8 Explain the function of each pin in Figure 5.4b. 182 CHAPTER 5 / INTERNAL MEMORY

5.9 What is a parity bit?

Parity bit is a bit that is added to the end of each string of binary code bit. It is used to detect the
parity errors occurred in the binary digits.

-When processing the bit values, the bit 1 that is corrupted as 0 or 0 corrupted as 1 is called a
parity error

-A parity error may occur while storing and retrieving bytes of data or sending or receiving bytes
of data
5.10 How is the syndrome for the Hamming code interpreted?
If the syndrome contains all 0s, no error has been detected. IF the syndrome contains one and
only one bit set to 1, then an error has occurred in one of the 4-check bits, and no correction is
necessary. If the syndrome contains more than one bit set to 1, then the numerical value of the
syndrome indicates the position of the data bit in error. That bit is inverted for correction.
5.11 How does SDRAM differ from ordinary DRAM?
Synchronous DRAM is synchronized to an external clock signal and running at the full speed of
the processor/memory bus without imposing wait states. DRAM is asynchronous.
CH06-ExternalMemory:
6.7 Define the terms seek time, rotational delay, access time, and transfer time.
Rotational delay - Once the track is selected, the disk controller waits until the appropriate sector
rotates to line up with the head. The time it takes for the beginning of the sector to reach the head
is known as the
rotational delay.
Access time - The sum of the seek time, if any, plus the rotational delay. The time it takes to get
into positionto read or write.
Transfer time - Time taken for data transfer. Once the head is in position, the read or write
operation is performed as the sector moves under the head - data transfer portion of the
operation.

6.8 What common characteristics are shared by all RAID levels?

1. RAID is a set of physical disk drives viewed by the operating system as a single logical drive.
2. Data are distributed across the physical drives of an array in a scheme known as striping.
3. Redundant disk capacity is used to store parity information, which guarantees data
recoverability in case of a disk failure.

6.9 Briefly define the seven RAID levels.

• RAID 0 - Non-redundant.
• RAID 1 - Mirrored, every disk has a mirror disk containing the same data.
• RAID 2 - Redundant via Hamming code; an error-correcting code is calculated across
corresponding bits
on each data disk, and the bits of the code are stored in the corresponding bit positions on
multiple parity
disks.
• RAID 3 - Bit-interleaved parity;
• RAID 4 - Block-interleaved parity;
• RAID 5 - Block-interleaved distributed parity;
• RAID 6 - Block-interleaved dual distributed parity
6.10 Explain the term striped data.
The disk is divided into strips, which may be physical blocks, sectors, or some other unit. The
strips are mapped round robin to consecutive array members. A set of logically consecutive
strips that maps exactly one strip to each array member is referred to as a stripe

6.11 How is redundancy achieved in a RAID system?

RAID 1: by having two identical copies of all data
The rest: by the use of error-correcting codes

6.12 In the context of RAID, what is the distinction between parallel access and independent
access?
Parallel access - All member disks participate in the execution of every I/O request. Typically,
the spindles of the individual drives are synchronized so that each disk head is in the same
position on each disk at any given time.
Independent access - Each member disk operates independently, so that separate I/O requests can
be satisfied in parallel.
CH07-InputOutput:
7.1- List three broad classifications of external, or peripheral, devices.
Human readable (suitable for communicating with computer user), machine
readable(...equipment), communication(...remote devices).

7.2- What is the International Reference Alphabet?

In which each character is represented by unique 7-bit binary code i.e 128 different characters
can be represented.

7.3- What are the major functions of an I/O module?

Control and timing, processor communication, device communication, data buffering, error
detection.
7.4- List and briefly define three techniques for performing I/O.
Programmed I/O: The processor issues an I/O command, on behalf of a process to an I/O
module; that
process then busy-waits for the operation to be completed before proceeding.
Interrupt-driven I/O: The processor issues an I/O command on behalf of a process, continues to
execute
subsequent instructions, and is interrupted by the I/O module when latter has completed its work.

7.5- What is the difference between memory-mapped I/O and isolated I/O?
Programmed I/O: The processor issues an I/O command, on behalf of a process to an I/O
module; that
process then busy-waits for the operation to be completed before proceeding.
Interrupt-driven I/O: The processor issues an I/O command on behalf of a process, continues to
execute
subsequent instructions, and is interrupted by the I/O module when latter has completed its work.
Direct memory access: controls exchange of data between main memory and I/O module.
7.6- When a device interrupt occurs, how does the processor determine which device issued
the interrupt?
Multiple interrupt lines, software poll, daisy chain, bus arbitration