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Digital Design & Microprocessors

Finite State Machine

1
VNU - University of Engineering and Technology 1 Faculty of Electronics and Telecommunications
Finite State Machine
Finite State Machine (FSM): is a conceptual model that describes systems with a finite number of states and transitions to
represent their behavior and logic.
➢ States: System’s configuration
➢ Transitions: How to move from one state to another based on inputs or events
➢ Inputs: Trigger transitions
➢ Output: (Optional) Generate based on current state or state transition

Transition

Reset

S0 S1

Fig 1. FSM diagram

VNU - University of Engineering and Technology 2 Faculty of Electronics and Telecommunications

Mealy Machine & Moore Machine
Moore Machine: outputs depends only on state (output at state)

Fig 2. Moore FSM diagram Fig 3. Moore state transition table

VNU - University of Engineering and Technology 3 Faculty of Electronics and Telecommunications

Mealy Machine & Moore Machine
Mealy Machine: outputs depends on state and input (output at transition)

Fig 4. Mealy FSM diagram Fig 5. Mealy state transition table

VNU - University of Engineering and Technology 4 Faculty of Electronics and Telecommunications

FSM Procedural

VNU - University of Engineering and Technology 5 Faculty of Electronics and Telecommunications

Traffic light
Traffic light: Two lane A and B
➢ S0: Wait until there a no people in lane A
➢ S1: Count down before check lane B
➢ S2: Wait until there are no people in lane B
➢ S3: Count down before check A

Fig 7. State transition table

State Output
S0 LA: green, LB: red
S1 LA: yellow, LB: red
S2 LA: red, LB: green
S3 LA: red, LB: yellow

Output table
Fig 6. Traffic light FSM

VNU - University of Engineering and Technology 6 Faculty of Electronics and Telecommunications

Traffic light

module traffic_light ( localparam clk_div_period =

input clk, 12_000_000; //when simulation, set
input reset_n, clk_div_period to 12
input Ta, reg [24:0] counter_clk;
input Tb, reg [4:0] counter_sec;
wire [4:0] counter_sec_wire;
output reg [7:0] led_7_segment_1, reg counter_reset;
output reg [7:0] led_7_segment_2,
output led_7_segment_1_ena, localparam S0 = 0; //La green, Lb red
output led_7_segment_2_ena, localparam S1 = 1; //La yellow, Lb red
output reg [2:0] La, localparam S2 = 2; //La red, Lb green
output reg [2:0] Lb localparam S3 = 3; //La red, Lb yellow
); localparam GREEN = 3'b101; //(rgb: 5)
localparam YELLOW = 3'b001;//(rgb: 1)
localparam RED = 3'b011; //(rgb: 3)
reg [1:0] current_state;
reg [1:0] next_state;

VNU - University of Engineering and Technology 7 Faculty of Electronics and Telecommunications

Traffic light

//7 segment digit always @*

assign led_7_segment_1_ena = 0; begin
assign led_7_segment_2_ena = 0; case (counter_sec_wire)
0: led_7_segment_2 = 8'h3F;
assign counter_sec_wire = current_state == 1: led_7_segment_2 = 8'h06;
S0 || current_state == S2 ? 4 : counter_sec; 2: led_7_segment_2 = 8'h5B;
3: led_7_segment_2 = 8'h4F;
always @* 4: led_7_segment_2 = 8'h66;
begin 5: led_7_segment_2 = 8'h6D;
case (counter_sec_wire) 6: led_7_segment_2 = 8'h7D;
0: led_7_segment_1 = 8'h3F; 7: led_7_segment_2 = 8'h07;
1: led_7_segment_1 = 8'h06; 8: led_7_segment_2 = 8'h7F;
2: led_7_segment_1 = 8'h5B; 9: led_7_segment_2 = 8'h6F;
3: led_7_segment_1 = 8'h4F; default: led_7_segment_2 = 8'hFF;
4: led_7_segment_1 = 8'h66; endcase
5: led_7_segment_1 = 8'h6D; end
6: led_7_segment_1 = 8'h7D;
7: led_7_segment_1 = 8'h07;
8: led_7_segment_1 = 8'h7F;
9: led_7_segment_1 = 8'h6F;
default: led_7_segment_1 = 8'hFF;
endcase
end

VNU - University of Engineering and Technology 8 Faculty of Electronics and Telecommunications

Traffic light
//---------------------------------------Counter----------------------------------
always @(posedge clk, negedge reset_n)
begin
if (~reset_n)
counter_clk <= 0;
else
if (counter_clk == clk_div_period - 1)
counter_clk <= 0;
else
counter_clk <= counter_clk + 1;
end
always @(posedge clk, negedge reset_n)
begin
if (~reset_n)
counter_sec <= 4;
else
begin
if (counter_reset)
counter_sec <= 4;
else
if (counter_clk == clk_div_period - 1)
counter_sec <= counter_sec - 1;
else
counter_sec <= counter_sec;
end
end

VNU - University of Engineering and Technology 9 Faculty of Electronics and Telecommunications

Traffic light

Following the above procedural //current_state -> next_state

always @*
➢ Code the sequential state register logic begin
➢ Code the functionality of state register logic case (current_state)
S0:
➢ Code the functionality of the next stage logic if (~Ta )
➢ Code the output logic next_state = S1;
else
next_state = S0;
S1:
//register state if (counter_sec == 0)
always @(posedge clk, negedge reset_n) begin next_state = S2;
if (~reset_n) else
current_state <= S0; next_state = S1;
else S2:
current_state <= next_state; if (~Tb )
end next_state = S3;
else
next_state = S2;
S3:
if (counter_sec == 0)
next_state = S0;
else
next_state = S3;
default:
next_state = S0;
endcase
end

VNU - University of Engineering and Technology 10 Faculty of Electronics and Telecommunications

Traffic light

//current_state -> output S2:

always @* begin
begin if (~Tb )
case (current_state) counter_reset = 1;
S0: else
begin counter_reset = 0;
if (~Ta) {La, Lb} = {RED, GREEN};
counter_reset = 1; end
else S3:
counter_reset = 0; begin
{La, Lb} = {GREEN, RED}; if (counter_sec == 0)
end counter_reset = 1;
S1: else
begin counter_reset = 0;
if (counter_sec == 0) {La, Lb} = {RED, YELLOW};
counter_reset = 1; end
else default:
counter_reset = 0; {La, Lb} = 0;
{La, Lb} = {YELLOW, RED}; endcase
end end

VNU - University of Engineering and Technology 11 Faculty of Electronics and Telecommunications

Title

VNU - University of Engineering and Technology 12 Faculty of Electronics and Telecommunications