CCAS.2.
5 Communications
Signals and Systems
QUANTIZATION AND
ENCODING
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Learning Outcomes
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Learning Outcomes
By the end of this session you should be able to:
• Describe how analog signals are converted to digital form.
• Carry out the complete analog-to-digital conversion process
including sample-and-hold, quantization and encoding
processes.
• Appreciate the practical limitations that affect the sampling
and reconstruction of CT signals.
• Understand the impact of quantization which results in loss of
information.
• Be aware of how a CT signal can be reconstructed from its
samples.
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Outline
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Outline
• Introduction
• DT processing of CT signals
• Ideal ADC
• Practical ADC model
• Sample-and-hold process
• Quantization and Encoding
• Digital-to-analog conversion (DAC)
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Introduction
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Recall: Sampling and PAM
• Recall that the previous lecture ended with a practical
application of sampling, namely Pulse Amplitude Modulation.
• We explained that PAM uses rectangular pulses that can be
realized in practice rather than ideal impulse functions.
• We also highlighted that PAM is a discrete analog signal, and not
a pure digital signal since its amplitude has not been discretized.
• In this lecture, we will describe how to convert a discrete analog
signal to a digital signal through quantization and encoding.
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Recall CCAS 2.4: ADC S&H and SAR process
• Also recall the steps in the ADC process discussed in CCAS 2.4:
– An input analog channel is selected to capture input samples.
– Each sample is then kept constant through the sample-and-hold (S/H or
S&H) circuitry.
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Recall CCAS 2.4: ADC SAR process
• The stable signal from the sample-and-hold circuit is then fed to
a successive approximation converter (SAR).
– SAR is one type of an analog-to-digital (A/D) converter.
– The SAR process is responsible for generating the binary code
corresponding to the input analog sample that was captured.
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A digital signal processing (DSP) system
• In the previous lecture, we explained the motivation for
converting analog signals to digital signals.
• The block diagram below depicts a typical DSP system.
– An analog signal is converted to a digital signal in order to apply DSP
techniques.
– The digital signal is subsequently reconstructed back into a (hopefully
enhanced) analog signal.
• The full ADC process comprises an anti-aliasing filter, a sample-
and-hold (S/H) circuit and an A/D converter.
– This lecture focuses on the S/H and A/D (ADC) procedures.
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DT processing of CT signals
Ideal ADC
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An ideal ADC process
• This slide depicts the operations carried out by an ideal ADC.
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An ideal ADC process
• This slide depicts the operations carried out by an ideal ADC.
• The slide essentially provides a visual recap of the sampling process
examined in the previous lecture.
• In the TD, the operation of the ideal ADC is described by:
𝑥 𝑛 = 𝑥𝑐 𝑡 |𝑡=𝑛𝑇 = 𝑥𝑐 𝑛𝑇
• In the FD, the operation of the ideal ADC is described by:
∞
𝑗𝜔
1 2𝜋
𝑋 𝑒 |𝜔=ΩΤ = 𝑋𝑐 (𝑗Ω − j 𝑘)
𝑇 𝑇
𝑘=−∞
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An ideal ADC process – TD view
• The top-left subplot depicts a bandlimited CT analog signal 𝑥𝑐 𝑡 .
• The middle-left subplot shows how 𝑥𝑐 𝑡 is sampled every T seconds and
assigns the value 𝑥𝑐 𝑛𝑇 to the nth sample of the sequence.
– This is referred to as spectrum scaling and periodization.
• The bottom-right subplot depicts the spectrum of the DT sequence 𝑥 𝑛 .
– Once the samples are taken from 𝑥𝑐 𝑡 and stored in memory, the time
scale information is lost.
– Hence, a time-scale normalization has been carried out effectively
“normalizing out” the sampling period by n = t/T.
– The distance between successive samples is now unity and the time
axis has changed from absolute time (t) to normalized time (n).
– The DT sequence 𝑥 𝑛 is now just a sequence of numbers that do not
carry any information about the sampling period T. 14
An ideal ADC process – FD view
• The top-right subplot depicts a bandlimited spectrum 𝑋𝑐 𝑗Ω .
• The middle-right subplot shows how the input spectrum 𝑋𝑐 𝑗Ω has been
scaled by 1/T and subsequently copied at all integer multiples of the
sampling frequency 𝐹𝑠 .
• The bottom-right subplot depicts the spectrum 𝑋 𝑒 𝑗𝜔 of 𝑥 𝑛 .
– The frequency axis is scaled using the relation ω = ΩΤ = 2𝜋 𝐹𝐹 .
𝑠
– This means that the frequency axis is normalized with the sampling
frequency being scaled to a DT frequency of 2π.
– This changes the frequency axis from absolute frequency (F or Ω) to
normalized frequency (f or ω).
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DT processing of CT signals
Practical ADC model
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Practical model for DSP of CT signals
• At the start of this lecture we presented a diagram for a typical DSP system.
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Practical model for DSP of CT signals - ADC
• Recall that a DSP system translates a continuously varying analog signal into a
series of discrete levels.
• We are now going to focus on practical ADC comprising three components:
• An analog low-pass filter (LPF).
• A sample-and-hold (S/H) circuit.
• An analog-to-digital (A/D) converter.
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Practical model for DSP of CT signals - LPF
• Recall that a DSP system translates a continuously varying analog signal into a
series of discrete levels.
• We are now going to focus on practical ADC comprising three components:
• An analog low-pass filter (LPF).
• A sample-and-hold (S/H) circuit.
• An analog-to-digital (A/D) converter.
• We explained in the previous lecture that the purpose of the LPF is to prevent
aliasing (anti-aliasing filter).
• This low-pass anti-aliasing filter is used to bandlimit the input signal to the
folding frequency.
• This filtering is critical since when the filter’s output is sampled, any
frequency components above the folding frequency will result in aliasing
errors causing signal distortion.
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DT processing of CT signals
Sample-and-hold process
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The sample-and-hold (S/H) process
• The figure below illustrates the sample-and-hold process.
• A sample-and-hold circuit has two functions; the first function is the sampling
process, which was discussed in detail in the previous lecture.
• The second function involves the holding operation.
• Following filtering and sampling, the sampled level must be held constant
until the next sample occurs, as shown in the diagram below.
• This is to allow the ADC converter enough time to process the sampled value.
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The sample-and-hold (S/H) process
• This S/H process is repeated at each sampling interval.
• Hence, the role of S/H is to:
– Sample the CT analog signal 𝑥𝑐 𝑡 as quickly as possible.
– Hold the sample value as constant as possible.
• The output of the S/H circuit then has a staircase approximation, as
illustrated in the plot below, given a sinewave as an example.
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Ideal (theoretical) S/H process – Zero-order-hold
• A sample-and-hold process is equivalent to zero-order-hold filtering.
– In zero-order-hold filtering, each sample value is held until the next
sampling instant.
– This is what generates the staircase approximation.
Assuming an ideal (theoretical) S/H process:
• Zero-order-hold in the TD corresponds to convolving the impulse train of
samples with a rectangular pulse of duration exactly equal to the sampling
period.
– The output of the S/H system is thus a weighted sequence of shifted
versions of the impulse response.
• Equivalently in the FD, zero-order hold corresponds to processing the
samples with an approximation to a LPF corresponding to the Fourier
transform of a rectangular pulse.
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Ideal (theoretical) S/H process – Zero-order-hold
• Convolution of an impulse train of
samples with a rectangular pulse
of duration Δ exactly equal to the
sampling period, is expressed as:
𝑦𝑠 𝑡 = (𝑥𝑠 ∗ ℎ)(𝑡)
• Processing the samples with an approximation to a LPF corresponding to
the Fourier transform of a rectangular pulse, is expressed as:
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DT processing of CT signals
Quantization and Encoding
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Basic ADC process – Quantization and encoding
• An analog-to-digital (A/D) converter is a physical device that converts an
analog quantity (voltage, current) at its input, to a binary code at its output.
• The ADC is the device that carries out both quantization and encoding.
– By encoding we are referring to binary coding.
– Modern ADCs typically have built-in S/H circuits too.
• The left plot in the figure below depicts the output from the S/H process.
– While the steps on the staircase are discrete, they are not quantized.
• Quantization assigns the input sample to a discrete level while encoding
generates the binary word corresponding to the assigned level.
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ADC – Quantization process
Quantizer
input-output
characteristic
Allocation of
levels in a 3-
bit quantizer
Quantizer
error function
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ADC – Quantization process
• The function of a quantizer is to:
– Define a range of input (analog) values.
– Divide the range into discrete (quantization) levels and intervals.
– Decide within which interval the input sample lies.
• A N-bit quantizer can represent 2𝑁 different levels (and thus numbers).
– The more bits used to represent a sampled value (resolution), the more
accurate the representation of the analog value by its digital equivalent.
– A uniform quantizer divides the input amplitude range into 2𝑁
quantization intervals of equal width Δ.
– Δ, is known as the quantization step.
• All values that fall within each quantization interval are represented by a
single value.
– Hence, quantization always results in loss of information.
• The coder then generates the binary word corresponding to the assigned
quantization level.
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ADC – Quantization process: Example
• Consider an ADC with a 2-bit quantizer, thus four discrete levels.
• In the figure below, the original analog waveform is shown in light gray.
• The blue staircase signal on the left shows the S/H output before the ADC.
• The blue staircase signal on the right shows the signal after quantization.
• Observe that all steps within an interval on the left have been assigned
(“pushed”) to a single value, in this case, according to a rounding process.
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Quantization noise or error
• Since quantization approximates each input sample to a predefined fixed
amplitude, there will be an error in the representation of each sample.
– This is known as quantization noise or quantization error.
• If the sampling theorem is satisfied and hence no aliasing error is present:
We can measure the quantization error by quantizing the CT signal 𝑥𝑐 𝑡 , as
shown in the graph below.
Δ
• The quantization error is then given by: 𝑒𝑐 𝑡 = 𝑡, −𝜏 ≤ 𝑡 ≤ 𝜏
2𝜏
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Signal-to-quantization-noise-ratio (SQNR)
• The universal performance metric for a quantizer is the signal-to-
quantization-noise-ratio (SQNR).
• For most signals of practical interest, it can be shown that the SQNR in dB) is
given by:
𝑆𝑄𝑁𝑅(𝑑𝐵) = 10 log10 𝑆𝑄𝑁𝑅 = 6.02𝑁 + 1.76
• This equation tells us that for every additional bit of resolution in the
quantizer, we gain an additional 6 dB in the SQNR performance.
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Digital-to-analog conversion
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DAC: Reconstructing the analog signal
• The block diagram of a DSP system shown at the start of this
lecture illustrated a DAC process after the DSP.
• This digital-to-analog conversion (DAC) process can be used to
reconstruct the original (or an enhanced) analog waveform.
• A reconstruction filter is required to smooth out the DAC output.
– Such a filter eliminates the higher frequency content that results from the
fast transitions of the staircase approximation.
• Details of this process, however, are beyond the scope of this
course.
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DAC: S/H Reconstruction
j
1 1/2
0 F0 =0.025Hz
−1
0 20 40 60 80 t (sec) 0 F (Hz)
(a)
j
1 1/2
−1
0 20 40 60 80 t(sec) −0.4 −0.2 0 0.2 F (Hz)
(b)
1 1/2
j
j
0
−1
0 20 40 60 80 t (sec) −0.2 0 0.2 F (Hz)
(c)
j
1 1/2
−1
0 20 40 60 80 t (sec) 0 F (Hz)
(d) 34
DAC: S/H Reconstruction
• The previous slide illustrates the practical reconstruction of a sinusoidal signal.
• A CT signal 𝑥𝑐 𝑡 is discretized to the DT signal 𝑥[𝑛].
• A S/H process then converts 𝑥[𝑛] to a staircase signal 𝑥𝑆𝐻 [𝑡].
– This signal has a discrete, aperiodic spectrum.
– The S/H process scales the magnitude of each input frequency component
by the since function and introduces a time delay of T/2 seconds.
• A reconstruction filter subsequently removes all frequency components
outside the Nyquist interval and scales the input amplitude by T.
– This yields the final reconstructed signal 𝑥𝑟 [𝑡].
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Summary
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Summary
• We showed how to determine the time-domain sequence and
frequency-domain spectrum of a DT signal from that of the
original CT signal through an ideal ADC process.
• We demonstrated how the sample-and-hold process leads to a
staircase approximation of the original, CT analog signal.
• We described how quantization and encoding translates the
staircase approximation into binary words that represent the
amplitude of the analog input at each of the sample times.
• We explained how an ADC converter must take samples of the
incoming analog data often enough to catch all the relevant
fluctuations in the signal amplitude.
• We presented a brief overview of digital-to-analog conversion.
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Reading
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Essential Reading
• From the textbook “Chaparro & Akan: Signals and systems
using MATLAB”:
– Chapter 8: 8.3
• From the textbook “Manolakis & Ingle: Applied Digital Signal
Processing”:
– Chapter 6: 6.5
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