Unit 2

Pheperials and Interfacing with 8086: Memory Interfacing, Interfacing I/O ports:
Programmable Peripheral Interface 8255 & Modes of Operation, ADC, DAC, and Stepper
Motor Interfacing, Programmable Timer 8253- Operations and Interfacing, Programmable
Interrupt Controller 8259, Communication Interface 8251 USART, DMA Controller 8257.
2.1 Memory Interfacing
Memory is an integral part of a microcomputer system. There are two main types of memory.

(i) Read only memory (ROM): As the name indicates this memory is available only for reading
purpose. The various types available under this category are PROM, EPROM, EEPROM which
contain system software and permanent system data.

(ii) Random Access memory (RAM): This is also known as Read Write Memory. It is a volatile
memory. RAM contains temporary data and software programs generally for different
applications.

While executing particular task it is necessary to access memory to get instruction codes and
data stored in memory. The microprocessor should be able to read from or write into the
specified register. The basic concepts of memory interfacing involve three different tasks such
as selection of the required chip, identify the required register and enable the appropriate
buffers.

Memory device must contain address lines, Input, output lines, selection input and control input
to perform read or write operation. All memory devices have address inputs that select memory
location within the memory device. These lines are labelled as AO...... AN.

The number of address lines indicates the total memory capacity of the memory device. A 1K
memory requires 10 address lines A0-A9. Similarly, a 1MB requires 20 lines A0-A19 (in the
case of 8086).

The memory devices may have separate I/O lines or a common set of bidirectional I/O lines.
Using these lines data can be transferred in either direction.
Whenever output buffer is activated, the data is read and whenever input buffers are activated
the data is written. These lines are labelled as I/O ... I/On or DO .............Dn.

The size of a memory location is dependent upon the number of data bits. If the numbers of
data lines are eight, then 8 bits or 1 byte of data can be stored in each location. Similarly, if
numbers of data bits are 16, then the memory size is 2 bytes. For example, 2K x 8 indicates
there are 2048 memory locations and each memory location can store 8 bits of data.

Memory devices may contain one or more inputs which are used to select the memory device
or to enable the memory device. This pin is denoted by CS (Chip select) or CE (Chip enable).
When this pin is at logic '0' then only the memory device performs a read or a write operation.
If this pin is at logic ‘1’ the memory chip is disabled. If there are more than one CS input, then
all these pins must be activated to perform read or write operation.

All memory devices will have one or more control inputs. When ROM is used, OE (output
enable) pin allows data to flow out of the output data pins. To perform this task both CS and
OE must be active. A RAM contains one or two control inputs. They are R /W or RD and WR.
If there is only one input R/W then it performs read operation when R/W pin is at logic 1. If it
is at logic 0 it performs write operation.

MEMORY INTERFACE USING RAMS, EPROMS AND EEPROMS

The general procedure of static memory interfacing with 8086 is briefly described as
follows:

1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit
bank is called ‘odd address memory bank’ and the lower 8-bit bank is called ‘even address
memory bank’.

2. Connect available memory address lines of memory chips with those of the microprocessor
and also connect the memory RD and WR inputs to the corresponding processor control
signals. Connect the 16-bit data bus of the memory bank with that of the microprocessor 8086.

3. The remaining address lines of the microprocessor, BHE and A0 are used for decoding the
required chip select signals for the odd and even memory banks. CS of memory is derived from
the O/P of the decoding circuit.

The address map of the system should be continuous as far as possible, i.e. there should be no
windows in the map. A memory location should have a single address corresponding to it, i.e.
absolute decoding should be preferred, and minimum hardware should be used for decoding.
Mostly, linear decoding is used to minimize the required hardware.
Example problem on memory interfacing with 8086
2.2 Interfacing I/O Ports:
2.3 Programmable Peripheral Interface (PPI) 8255 & Modes of Operation
 8255 is a widely used, programmable, parallel I/O device.
 It can be programmed to transfer data under various conditions from simple I/O to
interrupt I/O.
INTEL introduced this programmable peripheral interface (PPI) chip 8255A for interfacing
peripheral devices to the 8085 system. This versatile chip 8255A is used as a general purpose
peripheral device for parallel data transfer between microprocessor and a peripheral device by
interfacing the device to the system data bus. The PPI has three programmable I/O ports viz.,
Port A, Port B and Port C each of 8 bit width. Port C can be treated as two ports – Port C upper
(PC7-4) and Port lower (PC3 – 0) and these two can be independently programmed as INPUT
or OUTPUT ports also.
Salient Features

 It is a general purpose programmable I/O device which is compatible with all INTEL
processors and also most other processors.
 It provides 24 I/O pins which may be individually programmed in two groups.
 This chip is also completely TTL compatible.
 It is available in 40 pin DIP and 44 pin plastic leaded chip carrier (PLCC) packages.
 It has three 8 bit ports. Port A, Port B and Port C. Port C is treated as two 4 bit ports
also.
 This 8255 is mainly programmed in two modes (a) the I/O mode and (b) The bit set/reset
mode (BSR) mode. The I/O mode is further divided into three modes: Mode 0, Mode
1, and Mode 2.
 An 8-bit control resister is used to configure the modes of 8255. There is also another
8-bit port called control port, which decides the configuration of 8255 ports. This port
is written by the microprocessor only.

2.3.1 PIN CONFIGURATION OF 8255:

 D0-D7 (Data Bus): Bidirectional, tri-state, data bus lines connected to the system data
bus. They are used to transfer data and control word from microprocessor to 8255 or
receive data or status word from 8255 to 8085.
 PA0-PA7(PortA): These 8-bit bidirectional I/O pins are used to send or receive data
from O/P or I/P device.
 PB0-PB7(Port B): These 8-bitbidirectional I/O pins are used to send or receive data
from O/P or I/P device.
 PC0- PC7(port C): These 8-bit bidirectional I/O pins are divided into two groups PCL
(PC0- PC3) and PCU (PC4- PC7). These groups can individually transfer data in or out
when programmed I/O. When programmed in bidirectional or handshake modes these
bits are used as handshake signals.
 RD’ (Read): MPU or CPU reads data in the ports or the status word through data buffer.
 WR’ (Write): MPU or CPU writes data in the ports or the control register through data
Buffer.
 CS’ (Chip Select): It is an active below input which can be used to enable 8255for data
transfer operation between CPU (MPU) and 8255.
 RESET: It is an active high input used to reset 8255. When reset input is high, the
control register is cleared and all the ports are set to the input mode. Usually
RESETOUT signal from 8085 is used to reset 8255.
 A0&A1: These input signals along with RD’, WR’ inputs control the selection of
control / status word registers or one of three ports.
2.3.2 BLOCK DIAGRAM OF 8255:

Data Bus buffer- Tri-state bidirectional buffer is used to interface the internal data bus of 8255
to the system data bus. Output data from the MPU to the ports or control register and the input
data to the MPU from the ports or status register are all pushed through the buffer.

Control Logic- This block accepts control bus signals as well as inputs from the address bus
and issues commands to the individual group control blocks (Group A Control and Group B
Control) as shown in Fig.2.

Group A Control and Group B Control- Group A control block controls PortA and PC7-
PC4.Group B controls block controls Port Band PC3- PC0.

PortA-This has 8-bit latched and buffered output and an 8-bit input latch. It can be programmed
in three modes:

Mode 0: Simple I/O mode

Mode 1: I/O with Handshaking mode

Mode 2: Bidirectional data transfer mode.

Port B-This has 8-bit I/O latch/buffer and an 8-bit data input buffer. It can be programmed in
mode 0 or mode 1.

Port C-This has 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C can be
splitted into two parts and each bit can be used as control signals for Port A and Port B in
handshake mode. It can be programmed for BSR (Bit Set / Reset mode) operation.

2.3.3 Modes of Operation:

1. BSR mode

2. I/O mode

 Mode 0: Simple I/O mode

 Mode 1: I/O with Handshaking mode
 Mode 2: Bidirectional data transfer mode

1. BSR (Bit Set/Reset) Mode:

Individual bits of Port C can be set or reset by sending out a single OUT instruction to the
control register. When Port C is used for control/status operation, this feature can be used to
set or reset individual bits. For BSR mode control word is given below.

A BSR word is to be written for each bit that is to be set or reset. The BSR word can also be
used for enabling or disabling the interrupt signals generated by Port c when 8255 is
programmed for mode 1or mode 2 operations.
2. I/O mode

Mode 0: Basic Input/output

This mode provides simple input and output operations for each of the three ports. Data is
simply written to or read from a specified port.

Basic functional definition in mode 0:

 There are two 8-bit ports (A and B) and two 4-bit ports [C (lower)] and [C (upper)].
 Any port can be an input port or an output port.
 Outputs are latched.
 Inputs are not latched.
 16 different input/output configurations are possible in this mode

Mode1: Strobed Input/ Output

It provides means for transferring I/O data to or from a specified port in conjunction with
strobes or hand-shaking signals. Port A and port B use the lines on port C for handshaking
signals.

Basic functional definition in mode1:

 There are two groups (Group A and B).

 Each group contains one 8-bit data port and one 4-bit control data port.
  The 8-bit data port can be either an input port or an output port. Both inputs and
outputs are latched.
 The4-bit port is used for control as well as for status of the 8-bit data port.

Mode 2: Strobed Bidirectional Bus

This functional configuration provides a means for communicating with a peripheral device or
Structure on a single 8-bit bus for both transmitting and receiving data. Handshaking signals
are provided to maintain a proper bus flow discipline. Interrupt generation and enable/disable
Functions are also available.

Basic functional definition in mode 2 (used in Group A only):

 There is one 8-bit bidirectional bus port (port A) and a 5-bit control port (port C)
 Both inputs and outputs are latched.
 The 5-bit control port (port C) is used for control as well as for status of the 8-bit
bidirectional bus port (port A).

2.4. ADC, DAC, and Stepper Motor Interfacing

2.4.1 Analog to Digital Converter (ADC) Interfacing

 The ADC is an input device to microprocessor, that sends an initializing signal to the
ADC to start the analog signal to digital conversion process. The start of conversion
signal is a pulse of a specific duration.
 The process of analog to digital conversion is a slow process and the processor has to
wait for the digital data till the conversion is over.
 After the conversion, the ADC sends the End of Conversion (EoC) signal to inform the
processor about it and the result is ready at the output buffer of the ADC. The tasks of
issuing SOC pulse to ADC, reading EOC signal from the ADC and reading the digital
output of the ADC are carried out by the CPU using 8255 I/O ports.
 The time taken by the ADC to calculate the equivalent digital data output from the
moment of the start of conversion is called conversion delay of the ADC
 It may range anywhere from a few microseconds, in case of fast ADCs, to even a few
hundred milliseconds in case of slow ADCs.
 Selection of ADC depends on the speed, resolution, cost etc
 The ADCs available in the market use different conversion techniques for the
conversion.
 Successive approximation and dual slope integration techniques are the most popular
techniques used in the integrated ADC chips
 Irrespective of the techniques used for conversion, general algorithm for ADC
interfacing contains the following steps.
1. Ensure the stability of analog input, applied to the ADC.
2. Issue Start of Conversion (SOC) pulse to ADC
3. Read End of Conversion (EOC) signal to mark the end of conversion process
4. digital data output of the ADC as equivalent digital output
 The ADC chips 0808 and 0809 are 8-bit CMOS, successive approximation converters.
 Successive approximation technique is of the fastest technique used for the process of
analog to digital conversion.
 The conversion delay is 100μs at a clock frequency of 640 KHz, which is quite low as
compared to other converters.
 These converters internally have a 3:8 analog multiplexers so that at a time eight
different analog inputs can be connected to the chips.
 Out of these eight inputs only one can be selected for conversion by using address lines
A, B C..
 Figure: Block Diagram of ADC 0808/0809

Figure: Pin Diagram of ADC 0808/0809

Q. Interface ADC 0808 with 8086 using 8255 ports. Use Port A of 8255 for transferring digital
data output of ADC to the CPU and Port C for control signals. Assume that an analog input is
present at I/P 2 of the ADC and a clock input of suitable frequency is available for ADC. Draw
the schematic and write required ALP
Interfacing diagram

 The analog I/P I/P2 is used and therefore the address pins A, B, C should be 0,1,0
respectively to select I/P 2. The OE and ALE pins are at +5V to select the ADC and
enable the outputs
 PCU acts as the input port to receive the EOC signal and PCL acts as the output port to
send SOC to ADC
 PA acts as a 8-bit input data port to receive the digital data output from the ADC

ALP
2.4.2 Interfacing Digital to Analog Converters (DAC)

 The DAC converts binary numbers into their equivalent analog voltages.
 The DAC finds applications in areas like digitally controlled gain, motor speed controls,
programmable gain amplifiers, etc.
 The DAC 0800 is a monolithic 8-bit DAC manufactured by National semiconductor
 It has settling time around 100ms and can operate on a range of power supply voltages,
i.e. from 4.5 v to +18 v. Usually V+ is 5v or +12 v
 The V– pin can be kept at a minimum of -12V

Figure: Pin diagram of DAC 0808

Q. Write an ALP to generate a triangular wave of frequency 500 Hz using the interfacing
circuit shown below. The 8086 system operates at 8MHz. The amplitude of the triangular
wave is +5V
  The Vref+ should be tied to +5v to generate a wave of +5V amplitude
 The required frequency of the output is 500Hz. i.e the period is 2 ms
 Assuming the wave to be generated symmetric, the waveform will rise for 1 ms and fall
for 1 ms. This will be repeated continuously.

ALP

2.4.3 Stepper motor interface

 A stepper motor is a device used to obtain an accurate position control of rotating shafts
 It employs rotation of its shaft in terms of steps rather than continuous rotation as in
case of AC or DC motors
 To rotate the shaft of the stepper motor, a sequence of pulses is applied to the windings
of the stepper motor in a proper sequence
 The number of pulses required for one complete rotation of the shaft of the stepper
motor is equal to its number of internal teeth on the rotor
 The stator teeth and the rotor teeth lock with each other to fix a position of the shaft.
 With a pulse applied to the winding input, the rotor rotates by one tooth position or an
angle x
 X=3600/no. of rotor teeth
 After the rotation of the shaft through angle x, the rotor locks itself with the next tooth
in the sequence on the internal surface of stator
 Fig below shows the internal schematic of a four winding stepper motor. Stepper motors
have been designed to work with digital circuits. Binary level pulses of 0-5v are
required at its winding inputs to obtain the rotation of shafts
 The sequence of pulses can be decided, depending upon the required motion of the
shaft.
ALP

2.5. Programmable Timer 8253- Operations and Interfacing

It is always possible to generate accurate time delays using the microprocessor system by using
software loop programs. But that will waste the precious time of CPU. Hence INTEL
introduced the chips 8253/8254 which is a hardware solution for the problem of generating
accurate time delays. These chips can be used for applications such as a real-time clock, event
counter, a digit alone shot, a square wave generator and also as a complex wave form generator.
Salient Features
 8254 is an upgraded version of 8253 and they are pin-compatible.
 8254 can operate with higher clock frequency ranging from DC to 8 MHz and 10 MHz,
whereas the 8253 can operate with clock frequency from DC to 2 MHz.
 8254 includes a status read-back command that can latch the count and the status of the
counters. This command is not available in 8253.
 8253 uses N-MOS technology whereas 8254 uses H-MOS technology.
 The chips are packaged in 24 pin DIP and requires a single +5V DC power supply.
 Three identical 16 bit counters that can operate independently in any of the six modes
are available. The counters are down counters.
 These chips are compatible with all INTEL and most of the other microprocessors.
 To operate a counter, a 16-bit count is loaded in its register and on command beings to
decrement the count until it reaches 0. At the end of the count, it generates a pulse that
can be used to interrupt the microprocessor.
 The counters can be programmed for either binary or BCD count.
 The read-back command of 8254 allows the user to check the count value and current
status of the counter.

PIN CONFIGURATION OF 8253/8354: The chips 8253/54 is packaged in a 24 pin DIP and
require a single +5V power supply. The pin diagram is shown in Fig. The description of each
pin is given below.
BLOCK DIAGRAM OF 8253/8254

The block diagram of the Programmable Interval Timer is shown in Fig. The block diagram
includes three counters - Counter 0, Counter 1 and Counter 2, a data bus buffer, read/write
control logic and a control word register. Each counter has two input signals CLOCK and
GATE and one OUTPUT signal-out.
Data Bus Buffer

This tri-state bidirectional 8-bit buffer is used to interface the 8253 to the system bus. Data is
transmitted or received by the buffer upon execution of INPUT or OUTPUT CPU instructions.
The data bus buffer has three basic functions. They are

i. Programming the MODES of the 8253.

ii. Loading the count registers and

iii. Reading the count values.

Read/Write Logic

The read/write logic accepts inputs from the system bus and in turn generates control signals
for overall device operation. It is enabled or disabled by so that no operation can occur to
change the function unless the device is selected by the system logic.

RD: A low on this pin informs the 8253 that the CPU is inputting data in the form of counters
value.

WR: It is an active low pin. A low on this pin informs the 8253 that the CPU is outputting data
in the form of mode information or loading counters.

A0, A1: These two lines are address lines used to select one of the three counters and the control
word register as shown in the table for mode selection.

CS (Chip Select): It is an active low pin. A low on this input enables 8253. No read or write
will occur unless the device is selected. The input has no effect on the actual operation of the
counters.

CONTROL WORD REGISTER:

 This register is selected when A0, A1 are at logic 1. It then accepts the information
from the data bus buffer and stores it in a register.
 The information stored in this register controls the operation MODE of each counter,
selection of binary or BCD counting and the loading of each count register.
 The control word register can only be written to into, but no read operation is possible.
Counter 0, Counter 1, Counter 2

 These three functional blocks are identical in operation. Each counter consists of a
single 16 bit, pre-settable DOWN counter.
 The counter can operate in either binary or BCD and its input, gate and output are
configured by the selection of modes stored in the control word register.
 The counters are totally independent. The counter can be read by a simple READ
operation for event count applications.

Operational Description

 The complete functional operation of 8253 is programmed by the system software.

 A set of control words must be sent out by the CPU to initialize each counter of
8253/8254 with the desired MODE.
 Once programmed, the 8253 is ready to perform whatever timing tasks it is assigned to
perform.

The actual counting operation of each counter is totally independent and additional logic is
provided on-chip so that the usual problems associated with efficient monitoring and
management of external, asynchronous events or rates to the micro computer system have been
eliminated.

Each counter of 8253/54 is individually programmed by writing a control word into control
word register. The control word register is shown in Figure below. The different bits of this 8
bit register are either set or reset for the operation of the counters. The various options are given
below
Refer solved problem 6.1 and 6.2 from text advanced mp and peripherals KM bhurchandi

2.6 Programmable Interrupt Controller 8259 PIC

There is an absolute need of this Programmable Interrupt Controller for Interfacing I/O devices
to the microprocessor. The 8085 processor has 5 interrupt lines namely, Trap, RST 7.5, RST
6.5, RST 5.5 and INTR. So, we can interface five I/O devices, which can perform the interrupt
driven data transfer safely.

But, suppose we wish to connect more than five I/O devices, to the microprocessor, then we
may have to connect more than one I/O device to the interrupt lines. This will affect the
interrupt driven data transfer and the microprocessor has to perform polling. i.e, it has to check
each device, which is in need of interrupt service.

This polling has the dis-advantage of long time and slow interrupt response. Hence to
overcome all these problems, INTEL introduced the 28 pin DIP chip -8259. This device accepts
interrupt requests from as many as 8 devices independently and as many as 64 I/O devices by
cascading method.

Salient Features

 INTEL 8259 is a single chip programmable interrupt controller which is compatible

with 8085, 8086 and 8088 processors.
 It is a 28 pin DIP IC with N-MOS technology and requires a single +5 DC supply.
 It handles up to eight vectored priority interrupts for the CPU and cascadable for up to
64 vectored priority interrupts without the need of any additional circuitry.
 when two 8259s are cascaded through cascade lines the first 8259 will act as master
and the second 8259 will act as a slave.
BLOCK DIAGRAM OF 8259
The block diagram of programmable interrupt controller is shown in Fig. below. The block
diagram consists of eight sub units. They are Control logic, Read/write logic, Data bus buffer.
Three register (IRR, ISR and IMR), 5 priority resolver and cascade buffer. The functions of
each unit are explained below

Interrupt Request Register (IRR) & Interrupt Service Register (ISR) The interrupts at the
IR input lines are handled by two registers in cascade, the Interrupt Request Register (IRR) and
the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting
service; and the ISR is used to store all the interrupt levels which are being serviced.

Priority Resolver This logic unit determines the priorities of the bits set in the IRR. The
highest priority is selected and strobed in to the corresponding bit of the ISR during pulse.

Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt lines. The
IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request
lines of lower priority.
Control Logic This unit has two pins. INT (Interrupt) as an output pin and (interrupt
acknowledge) as an input pin. The INT is connected to the interrupt pin of the microprocessor
unit. Whenever an interrupt is noticed by the CPU, it generates signal.

Cascade Buffer This function block stores the IDs of all 8259A are used in the system. The
associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are
inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the
interrupting slave device onto the CAS0 –2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data Bus during the next one or two consecutive
INTA pulses.

WORKING OF 8259

 The 8259 accepts interrupt requests from any one of the 8 I/O lines (IR0 - IR7). Then
it ascertains the priority of the interrupt lines. Then it ascertains the priority of the
interrupt lines.
 The sequence of steps that occur when an interrupt request line of 8259 goes high is as
follows.
 The 8259 accepts the requests on IR0 - IR7 in IRR. Then it checks the contents of IMR
whether that request is masked or not.
 The 8259, then checks ISR to know the interrupt levels that are being currently serviced.
After this 8259 sends a high INT to 8085 processors. Normally, it is the job of the
priority resolver to check the contents of IRR, IMR and ISR and decide whether to
activate INT output of 8259 or not.
 Now 8085 processor responds by suspending the program flow at the end of the current
instruction and makes low.
 On receiving, 8259 sends code for CALL to the microprocessor on D7-0 bus.
 This code for CALL in IR register of 8259 causes the 8085 to issue two more signals.
When goes low the second time, 8259 places LSB of ISS address on the data bus. When
goes low the third time, 8259 places the MSB of ISS address on the data bus.
 Now, the microprocessor branches to the ISS after saving the contents of program
counter on the stack top.
 After finishing the ISS, the control returns to the main program by popping the top of
stack to PC.
2.7. Communication Interface 8251 USART

The 8251 is a programmable chip designed for synchronous and asynchronous serial data
communication. USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is the
key component for converting parallel data to serial form and vice versa Two types of serial
data communications are widely used -Asynchronous Communication and synchronous
Communication.
SIGNAL DESCRIPTION OF 8251

D 0 to D 7 (l/O) This is bidirectional data bus which receives control words and transmits data
from the CPU and sendsstatus words and received data to CPU.

RESET (Input) A "High" on this input forces the 8251 into "reset status." The device waits
for the writing of "modeinstruction." The min. reset width is six clock inputs during the
operating status of CLK.

CLK (Input) CLK signal is used to generate internal device timing. CLK signal is independent
of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and
TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.

WR (Input) This is the "active low" input terminal which receives a signal for writing transmit
data and control wordsfrom the CPU into the 8251.

RD (Input) This is the "active low" input terminal which receives a signal for reading receive

data and status wordsfrom the 8251.

C/D (Input) This is an input terminal which receives a signal for selecting data or command
words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be
accessed. If C/D = high, commandword or status word will be accessed.

CS (Input) This is the "active low" input terminal which selects the 8251 at low level when
the CPU accesses.

TXD (output) This is an output terminal for transmitting data from which serialconverted data
is sent out. The device is in "mark status" (high level) after resetting or during a status when
transmit is disabled. It is also possible to set the device in "break status" (low level) by a
command.

TXRDY (output) This is an output terminal which indicates that the 8251is ready to accept a
transmitted data character. Butthe terminal is always at low level if CTS = high or the device
was set in "TX disable status" by a command. Note: TXRDY status word indicates that transmit
data character is receivable, regardless of CTS or command. If the CPU writes a data character,
TXRDY will be reset by the leading edge or WR signal.
TXEMPTY (Output) This is an output terminal which indicates that the 8251 has transmitted
all the characters and had no data character. In "synchronous mode," the terminal is at high
level, if transmit data characters are no longer remaining and sync characters are automatically
transmitted. If the CPU writes a data character, TXEMPTY will be reset by the leading edge
of WR signal.

TXC (Input) This is a clock input signal which determines the transfer speed of transmitted
data. In "synchronous mode," the baud rate will be the same as the frequency of TXC. In
"asynchronous mode", it is possible to select the baud rate factor by mode instruction. It can
be 1, 1/16 or 1/64 the TXC. The falling edge of TXC sifts the serial data out of the8251.

RXD (input) This is a terminal which receives serial data.

RXRDY (Output) This is a terminal which indicates that the 8251 contains a character that is
ready to READ. If the CPU reads a data character, RXRDY will be reset by the leading edge
of RD signal. Unless the CPU reads a data character before the next one is received completely,
the preceding data will be lost. In such a case, an overrun error flag status word will be set.

RXC (Input) This is a clock input signal which determines the transfer speed of received data.
In "synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous
mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64
the RXC.

SYNDET/BD (Input or output) This is a terminal whose function changes according to mode.
In "internal synchronous mode." this terminal is at high level, if sync characters are received
and synchronized. If a status word is read, the terminal will be reset. In "external synchronous
mode, "this is an input terminal. A "High" on this input forces the 8251 to start receiving data
characters.

In "asynchronous mode," this is an output terminal which generates "high level"output upon
the detection of a "break" character if receiver data contains a "low-level" space between the
stop bits of two continuous characters. The terminal will be reset, if RXD is at high level. After
Reset is active, the terminal will be output at low level

DSR (Input) This is an input port for MODEM interface. The input status of the terminal can
be recognized by theCPU reading status words.
DTR (Output) This is an output port for MODEM interface. It is possible to set the status of
DTR by a command.

CTS (Input) This is an input terminal for MODEM interface which is used for controlling a
transmit circuit. The terminal controls data transmission if the device is set in "TX Enable"
status by a command. Data is transmittable if the terminal is at low level.

RTS (Output) This is an output port for MODEM interface. It is possible to set the status RTS
by a command

CONTROL WORDS

There are two types of control word.

1. Mode instruction (setting offunction)
2. Command (setting ofoperation)
MODE INSTRUCTION

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait
for write" at either internal reset or external reset. That is, the writing of a control word after
resetting will be recognized as a "mode instruction." Items set by mode instruction are as
follows:

 Synchronous/asynchronous mode
 Stop bit length (asynchronous mode)
 Character length
 Parity bit
 Baud rate factor (asynchronous mode)
 Internal/external synchronization (synchronous mode)
 Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figure 3.3.2. In the case of synchronous
mode, itis necessary to write one-or two byte sync characters. If sync characters were written,
a function will be set because the writing of sync characters constitutes part of mode instruction.

COMMAND

Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters. Items to be set by
command are as follows:

• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)
The bit configuration of Command instruction is shown in Figure 3.3.3.
2.8 DMA Controller 8257

It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data
directly to/from memory without any interference of the CPU. Using a DMA controller, the
device requests the CPU to hold its data, address and control bus, so the device is free to transfer
data directly to/from the memory. The DMA data transfer is initiated only after receiving
HLDA signal from the CPU.

The sequences of operations performed by a DMA are

 Initially, when any device has to send data to the memory, the device has to send DMA
request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA signal.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU will relinquish the bus and acknowledges the HOLD request through HLDA
signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the memory interfaced with Microprocessor and I/O devices.
FEATURES OF 8257

 It has four channels that can be used over four I/O devices.
 Each channel has 16-bit address and 14-bitcounter.
 Each channel can transfer data up to64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It operates in 2 modes, i.e., Master mode and Slave mode.

8257 PIN DESCRIPTION

The pin configuration of DMA Controller (8257) is shown in Figure 3.8.1 and the descriptions
are as follows:

DRQ0−DRQ3 These are the four individual channel DMA request inputs, which are used by
the peripheral devices for using DMA services. When the fixed priority mode is selected, then
DRQ0 has the highest priority and DRQ3 has the lowest priority.

DACKo − DACK3 These are the active-low DMA acknowledge lines, which updates the
requesting peripheral about the status of their request by the CPU. These lines can also act as
strobe lines for the requesting devices.
Do − D7 These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to 8257 and
status word from 8257. In the master mode, these lines are used to send higher byte of the
generated address to the latch. This address is further latched using ADSTB signal.

IOR It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data from
the peripheral devices during a memory write cycle.

IOW It is an active low bi-direction tri-state line, which is used to load the contents of the data
bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or terminal
count register. In the master mode, it is used to load the data to the peripheral devices during
DMA memory read cycle.

CLK It is a clock frequency signal which is required for the internal operation of 8257.

RESET This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3 These are the four least significant address lines. In the slave mode, they act as an
input, which selects oneof the registers to be read or written. In the master mode, they are the
four least significant memory address output lines generated by8257.

CS It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. Inthe master mode, it disables the read/write operations to/from 8257.

READY It is an active-high asynchronous input signal, which makes DMA ready by inserting
wait states.

HRQ This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with HOLD
input of the CPU.

HLDA It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to1.

MEMR It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.

MEMW It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.
ADSTB It is a control output line used to split data and address line through Latches.

AEN This signal is used to disable the address bus/data bus.

TC It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.

MARK The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK
output to the selected peripheral device.
Vcc It is the power signal which is required for the operation of the circuit.

INTERNAL ARCHITECTURE OF 8257:

The functional Block Diagram of DMA controller (8257) is shown in Figure 3.8.2 and the
description are as follows: It consists of five functional blocks:

a) Data bus buffer

b) Control logic
c) Read/write logic
d) Priority Resolver
e) DMA channels

Figure: Functional Block Diagram of DMA controller (8257)

Data Bus Buffer: 8-bit Tristate, bidirectional buffer interfaces the internal bus of 8257 with
the external system bus under the control of various control signals.
Read/Write Logic: In the slave mode, the read/write logic accepts the I/O Read or I/O Write
signals, decodes the Ao-A3 lines and either writes the contents of the data bus to the addressed
internal register or reads the selected register depending upon whether IOW or IOR signal is
activated. In master mode, the read/write logic generates the IOR and IOW signals to control
the dataflow to or from the selected peripheral.

Control Logic: The control logic controls the sequences of operations and generates the
required control signals like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the
address lines A4-A7, in master mode.
Priority Resolver: The priority resolver resolves the priority of the four DMA channels
depending upon whether normal priority or rotating priority is programmed.

Register Organization of 8257: The 8257 performs DMA operation over four independent
DMA channels with the following Registers.

DMA Address Register

Each DMA channel has one DMA address register. The function of this register is to store the
address of the starting memory location, which will be accessed by the DMA channel. The
device that wants to transfer data over a DMA channel, will access the block of the memory
with the starting address stored in the DMA Address register.

Terminal Count Registers

Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit
register is used for ascertaining that the data transfer through a DMA channel ceases or stops
after the required number of DMA cycles. After each DMA cycle, the terminal count register
content will be decremented by one and finally it becomes zero after the required number of
DMA cycles are over. The bits 14 and 15 of this register indicate the type of the DMA operation
(transfer).

Mode Set Register

The mode set register is used for programming the 8257 as per the requirements of the system.
The function of the mode set register is to enable the DMA channels individually and also to
set the various modes of operation as shown in Figure 3.8.3.
The bits Do-D3 enable one of the four DMA channels of 8257.If the TC STOP bit is set, the
selected channel is disabled after the terminal count condition is reached, and it further prevents
any DMA cycle on the channel. If the TC STOP bit is programmed to be zero, the channel is
not disabled, even after the counter reaches zero and further request are allowed on the same
channel. The auto load bit, if set, enables channel 2 for the repeat block chaining operations,
without immediate software intervention between the two successive blocks. The extended
write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating them
earlier, which is useful in interfacing the peripherals with different access times.

Status register

The lower order 4-bits of this register contain the terminal count status for the four individual
channels. If any of these bits is set, it indicates that the specific channel has reached the terminal
count condition. The update flag is not affected by the read operation. This flag can only be
cleared by resetting 8257. The update flag is set every time; the channel 2 registers are loaded
with contents of the channel 3 registers. It is cleared by the completion of the first DMA cycle
of the new block. This register can only read.

DMA TRANSFER & OPERATIONS

The 8257 is able to accomplish three types of

operations such as

1.DMA operation

2.Write Operation

3. Read Operation
Operational sequence of 8257 is as follows

 The 8257 request any one of the 8257 DRQ inputs to transfer single byte.
 In response to the request, the 8257 sends HRQ signal to CPU at its HLD input and
waits for acknowledgement at the HLDA input.
 If the DMA controller receives the HLDA signal it indicates that the bus is available
for the transfer.
 The DMA controller generate the read and write commands to transfer the byte from/to
the I/O Device.
 The DACK line of the used channel is pulled down by the DMA controller to I/O device
that requested for DMA transfers.
 The HRQ line is lowered by the DMA controller to indicate the CPU that it may regain
the control of the bus.
 The DRQ must be high until acknowledged.
 In each s4 state, the DRQ lines are sampled and highest priority request is recognized
during next transfer. The HRQ line is maintained active till all the DRQ line go low.