UNIT IV

PERIPHERAL INTERFACING

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Study on need, Architecture, configuration and interfacing, with ICs: 8255, 8259, 8254, 8237, 8251, 8279, -
A/D and D/A converters &Interfacing with 8085& 8051.
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1. Introduction:

Data Transfer Techniques

Data transfer may take place between two devices.

For e.g.
➢ Microprocessor and memory
➢ Microprocessor and I/O device
➢ Memory and I/O device

Classification of data transfer techniques

1. Programmed data transfer
2. Direct Memory Access (DMA)
Programmed data transfer

➢ Data is transferred from the I/O device to the microprocessor or memory.

➢ Data is transferred under the control of the program stored in the program memory of the
microprocessor based system.
➢ This technique of data transfer is normally used if the size of data to be transferred is
small.
Programmed data transfer techniques is classified as
➢ Parallel data transfer
➢ Serial data transfer
➢ Synchronous data transfer
➢ Asynchronous data transfer
➢ Interrupt Initiated data transfer
Comparison of Parallel/ Serial

Parallel Serial

8 bits of data tranferred at a time Only 1 bit of data is transferred at a time

9 lines required to connect two devices 2 lines required to connect two devices
Advantageous over small distances Advantageous over long distances

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 Comparison of Asynchronous/ Synchronous Data Transfer techniques

Asynchronous Synchronous

Used to transfer one character at a time Used to transfer a block of

Start and stop bits are used with each characters at a time
character No start/ stop bits are used
Speed is less Speed is high
Transmitter and receiver can use two Transmitter and receiver share a
separate clock inputs common clock

❖ Interrupt Initiated Data Transfer

• Microprocessor initiates the interrupt mechanism and starts executing the main program.
• I/O device informs the microprocessor that it is ready by generating an interrupt signal.
• Microprocessor services the interrupt by completing the data transfer.

• DMA Controlled Data Transfer

• DMA stands for Direct Memory Access
• used when large amount of data is to be transferred
• Microprocessor does not participate in this type of data transfer
• Data is transferred directly between an I/O device and memory or vice-versa
• Data transfer is controlled by an I/O device or a DMA controller
• DMA data transfer is fast as compared to programmed data transfer

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Describe the internal block diagram of 8255 / PPI .(December 2010) (April 2018)(December 2017)
Explain the functioning of 8255 programmable peripheral interface and its modes. [April/May 2017,
May/June 2016, April/May 2015, Nov/Dec2015,April/May 2011,May/June 2014,May/June
2013,Nov/Dec 2013,May/June 2009]
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. 2.Parallel communication interface (8255)(Programmable peripheral interface)
Definition:
The 8255 is a general purpose programmable I/O device used for parallel data transfer. It can be
programmed to transfer data under various conditions, from simple I/O to Interrupt I/O. It is flexible,
versatile and economical when multiple I/O ports are required.
Functional Block Diagram
The 8255 consists of four sections namely,
• Data bus buffer
• Read/write control logic
• Group A control
• Group B control

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 Figure. Block diagram of 8255 Programmable Peripheral interface.

DATA BUS BUFFER:

• This is a tri-state, bi-directional data bus used to interface the internal data bus of 8255A to the
system data bus of 8085.
• Using IN or OUT instructions, CPU can read or write the data from/to the data bus buffer.
• It can also be used to transfer control words and status information between CPU and 8255A.
•
READ/WRITE CONTROL LOGIC:
• This block controls the chip detection (CS), read (RD) and write (WR) operations.
• It consists of A0 and A1 signals which are generally connected to the CPU address lines A0
and A1 respectively.
• When CS (Chip select) signal goes low, different values of A0 and A1 select one of I/O
ports or control register.

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 Group A and Group B control:
• Group A and B get the Control Signal from CPU and send the command to the individual
control blocks.
• Group A send the control signal to port A and Port C (Upper) PC7-PC4.
• Group B send the control signal to port B and Port C (Lower) PC3-PC0.

PORT A:
• This is a 8-bit buffered I/O latch.
• It can be programmed by mode 0 , mode 1, mode 2 .

PORT B:
• This is a 8-bit buffer I/O latch.
• It can be programmed by mode 0 and mode 1.

PORT C:
• The eight bit ports of PORT C can be used as individual bits or be grouped into two 4 bit
ports. Cupper (Cu) and C Lower (CL).The functions of these ports are defined by writing a control
word in the control register.

Functions of Pin:

The signal description of 8255 is briefly presented as follows

➢ It has 24 I/O programmable pins which can be grouped into three 8 bit parallel ports of Port A,
Port B and Port C.
➢ It is TTL compatible.
PA7-PA0: These are eight port A lines that acts as either latched output or buffered input lines depending
upon the control word loaded into the control word register.
PC7-PC4 : Upper nibble of port C lines. They may act as either output latches or input buffers lines. This
port also can be used for generation of handshake lines in mode 1 or mode 2.

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 PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4 lines.
PB0-PB7 : These are the eight port B lines which are used as latched output lines or buffered input lines in
the same way as port A.
A1-A0: These are the address input lines and are driven by the microprocessor. These address lines A1-A0
are used for addressing any one of the four registers, i.e. three ports and a control word register as given
in table below.

RD : This is the input line driven by the microprocessor and should be low to indicate read operation to
8255.

WR : This is an input line driven by the microprocessor. A low on this line indicates write operation.

CS : This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals,
otherwise RD and WR signal are neglected • In case of 8086 systems, if the 8255 is to be interfaced with
lower order data bus,the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

D0-D7 : These are the data bus lines those carry data or control word to/from the microprocessor.

RESET: A logic high on this line clears the control word register of 8255. All ports are set as input ports
by default after reset.
OPERATING MODES OF 8255
➢ BSR mode
➢ I/O mode

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CONTROL WORD FORMATS:

D7 bit of control word decides the type of mode.

• If it is ‘1’. I/O mode is selected.
• If it is ‘0’. BSR mode is selected

a) BSR (BIT SET/RESET) mode:

• The PORT C can be Set or Reset by sending OUT instruction to the CONTROL registers.
• In BSR mode individual bits of Port C can be used for applications such as on/off switch.
• The control word sets or reset one bit at a time.

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 b) FOR I/O MODE

The mode format for I/O as shown in figure

The I/O mode is divided into three modes mode 0, mode 1, and mode 2 given below
• Mode 0 – Basic I/O mode
• Mode 1 – strobbed I/O mode
• Mode 2 – Bidirectional data transfer mode
Steps to communicate with peripherals through the 8255 .They are
1. Determine the addresses of Port A,B and C and of the control register according to the chip select
logic and address line A0 and A1.
2. Write a control word in the control register
3. Write I/O instructions to communicate with peripherals through ports A, B and C.control word
does not alter any previously transmitted control word with bit D7=1.Thus the I/O operations of Port
A and Port B are not affected by a BSR control word.

I/O MODES:

1) MODE 0 (Simple input / Output):

In this mode , port A, port B are used as two simple 8 bit I/O ports and port C as two 4 bit
ports used as individually (Simply).

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 ➢ Features of mode 0 are:
• Any port can be input or output
• Outputs are latched
• Inputs are not latched
2) MODE 1: (Input/output with Hand shake)

In this mode, input or output is transferred by hand shaking Signals. The handshaking signals are
exchanged between the microprocessor and peripheral prior to data transfer.

➢ Features of mode 1

1. Two ports (A and B) function as 8 bit I/O ports .They can be configured either as input or output
ports.
2. Each port uses 3 lines from port C as handshake signals. The remaining 2 lines of PORT C can be
used for simple I/O operations.

2.1)Input control signal (Mode 1 ):

• STB (Strobe input ) – If this lines falls to logic low level, the data available at 8-bit input port
is loaded into input latches.

• IBF (Input buffer full) If this signal rises to logic 1, it indicates that data has been loaded into
latches, i.e. it works as an acknowledgement. IBF is set by a low on STB and is reset by the rising
edge of RD input.

• INTR (Interrupt request) This active high output signal can be used to interrupt the CPU.
whenever an input device requests the service. INTR is set by a high STB pin and a high at IBF
pin.
➢ INTE is an internal flag that can be controlled by the bit set/reset mode of either PC 4(INTEA)
or PC2(INTEB) as shown in fig
➢ INTR is reset by a falling edge of RD input. Thus an external input device can be request the
service of the processor by putting the data on the bus and sending the strobe signal.

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2.2) Output control signal(Mode 1) :

• OBF (Output buffer full) – This status signal, whenever falls to low, indicates that CPU has
written data to the specified output port. The OBF flip-flop will be set by a rising edge of WR
signal and reset by a low going edge at the ACK input.
• ACK (Acknowledge input) – ACK signal acts as an acknowledgement to be given by an output
device. ACK signal, whenever low, informs the CPU that the data transferred by the CPU to the
output device through the port is received by the output device.
• INTR (Interrupt request ) – Thus an output signal that can be used to interrupt the CPU when
an output device acknowledges the data received from the CPU.INTR is set when ACK, OBF
and INTE are 1. It is reset by a falling edge on WR input. The INTEA and INTEB flags are
controlled by the bit set-reset mode of PC6 and PC2 respectively.

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3) MODE 2 :bi-directional I/O data transfer:

➢ Features of Mode2

• In this mode, Port A can be configured as the bidirectional port and Port B is either in Mode
0 or Mode 1.
• Port A uses 5 signals from Port C as handshake signals for data transfer .The remaining 3
signals from Port C can be used either as simple I/O or as handshake for Port B.
.

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3. Serial Communication Interface (8251)

(Programmable Communication Interface)

Introduction:
The basic concepts concerning the serial I/O mode can be classified into the following categories
1. Interfacing Requirements
2. Alphanumeric codes
3. Transmission format
4. Error checks in data communication
5. Data communication over telephone lines
• Interfacing Requirements

Serial I/O Interfacing

➢ The MPU selects the peripheral through chip select and uses the control signals .Read to receive data
and write to transmit data.
➢ To communicate with alphabetic letters and decimal numbers of the computer into binary, we use
ASCII code of 7 bit 00H to 7FH is assigned to a letter, a decimal number, a symbol or a machine
command.

[30 – 39H 0 to 9 ]
[41H– 5AH A to Z]
[21H – 2FH for various symbols]
[00 - 1FH for machine commands]

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• Transmission format

➢ In synchronous format, receiver and a transmitter are synchronized with the same clock and a
block of character is transmitted along with the synchronization information. This format is
generally used for high speed transmission (more than 20 Kbits/second)

➢ The asynchronous format is character oriented. Each character carries the information of the start
and stop bits. Transmission starts with one start bit(low) followed by a character , and one or two
stop bits (high) .This is also known as framing. It is used in low speed transmission less than
20Kbits/second.

• Communication Modes
According to the direction and simultaneity of data flow, it is classified as
Simplex - Data are transmitted in only one direction.
Example: Transmission from a microcomputer to a printer.
Duplex - Data flow in both direction
• Half Duplex - If the transmission goes one way at a time it is called half duplex.
• Full Duplex – If both transmitting and receiving signals goes simultaneously, it is called full
duplex. Example: Transmission between computers.

• Rate of transmission
The rate at which the bits are transmitted is called bits/second or Baud rate. For example
1200 baud = 1200 bits/second. It indicates1200 bits are transmitted in a second. For 1 bit it
takes 1/1200 =0.83 ms.

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***************************************************************************************
Explain USART (8251) serial communication interface with its functional block diagram.(April
2018)(June 2016)
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Programmable Communication Interface 8251 (USART)/ (Programmable serial interface)

Definition:
The 8251 is a programmable USART (Universal Synchronous Asynchronous Receiver Transmitter)
is designed for Synchronous and Asynchronous serial communication; The 8251 receives parallel
data from the CPU and transmits serial data after conversion. This device also receives serial data
from the outside and transmits parallel data to the CPU after conversion.

The block diagram of 8251 includes five sections:

• Read /Write control logic
• Transmitter section
• Receiver Section
• Data bus buffer
• Modem control

Figure:8251 USART Serial communication Interface

➢ The control logic interfaces the chip with the MPU determines the functions of the chip
according to the control word in its register and monitors the data flow.

➢ The transmitter section converts a parallel word received from the MPU into a serial bits and
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 transmits them over TxD line to a peripheral.

➢ The receiver section receives serial bits from a peripheral converts them into parallel word and
transfers the word to the MPU.

➢ The MODEM control is used to establish data communication through modems over telephone
lines.

1. Transmitter section
➢ The transmitter accepts parallel data from the MPU and converts them into serial data.
➢ It has two registers, A buffer register to hold eight bits and an output register to convert eight
bits into a stream of serial bits.
➢ The MPU writes a byte in the buffer register whenever the output register is empty, the contents
of the buffer register are transferred to the output register.
➢ This section transmits data on the TxD pin with the appropriate framing bits(start & stop).3 output
and 1 input signal are associated with transmitter section.

TXD (Transmit Data)

This is an output terminal for transmitting data from which serial-converted data is sent out.

TXRDY (Transmitter Ready)

This is an output terminal during high indicates that the 8251is ready to accept a transmitted
data character. It can be used either to interrupt the MPU or to indicate the status.

TXEMPTY (Transmitter Empty)

This signal at logic 1 indicates that the 8251 has transmitted all the characters and the output register
is empty. It is reset when a byte is transferred from the buffer to the output register.

TXC (Transmitter clock)

This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it
is possible to select the baud rate factor by mode instruction. It can be 1,16 or 64 the baud.

2. Receiver Section

➢ The receiver accepts serial data on the RxD line from a peripheral and converts them into parallel
data.
➢ The section has two registers, the receiver input register and the buffer register.
➢ When RxD line goes low, the control logic assumes it is a start bit, waits for half a bit time and
samples the line again. If the line is still low, the i/p register accepts the following bits, forms a
character and loads it into the buffer register subsequently. The parallel byte is transferred to the
Microprocessor when requested.
RXD (Receive Data)
The bits are received serially on this line and converted into a parallel byte in the receiver input
register.
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 RXC (Receiver clock)
This clock signal controls the rate at which bits are received by the USART .In asynchronous
mode, the clock can be set to 1,16 and 64 times the baud.

RXRDY (Receiver Ready)

This output signal goes high when USART has a character in the buffer register and is ready to
transfer it to the MPU .This line can be used either to indicate the status or to interrupt the MPU.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode." this
terminal is at high level, if sync characters are received and synchronized.

In "asynchronous mode," this is an output terminal which generates "high level" output upon the detection
of a "break" character if receiver data contains a "low-level" space between the stop bits of two continuous
characters.

3. MODEM Control

.
1. DSR ( Data set ready)
This is an input port for MODEM interface. This is normally used to check if the Data set is ready
when communicating with a modem.
2. DTR ( Data terminal ready)
This is an output port for MODEM interface. It is used to indicate that the device is ready to accept
data when the 8251 is communicating with a modem.
3. CTS ( Clear to send)
This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The
terminal controls data transmission if the device is set in "Tx Enable" status by a command. Data is
transmittable if the terminal is at low level.
4. RTS ( Request to send data)
This is an output port for MODEM interface. It is used to indicate the MODEM that the receiver is
ready to receive a data byte from the MODEM.

4.Read/Write control logic and Registers

This section includes R/W control logic,
➢ six input signals,
➢ control logic and
➢ 3 buffer registers: Data register, control register and status register.
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Control Register
The 16 bit register for a control word consists of two independent bytes. The first byte is called the mode
instruction and the second byte is called the command instruction. This register can be accessed as an
output port when the C/D pin is high.

Status Register
This input register checks the ready status of a peripheral. This register is addressed as an input port when
the C /D is high .It has the same port address as the control register.

Data Buffer
This bidirectional register can be addressed as an input port and an output port when C/D pin is low.

The input signals to the control logic are as follows.

There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. The writing of a control word after
resetting will be recognized as a "mode instruction."
8251 Mode word
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)

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 8251 command word

8251 status word

Pin Description
❖ Initializing the 8251
• To implement serial communication, the MPU must inform 8251 of all details such as mode, baud ,
stop bits, parity etc.,
• Therefore prior to data transfer ,a set of control words must be loaded into the 16 bit control register
of the 8251.The MP must check the readiness of a peripheral by reading the status register.
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 • The control words are divided into two formats: Mode word and command word.
• The mode word specifies the general characteristics of operation (such as baud, parity, number of
stop bits) .The command word enables data transmission and/or reception and the status word
provide the information concerning register status and transmission errors.

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Draw the block diagram of 8279 Keyboard/Display controller and explain how to interface the Hex
Key Pad and 7-segment LEDs using 8279. (December 2017)
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4.Programmable Keyboard/Display controller – 8279

Definition:

A 8279 is a general purpose keyboard display controller that simultaneously drives the display of a
system and interferes a keyboard with the CPU, leaving it free for routine task.

✓ The keyboard is interfaced either in interrupt mode or polled mode.

✓ In the Interrupt mode, the processor is requested service only if any key is pressed, otherwise
the CPU can proceed with its main task.
✓ In the Polled mode, the CPU periodically reads an internal flag of 8279 to check for a key pressed.

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Basic Description of the 8279

DATA BUS (D7-D0)

All data and commands between the microprocessor and 8279 are transmitted on these lines.
RD (read):
Microprocessor reads the data/ status from 8279.
WR (write):
Microprocessor writes the data to 8279
A0:
A high signal on this line indicates that the word is a command or status. A low signal
indicates the data.
RESET:
High signal in this pin resets the 8279. After being reset, the 8279 is placed in the following
modes
• 16 x 8 – bit character display – left entry
• Two key lock out
CS (Chip Select):
A low signal on this input pin enables the communication between 8279 and the
microprocessor.
IRQ (Interrupt Request):
• The interrupt line goes low with each FIFO/sensor RAM reads and returns high if there
still information in the RAM
SL0-SL3:
• The scan lines which are used to scan the key switch or sensor matrix and the displays
digits. These lines can be either encoded (1 of 16) or decoded (1 of 4)

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 RL0-RL7:
• Input return lines which are connected to the scan lines through the keys or sensor
switches. They have active internal pull-ups to keep them high serve as an 8- bit input in the
strobed input mode.
SHIFT:
• It has an active internal pull-up to keep it high until a switch closure pulls it low.
CNTL/STB:
• For keyboard mode, this line is used as a control input and stored like status on a key
closure.
• The line is also the strobed line to enter the data into the FIFO in the strobed input.
OUT A0 – OUT A3, OUT B0 – OUT B3:
• These two ports are the outputs for the 16x4 display refresh registers. These two ports may
also be considered as one 8 – bit port.
• The two 4 – bit ports may be blanked independently.
BD:
This output is used to blank the display digit switching or by a display banking command.

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Explain the working Principle of 8279 Keyboard/Display Controller.(April 2010)(June 2016)
(December 2016)(May 2015)(December 2015)
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Keyboard/Display Controller (8279)

A 8279 is a general purpose keyboard display controller that simultaneously drives the display
of a system and interferes a keyboard with the CPU, leaving it free for routine task.

Functional block diagram of 8279

It consists of four sections
• Keyboard section
• Scan section
• Display section
• CPU Interface section

CPU INTERFACE SECTION:

• This section has bi-directional data buffer (DB0 –DB7), I/O control lines (RD, WR, CS, A0) and
Interrupt Request lines (IRQ).
• The A0 signal determines whether transmit/receive control word or data is used.
• An active high in line IRQ is generated to interrupt the microprocessor whenever the data is available.

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 Figure:8279 keyboard /Display Interface

• It consists of
a) A set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display.

A0 RD WR Operation
0 0 0 MPU writes the data is 8279
0 0 1 MPU reads the data from 8279
1 1 0 MPU writes control word to 8279
1 0 1 MPU read status word from 8279

KEYBOARD SECTION:
• This section has keyboard debounce and control, 8X8 FIFO/sensor RAM, 8 return lines
(RL0 – RL7) and CNTL/STB and shift lines.
• In the keyboard debounce and control unit, keys are automatically debounced and the
keyboard can be operated in two modes.
➢ Two keys lock out
➢ N – key roll over
• The 8X8 FIFO/sensor RAM consists of 8 registers that are used to store eight keyboard
entries.
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 • The return lines (RL0-RL7) are connected to eight columns of keyboard.
• The status of shift and CNTL/STB lines are stored along with the key closure.
SCAN SECTION:
• This section has scan counter and four scan lines (SL0 – SL3).
• These lines are decoded by 4 to 16 decoder to generate 16 scan lines.
• Generally SL0 – SL3 are connected with the rows of a matrix keyboard.

DISPLAY SECTION:
• This section has two groups of outputs lines A0 – A3 and B0 – B3. These lines are used to
send data to display drivers.
• BD line is used blank the display. It also has 16X8 displays RAM.
• The display address register holds the address of the word currently being written or read by
the CPU to or from the display RAM.
• The contents of the registers are automatically updated by 8279 to accept the next data entry by
CPU.
Modes of operations of 8279

1. Input (Keyboard) modes

2. Output (Display) modes

1. Keyboard modes
❖ Scanned keyboard mode with N key rollover
In this mode, each key depression is treated independently. When a key is pressed, the debounce
circuit waits for 2 keyboards scans and then checks whether the key is still depressed. If it is still
depressed, the code is entered in FIFO RAM
❖ Scanned keyboard mode with 2 key lock out.
It prevents 2 keys from being recognized if pressed simultaneously. If two keys are pressed within
a debounce cycle (simultaneously),no key is recognized till one of them remains
closed, and the other is released. The last key that remains depressed is considered as single valid
key depression.

2. Display modes

❖ Left entry mode

The data is entered from the left side of the display unit.

❖ Right entry mode

The first entry to be displayed is entered on the rightmost display.

Programming the Keyboard Interface :

• Before any keystroke is detected, the 8279 must be programmed
• The first 3 bits of the number sent to the control port (11H) select one of the 8 different control
words.

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Command Words of 8279

Keyboard Display mode set

The format of the command word is to select different modes of operation of 8279

Control Word Description

a)000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode

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DD field selects either: 8- or 16-digit display Whether new data are entered to the rightmost or
leftmost display position.

b) Programmable clock (001PPPPP)

The clock for operation of 8279 is obtained by dividing the external clock input signal by a
programmable constant called prescaler.The clock command word programs the internal clock driver.
The code PPPPP, is a prescalar that divides the clock input pin (CLK) to achieve the desired
operating frequency, e.g. 100 KHz requires 010102

(c)Read FIFO/Sensor RAM(010 AI X AAA )

The read FIFO control word selects the address (AAA) of a keystroke from the FIFO buffer
(000 to 111).X - don’t care and AI selects auto-increm(ent for the address

d) Read Display RAM(011 AI AAAA)

This command enables a programmer to read the display RAM data.
The display read control word selects the 4 bit address AAAA points to the 16 byte display RAM
positions that is to be read.

e) Write Display RAM(100 AI AAAA)

The display write control word selects the 4 bit address AAAA points to the 16 byte display
RAM positions that is to be written.. Display. Z selects auto-increment so subsequent writes go to
subsequent display positions.

f) Display with inhibit blanking (1010WWBB)

The display write inhibit control word inhibits writing to either the leftmost 4 bits of the
display (left W) or rightmost 4 bits (right W).BB works similarly except that they blank (turn off) half
of the output pins.

g) Clear Display RAM (1100CCFA)

The clear control word clears the display, FIFO or both Bit F clears FIFO and the display
RAM status, and sets address pointer to 000.
If CC are 00 or 01, all display RAM locations become 00000000.
If CC is 10, --> 00100000, if CC is 11, --> 11111111.

h) End Interrupt/Error mode set(1110E000 )

End of Interrupt control word is issued to clear IRQ pin to zero in sensor matrix mode
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 ➢ Clock must be programmed first. If 3.0 MHz drives CLK input, PPPPP is programmed to
30 or 111102.
➢ Keyboard type is programmed next. The previous example illustrates an encoded
keyboard, external decoder used to drive matrix.
➢ Program the operation of the FIFO.Once programmed never reprogrammed done, until a
procedure is needed to read prior keyboard codes .

**************************************************************************************
Draw and explain the functional block diagram of 8254 Timer and its command word
format.[ May/June 2016, Nov/Dec 2016, May/June 2013, May/June 2009][Dec 2017]
Explain the blocks diagram and modes of the 8254 timer. {Nov/Dec 2015 .Dec 2012,June 2014]

************************************************************************** ***********

5. Programmable Interval Timer (8254/8253)

Definition:

The 8254 is a programmable interval timer/counter is used for the generation of accurate time delays ,
controlling real-time events such as real-time clock, events counter, and motor speed and direction control
under software control.
After the desired delay, the 8254 will interrupt the CPU. This makes microprocessor to be free the
tasks related to the counting process and can execute the programs in memory, while the timer device may
perform the counting tasks. This minimizes the Software overhead on the microprocessor.

Application of 8254:
• Real time clock
• Event-counter
• Digital one-shot
• Programmable rate generator
• Square wave generator
• Binary rate multiplier
• Complex waveform generator
• Complex motor controller

It consists of
• Three independent 16-bit programmable counters (timers)
• a data bus buffer
• Read/Write control Logic
• Control register

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 8254 Functional Block diagram of 8253

DATA BUS BUFFER:

This 3- state, bi-directional, 8-bit buffer is used to interface the 8254 to the system bus.

READ/WRITE LOGIC:

➢ The Read/Write logic accepts inputs from the system bus and generates control signals for
the other functional blocks of the 8254.
➢ A1 and A0 select one of the three contents counters or the control word register to be read
from/written into.
➢ A “low” on the RD input tells the 8254 that the CPU is reading one of the counters.
➢ A “low” on the WR input tells the 8254 that the CPU is writing either a control word or an
initial count.
➢ Both RD and WR are qualified by CS; RD and WR are ignored unless than 8254 has been
selected by holding CS low.

CONTROL WORD REGISTER:

➢ The control word register is selected by the read/write logic when A1, A0=11.
➢ If the CPU then does a write operation to the 8254, the data is stored in the control word
register and is interpreted as a control word used to define the operation of the counters.

25
 ➢ The control word register can only be written to; status information is available with the
Read-Back command.

COUNTER 0, COUNTER 1, COUNTER 2:

➢ Each is a 16 bit down counter

➢ The counters are fully independent. Each counter may operate in a different mode.
➢ Each counter has a separate clock input, count enable (gate) input lines and output lines.
➢ The control word register is not a part of the counter itself, but its contents determine how
the counter operates.

8254 Pin Description

D0 to D7 : read, write, Chip select & Address pins A1 and A0 are connected to Microprocessor
A1, A0 The address inputs select one of the four internal registers for programming, reading, or
writing to a counter.
CLK: The clock input is the timing source for each of the internal counters. It is often connected to
the PCLK signal from the bus controller
CS: Chip Select enables the 8254 for programming, and reading and writing
Gate: The gate input controls the operation of the counter in some modes
OUT: A counter output is where the wave-form generated by the timer is available

26
 Read/Write causes data to be read/written from the 8254 and often connects to the

Each counter is individually programmed by writing a control word, followed by the

initial count.The control word allows the programmer to select the counter, model of operation,
binary or BCD count and type of operation (read/write).
Command word of 8254

Each counter may be programmed with a count of 1 to FFFFH. Minimum count is 1 all modes
except 2 and 3 with minimum count of 2.
Each counter has a program control word used to select the way the counter operates.

If two bytes are programmed, then the first byte (LSB) stops the count, and the second byte
(MSB) starts the counter with the new count.

****************************************************************************************
Explain the various modes of operation of timer interface 8253/8254.[Dec 2013,Dec 2015,Dec 2016]
**************************************************************************************
There are 6 modes of operation for each counter
1. MODE 0: INTERRUPT ON TERMINAL COUNT :
2. MODE 1: Programmable One-Shot:
3. MODE 2: RATE GENERATOR:
4. MODE 3: SQUARE WAVE GENERATOR
5. MODE 4: SOFTWARE TRIGGERED STROBE :
6. MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE):

Modes of operation
27
MODE 0: INTERRUPT ON TERMINAL COUNT:
➢ Mode 0 is typically used for event counting. After the Control Word is written, OUT is initially
low, and will remain low until the Counter reaches zero.
➢ OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written
into the Counter.
➢ GATE = 1 enables counting; GATE = 0 disables counting. GATE has no effect on OUT.
➢ The output becomes a logic 0 when the control word is written and remains there until N plus the
number of programmed counts.

MODE 1: PROGRAMMABLE ONE-SHOT:

➢ OUT will be initially high.
➢ OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will
remain low until the Counter reaches zero.
➢ OUT will then go high and remain high until the CLK pulse after the next trigger.
➢ The Gate input triggers the counter to output a 0 pulse for count clocks. Counter reloaded if
Gate is pulsed again.

MODE 2: RATE GENERATOR:

➢ This Mode functions like a divide-by-N counter. It is typically used to generate a Real Time
Clock interrupt.
➢ OUT will initially be high. When the initial count has decremented to 1, OUT goes low for
one CLK pulse. OUT then goes high again, the Counter reloads the initial count and the
process is repeated.
➢ Mode 2 is periodic, the same sequence is repeated indefinitely. For an initial count of N, the
sequence repeats every N CLK cycles.
➢ GATE = 1 enables counting; GATE = 0 disables counting. If GATE goes low during an
output pulse, OUT is set high immediately.
➢ Counter generates a series of pulses 1 clock pulse wide. The separation between pulses is
determined by the count. The cycle is repeated until reprogrammed or G pin set to 0.

28
MODE 3: SQUARE WAVE GENERATOR
➢ Mode 3 is typically used for Baud rate generation. Mode 3 is similar to Mode 2 except for the
duty cycle of OUT. OUT will initially be high.
➢ When half the initial count has expired, OUT goes low for the remainder of the count. Mode 3
is periodic; the sequence above is repeated indefinitely.
➢ An initial count of N results in a square wave with a period of N CLK cycles.GATE = 1
enables counting; GATE = 0 disables counting. If GATE goes low.while OUT is low, OUT is
set high immediately; no CLK pulse is required.
➢ Even counts: OUT is initially high. The initial count is loaded on one CLK pulse and then is
decremented by two on succeeding CLK pulses.
➢ When the count expires OUT changes value and the Counter is reloaded with the initial count.
The above process is repeated indefinitely.so for odd counts, OUT will be high for (N + 1)/2
counts and low for (N - 1)/2 counts

MODE 4: SOFTWARE TRIGGERED STROBE :

• OUT will be initially high. When the initial count expires, OUT will go low for one CLK pulse and
then go high again. The counting sequence is ``triggered'‘ by writing the initial count. (G must be 1).

MODE 5: HARDWARE TRIGGERED STROBE (RETRIGGERABLE):

OUT will initially be high. Counting is triggered by a rising edge of GATE. When the initial count
has expired, OUT will go low for one CLK pulse and then go high again. G controls similar to
Mode 1.
Trigger with count of 5

29
 *******************************************************************************
Explain the working principle of 8257 DMA controller interface. (June 2016)
What is DMA? Explain the DMA based data transfer sing DMA controller (April 2015)
*******************************************************************************
6. Direct Memory Access
Direct memory access (DMA) or DMA mode of data transfer is the fastest amongst all the modes of
data transfer. In this mode, the device may transfer data directly to/from memory without any
interference from the CPU.
DMA Controller
The DMA controller (8257) allows certain hardware subsystems to read/write data to/from memory
without microprocessor intervention, allowing the processor to do other work.
.

1 2 3 4 5 6 7 8 9
CLK

HOLD

HLDA

It is used in disk controllers, video/sound cards etc, or between memory locations. Typically, the
CPU initiates DMA transfer, does other operations while the transfer is in progress, and receives an
interrupt from the DMA controller once the operation is complete.

It contains of five main blocks.

1. Data bus buffer

2. Read/Control logic
3. Control logic block
4. Priority resolver
5. DMA channels.

30
 Figure:8237 DMA controller

❖ Programming the 8237

There are 4 steps required to program the address and count registers first:
1. Clear the F/L flip-flop with a clear F/L command
2. Disable the channel
3. Program the LSB and then MSB of the address
4. Program the LSB and then MSB of the count
Additional programming is required to select the mode of operation before the channel is
enabled and started.

31
Internal registers
• The current address register (CAR) is used to hold the 16-bit memory address used for the
DMA transfer.
• The current word count register (CWCR) programs a channel for the number of bytes (up
to 64K) transferred during a DMA action.
• The base address (BA) and base word count (BWC) registers are used when auto-
initialization
• is selected for a channel. In this mode, their contents will be reloaded to the CAR and CWCR
after the DMA action is completed.
• Each channel has its own CAR, CWCR, BA and BWC.
• The command register (CR) programs the operation of the 8237 DMA controller
• The mode register (MR) programs the mode of operation for a channel.
• The request register (RR) is used to request a DMA transfer via software, which is very
useful in memory-to-memory transfers.
• The mask register set/reset (MRSR) sets or clears the channel mask to disable or enable
particular DMA channels.
• The status register shows the status of each DMA channel.

Data bus buffer:

• It is a tri-state, bidirectional, 8 bit buffer which interfaces the 8257 to the system data in the slave
mode; it is used to transfer data between microprocessor and internal registers.
• In master mode, it is used to send higher byte address (A8-A15) on the data bus.
Read/write logic:
• When the microprocessor is programming or reading one of the internal registers of the read/write
logic accepts the I/O read (IOR) or low signal.
• Decodes least significant four address bits (A0-A7) and either writes the contents of the data bus
addressed register or places the contents of the addressed register onto data bus.
• During DMA cycles the Read/write logic generates the I/O read and memory write or I/O write and
memory read signals IOR control the data transfer between peripheral and memory device.

DMA channels:
The 8257 provides four identical channels labeled CH0, CH1, CH2 and CH3. Each channel has two-16
bit registers. They are
1. DMA address register
2. Terminal count register
1. DMA address register:
➢ It specifies the address of the first memory location to be accessed.

32
 ➢ It is necessary to load valid memory address in the DMA address register before channel is
enabled.
2. Terminal count register:
➢ The value loaded into the low order 14 bits of TCR specifies the number of DMA cycles
minus one (N-1) before TC output is activated.
➢ Therefore, for N number of desired DMA cycles it is necessary to load the value N-1 into
the low order 14 bits of TCR.
➢ MSB 2 bits specify the type of operation to be performed.
Control Logic:
• It controls the sequence of operations during all DMA cycles by generating the appropriate control
signals and the 16 bit address that specified the memory location to be accessed.
• It consists of mode set register and status register.
• Mode set register is programmed by the CPU to configure 8257 whereas the status register is read
by CPU to check which channels have reached a terminal count condition and status of update flag.

➢ Mode set register:

• LSB 4 bits are the enable 4 DMA channels.
• MSB 4 bits are the enable auto load, TC stop, extended write, rotating priority modes and
terminal count registers.
• It is cleared by RESET input, this disabling all options, inhibiting all channels and
preventing bus conflicts on power-up.
Master mode,
➢ It controls the sequence of DMA operation during all DMA cycles.
➢ It generates address and control signals.
➢ It increments 16 bit address and decrement 14 bit counter registers.
➢ It activates a HRQ signal on DMA channel Request.
Slave mode it is disabled.

➢ STATUS REGISTER:

• It indicates which channels have reached a terminal count condition and includes the
update flag.
33
 • The Tc status bit=1, terminal count has been reached for that channel.
• Tc bit remains set until the status register is read or the 8257 is reset.
• Update flag =1, 8257 is executing update cycle
• In update cycle 8257 lad parameters in channel 3 to channel 2.

PRIORITY RESOLVER:
It resolves the peripherals request. It can be programmed to work into two modes, either fixed
mode or rotating priority mode.

Initializing of DMA controller

➢ A DMA controller is capable of becoming the bus master and supervising a transfer between an
I/O or mass storage interface and memory. While making a transfer, it must be able to place
memory address on the bus and send and receive handshaking signals in a manner similar to that
of the bus control logic. The purpose of a DMA controller is to perform a sequence of transfers (ie
a block transfer) by stealing bus cycles.

➢ A DMA controller is designed to service one or more I/O mass storage interfaces, and each
interface is connected to the controller by a set of conductors. A portion of a DMA controller for
servicing a single interface is called a channel..

➢ The general organization of a one channel DMA controller and its principal connection is shown
in figure. In addition to the usual control and status registers, each channel must contain an
address register and a byte (or word) count register.

➢ Initializing the controller consists of filling these registers with the beginning (or ending) address
of the memory array that is to be used as a buffer and the number of bytes (words) to be
transferred .For an input to memory, each time the interface has data to transfer it makes a DMA
request

➢ The controller then makes a bus request and when it receives a bus grant, it puts the contents of
the address register on the address bus, sends an acknowledgement back to the interface, and
issues I/O read and memory write signals. The interface then puts the data on the data bus and
drops its request.

➢ When the memory accepts the data it returns a ready signal to the controller, which then
increments (or decrements) the address register, decrements the byte (word) count, and drops its
bus request.

➢ Upon the count reaching zero, the process stops and a signal is sent to the processor as an
interrupt request or to the interface to notify it that the transfers have terminated. An output is
similarly executed except that the controller issues I/O write and memory read signals and the
data are transferred in the other direction.

DRQ0-DRQ3 (DMA Request):

These are the asynchronous peripheral request input signal. The request signals is generated by
external peripheral device.
34
DACK0-DACK3:
These are the active low DMA acknowledge output lines. Low level indicate that, peripheral is
selected for giving the information (DMA cycle).In master mode it is used for chip select
HLDA becomes active to indicate the processor has placed its buses at high-impedance state as can
be seen in the timing diagram,there are a few clock cycles between the time that HOLD changes and
until HLDA changes
HLDA output is a signal to the requesting device that the processor has relinquished control of its
memory and I/O space. one could call HOLD input a DMA request input and HLDA output a DMA
grant signal

Steps in a DMA operation

➢ Processor initiates the DMA controller gives device number, memory buffer pointer, called
channel initialization.
➢ Once initialized, it is ready for data transfer.
➢ When ready, I/O device informs the DMA controller .DMA controller starts the data transfer
process
• Obtains bus by going through bus arbitration
• Places memory address and appropriate control signals
• Completes transfer and releases the bus
• Updates memory address and count value
• If more to read, loops back to repeat the process
Notify the processor when done typically uses an interrupt

Modes of DMA operation

Each channel may be put in one of four modes,with its current mode being determined by bits 7
and6 of the channel’s mode register .The four possible modes are

35
 a) Byte b) Burst c) Block

❖ Single transfer mode (01)

After each transfer the controller will release the bus to the processor for at least one bs cycle,
but will immediately begin testing for DREQ inputs and proceed to steal another cycle as
soon as a DREQ line becomes active.
❖ Block transfer mode (10)
DREQ need only be active until DACK becomes active,after which the bus is not released
until the entire block of data has been transferred.
❖ Demand Transfer mode(00)
This is similar to the block mode except that DREQ is tested after each transfer. If DREQ is
inactive , transfers are suspended until DREQ once again becomes active ,at which time the
block transfer continues from the point at which it was suspended. This allows the interface
to stop the transfer in the event that its device cannot keep up.
❖ Cascade Mode(11)
In this mode 8237s may be cascaded so that more than four channels can be included in the
DMA subsystem. In cascading the controllers ,those in the second level are connected to those
in the first level by joining HRQ to DREQ and HLDA to DACK ,To conserve space, this
mode will not be considered further.
In this mode
Single-cycle mode: DMA data transfer is done one byte at a time

Burst-mode: DMA transfer is finished when all data has been moved.

***************************************************************************************
Draw the block diagram of 8259A and explain how to program 8259A (April 2010).(Dec 2018)
Explain the working of 8259 with a neat block diagram . (Nov/Dec 2016/April 2015)
**********************************************************************************

36
7. Programmable Interrupt controller (8259)

Definition:

• The Intel 8259 Programmable Interrupt Controller handles up to eight vectored priority interrupts or
the CPU.It is cascadable for up to 64 vectored priority interrupts without additional circuitry. It is
packaged in a 28-pin DIP, uses NMOS technology and requires a single a5V supply.

• It accepts requests from the peripheral equipment, determines which of the incoming requests is of
the highest importance (priority), ascertains whether the incoming request has a higher priority value
than the level currently being serviced, and issues an interrupt to the CPU based on this
determination.

➢ Interrupt Request Register (RR): IRR stores all the interrupt request in it in order to serve them
one by one on the priority basis.

➢ In-Service Register (ISR): This stores all the interrupt requests those are being served, i.e. ISR
keeps a track of the requests being served.

➢ Priority Resolver: This unit determines the priorities of the interrupt requests appearing
simultaneously. The highest priority is selected and stored into the corresponding bit of ISR
during INTA pulse. The IR0 has the highest priority while the IR7 has the lowest one, normally in
fixed priority mode. The priorities however may be altered by programming the 8259A in rotating
priority mode.

37
➢ Interrupt Mask Register (IMR) : This register stores the bits required to mask the interrupt
inputs. IMR operates on IRR at the direction of the Priority Resolver.

Interrupt Control Logic: This block manages the interrupt and interrupt acknowledge signals to

be sent to the CPU for serving one of the eight interrupt requests. This also accepts the interrupt
acknowledge (INTA) signal from CPU that causes the 8259A to release vector address on to the
data bus.

➢ Data Bus Buffer: This tristate bidirectional buffer interfaces internal 8259A bus to the
microprocessor system data bus. Control words, status and vector information pass through data
buffer during read or write operations.

➢ Read/Write Control Logic: This circuit accepts and decodes commands from the CPU. This
block also allows the status of the 8259A to be transferred on to the data bus.

➢ Cascade Buffer/Comparator: This block stores and compares the ID’s all the 8259A used in
system. The three I/O pins CASO-2 are outputs when the 8259A is used as a master. The same
pins act as inputs when the 8259A is in slave mode. The 8259A in master mode sends the ID of
the interrupting slave device on these lines. The slave thus selected, will send its preprogrammed
vector address on the data bus during the next INTA pulse.

➢ CS: This is an active-low chip select signal for enabling RD and WR operations of 8259A. INTA
function is independent of CS.

➢ WR: This pin is an active-low write enable input to 8259A. This enables it to accept command
words from CPU.

➢ RD: This is an active-low read enable input to 8259A. A low on this line enables 8259A to
release status onto the data bus of CPU.

➢ D0-D7 : These pins from a bidirectional data bus that carries 8-bit data either to control word or
from status word registers. This also carries interrupt vector information.

➢ CAS0 – CAS2 Cascade Lines: A signal 8259A provides eight vectored interrupts. If more
interrupts are required, the 8259A is used in cascade mode. In cascade mode, a master 8259A
along with eight slaves 8259A can provide up to 64 vectored interrupt lines. These three lines act
as select lines for addressing the slave 8259A.

➢ PS/EN: This pin is a dual purpose pin. When the chip is used in buffered mode, it can be used as
buffered enable to control buffer transreceivers. If this is not used in buffered mode then the pin is
used as input to designate whether the chip is used as a master (SP =1) or slave (SP = 0).

➢ INT: This pin goes high whenever a valid interrupt request is asserted. This is used to interrupt
the CPU and is connected to the interrupt input of CPU.

➢ IR0 – IR7 (Interrupt requests) :These pins act as inputs to accept interrupt request to the CPU.
In edge triggered mode, an interrupt service is requested by raising an IR pin from a low to a high

38
 state and holding it high until it is acknowledged, and just by latching it to high level, if used in
level triggered mode.

➢ A0 : This input signal is used in conjunction with WR and RD signals to write commands into the
various command registers, as well as reading the various status registers of the chip. This line
can be tied directly to one of the address lines.

Command Words of 8259A

The 8259A accepts two types of command words generated by the CPU:

1. Initialization Command Words (ICWs):

Before normal operation can begin, each 8259A in the system must be brought to a starting pointed
by a sequence of 2 to 4 bytes timed by WR pulses.

2. Operational Command Words (OCWs):

These are the command words which command the 8259A to operate in various interrupt modes.
These modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.

❖ Interrupt Sequence of 8259 Programmable Interrupt Controller

Interrupt Sequence with an 8085 system

1. One or more IR lines are raised high that set corresponding IRR bits.

2. 8259A resolves priority and sends an INT signal to CPU.

3. The CPU acknowledge with INTA pulse.

4. Upon receiving an INTA signal from the CPU, the highest priority ISR bit is set and the
corresponding IRR bit is reset. The 8259 will also release a CALL instruction code (11001101) on to
the 8 bit data through its D7 - D0 pins.

5. The CALL instruction will initiate a second INTA pulse. During this period 8259A releases an 8-bit
pointer on to a data bus from two more INTA pulses to be sent to the 8259 from the CPU group.

6. These two INTA pulses allow the 8259 to release its programmed subroutine address onto the data bits.
The lower 8 bit address is released at the first INTA pulse and the higher 8 bit address is released at the
second INTA pulse.

7. This completes the 3 byte CALL instruction released by the 8259. Interrupt cycle. The ISR bit is
reset at the end of the second INTA pulse if automatic end of interrupt (AEOI) mode is programmed.
Otherwise ISR bit remains set until an appropriate EOI command is issued at the end of interrupt
subroutine.

39
❖ Priority Modes

1.Fully Nested Mode

• IR0 is the highest and IR7 is the lowest one

• In addition any IR can be assigned the highest priority; the priority sequence will begin at that IR.

Example:

IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

4 5 6 7 0 1 2 3

2.Automatic Rotation(equal Priority):

In this mode, a device which one is being serviced will be considered as a lowest priority in the next
time
First IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
Time
6 7 0 1 2 3 4 5

Second IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7

Time
1 0 7 6 5 4 3 2

3.Specific rotation mode(Specific Priority)

The programmer can change the priorities by programming the bottom priority and ths fixing all
other priorities.ie if IR4 is programmed as the lowest priority ,then IR% will have the highest one.

End of Interrupt (EOI)

• After the completion of an interrupt service, the corresponding ISR bit needs to be
reset.
• This is called the End of Interrupt (EOI).
• It can be issued in 3 formats. They are,
•
(i) Non-specific EOI command→When the 8259 receives this command, it resets the
highest priority ISR bit.
(ii) Specific EOI command→ It specifies which ISR bit to be reset.
(iii) Automatic EOI command When the 8259 receives the third signal, the ISR bit is

reset

40
 Command and Status Words of 8259

✓ Command Word for Operational Command Words (OCWs)

****************************************************************************************
Explain A/D interface with 8085 with neat sketch.(Dec 2014)
Explain how D/A and A/D interfacing done with 8085with an application(April 2015)(Dec 2017)
***************************************************************************************
8.Analog to digital conversion
➢ The process of analog to digital conversion is a slow process, and the microprocessor has to wait
for the digital data till the conversion is over.

➢ After the conversion is over, the ADC sends end of conversion EOC signal to inform the
microprocessor that the conversion is over and the result is ready at the output buffer of the ADC.
These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and reading the
digital output of the ADC are carried out by the CPU using 8255 I/O ports.

➢ The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is
called as the conversion delay of the ADC.

➢ It may range anywhere from a few microseconds in case of fast ADC to even a few hundred
milliseconds in case of slow ADCs.

41