UNIT-І 8086 MICROPROCESSORS

8086 MICROPROCESSORS

Syllabus
8086 MICROPROCESSORS
Introduction to Microprocessor, 8086 Microprocessor Family, 8086 Main Features, Register
Organization, Internal Architecture (BIU, EU), Program Status Register, Pin Diagram /
Description, 8086 System Timing, Minimum Mode and Maximum Mode Configuration with

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Timing Diagram.

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Topics
> Introduction to Microprocessor

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8086 Microprocessor Family 3

8086 Main Features 4

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Register Organization 4
Registers 5

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• General Purpose
Segment Registers 5

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• Indexed and Pointer Registers 6

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• Flags (Program Status Register) 6

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Internal Architecture (BIU, EU) 7

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Pin Diagram / Description 9
8086 System Timing 15

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Minimum Modes of 8086. 16

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• Architecture.
o Pin Diagram.
• Timing Diagrams.
Maximum Modes of 8086. 20
• Architecture.
• Pin Diagram.

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o Timing Diagrams.

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Dept. of ECE.
 UNIT- I 8086 MICROPROCESSORS

Introduction to Microprocessor

Microprocessor is the brain of computer, which does all the work. It is a computer
processor that incorporates all the functions of CPU (Central Processing Unit) on a single
IC (Integrated Circuit) or at the most a few ICs.

Microprocessors Characteristics
➤ Microprocessors are multipurpose devices that can be designed for generic or specialized
functions. The microprocessors of laptops and smartphones are general purpose whereas
ones designed for graphical processing or machine vision are specialized ones. There are

some characteristics that are common to all microprocessors.

important defining characteristics of a microprocessor

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These are the most
Clock speed
Instruction set
Word size
Clock Speed
Every microprocessor has an internal clock that regulates the speed at which it executes
instructions and also synchronizes it with other components. The speed at which the
microprocessor executes instructions is called clock speed. Clock speeds are measured in
MHz or GHz where 1 MHz means 1 million cycles per second whereas 1 GHz equals to
1 billion cycles per second. Here cycle refers to single electric signal cycle.

Bus
Connection lines used to connect the internal parts of the microprocessor chip is called
bus. There are three types of buses in a microprocessor -

Data Bus Lines that carry data to and from memory are called data bus. It is a
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bidirectional bus with width equal to word length of the microprocessor

Address Bus It is a unidirectional responsible for carrying address of a memory
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location or I/O port from CPU to memory or I/O port

Control Bus - Lines that carry control signals like clock signals, interrupt
signal or ready signal are called control bus. They are bidirectional. Signal that denotes
that a device is ready for processing is called ready signal. Signal that indicates to a
device to interrupt its process is called an interrupt signal.

Memory
Microprocessor has two types of memory
RAM -Random Access Memory is volatile memory that gets erased when power is
switched off. All data and instructions are stored in RAM.
ROM Read Only Memory is non-volatile memory whose data remains intact even after
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power is switched off. Microprocessor can read from it any time it wants but cannot write
to it. It is preprogrammed with most essential data like booting sequence by the
manufacturer.

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 UNIT-I 8086 MICROPROCESSORS

RISC Processor
> RISC stands for Reduced Instruction Set Computer. It is designed to reduce the
execution time by simplifying the instruction set of the computer. Using RISC
processors, each instruction requires only one clock cycle to execute results in uniform
execution time. This reduces the efficiency as there are more lines of code, hence more
RAM is needed to store the instructions. The compiler also has to work more to convert
high-level language instructions into machine code.

Characteristics of RISC
The major characteristics of a RISC processor are as follows -

It consists of simple instructions.

It supports various data-type formats.
It utilizes simple addressing modes and fixed length instructions for pipelining.
It supports register to use in any context.
One cycle execution time.
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"LOAD" and "STORE" instructions are used to access the memory location.
It consists of larger number of registers.
It consists of less number of transistors.

CISC Processor
➤ CISC stands for Complex Instruction Set Computer. It is designed to minimize the
number of instructions per program, ignoring the number of cycles per instruction. The
emphasis is on building complex instructions directly into the hardware.
The compiler has to do very little work to translate a high-level language into assembly
level language/machine code because the length of the code is relatively short, so very
little RAM is required to store the instructions.

Characteristics of CISC
>
Variety of addressing modes.
Larger number of instructions.
Variable length of instruction formats.
Several cycles may be required to execute one instruction.
Instruction-decoding logic is complex.
One instruction is required to support multiple addressing modes.

Microprocessors Families
The microprocessor is the greatest invention of the 20th century. The evaluation of
microprocessors is shown below Table 1.1

Table 1.1
Microprocessor Evaluations
General Purpose Processor Transistors Data Length Technology
4004 2300 4 bits PMOS
8008 3500 8 bits PMOS
8080 6000 8 bits PMOS
8085 6500 8 bits NMOS

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 UNIT-I 8086 MICROPROCESSORS

8086 30000 16 bits HMOS

80286 134000 16 bits HCMOS
80386 275000 16/32 bits HCMOS
80486 1200000 16/32 bits HCMOS
Athalon XP 3700000 16/32/64 bits
Celeron 7500000 32 bits
Pentium 4 55000000 32 Bit

Introduction to 8086

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Main Features

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8086 is a 16-bit microprocessor.
It make use of HMOS technology.
8086 has 16 data lines represented as Do to D15.
8086 has 20 address lines represented as A to A20. it can access upto 220 memory
locations (1 MB).
The address and data bus can be multiplexed together to form ADo to AD15.
It consists of eight status signal S0 to S7.
It can support upto 64 I/O ports.
It provides 14, 16 bit registers. Which can be classified into three categories such as
general purpose registers, segment registers & flag registers
8086 is designed to operate in two modes, minimum and maximum.
8086 has two blocks represented as Execution Unit (EU) & Bus Interface Unit (BIU).
It can per fetches upto 6 instruction bytes from memory and queues then in order to speed
up instruction execution.
To perform any operation it requires four clock cycles which are obtained by using
crystal oscillator. It may be 5MHz, 8MHz or 10MHz frequency.
It requires single phase clock with 33% duty cycle to provide internal timings.
A 40 pin dual in line package.
It requires +5V power supply.

Register Organization of 8086

8086 has a powerful set of registers known as general purpose and special purpose
registers. All of them are 16 bit registers.
The general purpose registers can be used as either 8 bit register or 16 bit registers. They
may be either used for holding data, variables and intermediate results temporarily or for
other purposes like a counter or for storing offset address from some particular
addressing modes etc.
The special purpose registers are used as segment registers, pointers, index registers or as
offset storage registers for particular addressing modes.
The register set are categorized into four groups namely general data registers, segment
registers, pointer and indexed registers and flag registers. Fig 1.1 shows the register
organization of 8086.
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 UNIT- I 8086 MICROPROCESSORS

SP

AX AH AL CS BP

BX BH BL SS FLAGS/PSW SI

CX CH CL DS DI

DX DH DL ES IP

General data registers Segment registers Pointers and index registers

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Fig. 1.1 Register Organization of 8086

General Purpose Registers

➤ The registers AX, BX, CX and DX are the general purpose 16 bit registers.
➤ Ax is used as 16 bit accumulator, with the lower 8 bit of AX designated as AL and higher
8 bit AH. AL can be used as an 8 bit accumulator for 8 bit operations. This is the most
important general purpose register having multi functions.
Usually the letters L and H specify the lower and higher bytes of a particular register. For
example, CH means the higher 8 bits of the CX register and CL means the lower 8 bits of
the CX register. The letter X is used to specify the complete 16 bit register.
The register CX is also used as a default counter in case of string and loop instructions.
The register BX is used as an offset storage for forming physical addresses incase of
certain addressing modes.
DX register is a general purpose registers which may be used as an implicit operand or
destination in case of a few instructions.

Segment Registers
The 8086 addresses a segmented memory. The complete 1 megabyte memory, which the
8086 addresses is divided into 16 logical segments. Each segment thus contains 64
Kbytes of memory.
There are four segment register, Code Segment Register (CS), Data Segment Register
(DS), Extra Segment Register (ES), and Stack Segment Register (SS).
The Code Segment (CS) register is used for addressing a memory location in the code
segment of the memory, where executable program is stored.
The Data Segment (DS) registers points to the data segment of the memory, where the
data is resided.
The Extra Segment (ES) register also refers to a segment which essentially is another data
segment of the memory. Thus the extra segment also contains data.
The Stack Segment (SS) register is used for addressing stack segment of memory i.e,
memory which is used to store stack data.
The CPU uses the stack for temporarily storing important data.
The segment registers contains 16 bit segment base addresses related to different
segments.
The advantage of this scheme is that instead of maintaining a 20 bit register for a physical
address, the processor just maintains two 16 bit registers which are within the word
length capacity of the machine. Thus the CS, DS, SS and ES segment registers,

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 UNIT-I 8086 MICROPROCESSORS

respectively, contains the segment addresses for the code, data stack and extra segments
of memory.

Pointers and Index Registers

The pointers contain offset within the particular segments.
The pointer IP, BP and SP usually contains offsets within the code (IP) and stack (BP &
SP) segments.
The index registers are used as general purpose registers as well as for offset storage in
case of indexed, based indexed and relative based indexed addressing modes.

The index registers are particularly useful for string manipulations.

The register SI is generally used to store the offset of source data in data segment while
the register DI is used to store the offset of destination in data or extra segment.

Flag Register of 8086

8086 has a 16 bit flag register which is divided into two parts. Conditional code or status
flags and machine control flags as shown in Fig. 1.2.
The condition code flag register is the
lower byte of the 16 bit flag register along with the
overflow flag. This flag identical to the 8085 flag register, with an additional over flow
flag, which is not present in 8085. This type of flag register of 8086 reflects the results of
the operations performed by ALU.
The control flag register is the higher byte of the flag register of 8086. It contains three
flags the direction flag (D), interrupt flag (1) and trap flag (Т).

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

X 0 D T S x Ac P X Cy

O-Overfiow flag z- Zero flag

D-Direction flag Ac-Auxiliary carry flag
1-Interrupt flag P-Parity flag
T-Trap flag Cy-Carry flag
S-Sign flag X-Not used

Fig 1.2 Flag Register of 8086

The description of each flag bits is as follows.

S- Sign Flag
This flag is set when the result of any computation is negative. For signed computations
the sign flag equals the MSB of the result.

Z- Zero Flag
The flag is set if the result of the computation or comparison performed by the previous
instruction is zero.

P-Parity Flag
This flag is set to 1 if the lower byte of the result contains even number of 1s.

C- Carry Flag
This flag is set when there is a carry out of MSB in case of addition or borrow in case of
subtraction. For example when two numbers are added a carry may be generated out of the most
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 UNIT-I 8086 MICROPROCESSORS

significant bit position. The carry flag in this case will be set to '1'. In case, no carry is
generated, it will be '0'. Some other instructions also affect or use this flag and will be discussed
later in this text.

T- Trap Flag
If this flag is set, the processor enters the single step execution mode. In other words, a
trap flag interrupt is generated after execution of each instruction. The processor executes the
current instruction and the control is transferred to the Trap interrupt service routines.

I- Interrupt Flag
If this flag is set, the maskable interrupts are recognized by the CPU, otherwise they are

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ignored.

D- Direction Flag
This is used by string manipulation instructions. If this flag bit is 0' the string is
processed beginning from the lowest address to the highest address, i.e, auto incrementing mode.
Otherwise the string is processed from the highest address towards the lowest address, i.e, auto
decrementing mode.

AC- Auxiliary Carry Flag

This is set if there is a carry from the lowest nibble, i.e, bit three during addition or

borrow for the lowest nibble i.e, bit three, during subtraction.

O- Overflow Flag
This flag is set if an overflow occurs, i.e if the result of a signed operation is large enough
to be accommodated in a destination register. For example, in case of the addition of two signed
numbers, if the result overflows into the sign bit, i.e, the result is of more than 7 bits in size in
case of 8 bit signed operations and more than 15 bit in size in case of 16 bit signed operations
then the overflow flag will be set.

Internal Architecture

The architecture of 8086 provides a number of improvements over 8085 architecture. It

supports a 16 bit ALU, a set of 16 bit registers and provides segmented memory
addressing capability, a rich instruction set, powerful interrupt structure, fetched
instruction queue for overlapped fetching and execution etc. the internal block diagram
shown in Fig. 1.3 describes the overall organization of different units inside the chip.
The complete architecture of 8086 can be divided into two parts Bus Interface Unit (BIU)
and Execution Unit (EU).
The Bus Interface Unit (BIU) contains the circuit for physical address calculations and a
predecoding instruction byte queue (6 bytes long). The bus interface unit makes the
system bus signal available for external interfacing of the devices. This unit is responsible
for establishing communications with external devices and peripherals including memory
via the bus. The 8086 addresses a segmented memory. The complete physical address
which is 20 bit long is generated using segment and offset register each of 16 bit long.
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For generating a physical address from contents of these two registers, the contents of a
segment register also called as segment address is shifted left bit wise four times and to
this result, contents of an offset register also called as offset address is added to produce a
20 bit physical address.

Ex: If the segment address is 1005H and the offset is 6666H, then the physical address is
calculated as
Segment address = 1005H
Offset address = 5555H = 0101 0101 0101 0101
Segment address = 1005H = 0001 0000 0000 0101
Physical address shifted segment address + offset address
=

Shifted by 4 bit positions = 0001 0000 0000 0101 0000 + 0101 0101 0101 0101
Physical address = 0001 0101 0101 1010 0101 = 155A5H

The segment addressed by the segment value 1005H can have offset values from 0000H
to FFFFH within it, i.e. maximum 64K locations may be accommodated in the segment.
The segment register indicates the base address of a particular segment, while the offset
indicates the distance of the required memory location in the segment from the base
address. Since the offset is a 16 bit number, each segment can have a maximum of 64K
locations. The bus interface unit has a separate adder to perform this procedure for
obtaining a physical address while addressing memory. The segment address value is to
be taken from an appropriate segment register depending upon whether code, data or
stack are to be accessed, while the offset may be the contents of IP, BX, SI, DI, SP, BP or
an immediate 16bit value, depending upon the addressing mode.

In 8086 the opcode is fetched and decoded. While the fetched instruction is executed
internally, the external bus is used to fetch the machine code of the next instruction and
arrange it in a queue known as predecoded instruction byte queue.
It is a 6 bytes long first in first out structure.
The instructions from the queue are taken for decoding sequentially. Once a byte is
decoded, the queue is rearranged by pushing it out and the queue status is checked for the
possibility of the next opcode fetch cycle. While the opcode is fetched by the Bus
Interfacing Unit (BIU), the Execution Unit (EU) executes the previously decoded
instruction concurrently. The BIU along with the EU thus forms a pipeline. The bus
interface unit thus manages the complete interface of EU with memory and I/O devices,
under the control of the timing and control unit.
The execution unit contains the register set of 8086 except segment registers and IP. It
has a 16 bit ALU, able to perform arithmetic and logical operations. The 16 bit flag
register reflects the results of execution by the ALU. The decoding unit decodes the
opcode bytes issued from the instruction byte queue. The timing and control unit derives
the necessary control signals to execute the instruction.
Opcode received from the queue, depending upon the information made available by the
decoding circuit.
The execution unit may pass the results to the bus interface unit for storing them in
memory.

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 UNIT-I 8086 MICROPROCESSORS

食ADD-AD
Address/status Address/data
AS3-A19/Ss 1

Memory address and data

bus interface

Internal data bus

Address conversion
mechanism (adder)
Instruction byte

BUSINTERFACШ
queue 6 bytes
CS
DS
SS
ES

コマート
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IP

Internal data bus

I Decoding

EXCUT-ON
circuit
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AX AH AL
BX BH BL

CX CH CL

DX DH DL
ALU (16)
SP
BP

UNIT SI
Dt

Register bank Flags (16)

Timing and control

circuit

Clock and control

signals

Fig. 1.3 8086 Architecture

Signal Descriptions of 8086

The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10
MHz, packaged in a 40 pin DIP or plastic package.
The 8086 operates in single processor or multiprocessor configurations to achieve high
performance.
The pin configuration Fig. 1.4 some of the pins serve a particular function in
is shown in
minimum mode and others function in maximum mode configuration.
The 8086 signals can be categorized in three groups. The first are the signals having
common functions in minimum as well as maximum mode, the second are the signals

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which have special functions for minimum mode and the third are the signals having
special functions for maximum mode.

AD15- ADO
> These are the time multiplexed memory I/O address and data lines. Address remains on

the lines during T1 state, while the data is available on the data bus during T2, T3, Tw
and T4. Here T1, T2, T3, Tw and T4 are the clock status of a machine cycle. Tw is a wait
state. These lines are active high and float to a tristate during interrupt acknowledge and
local bus holds acknowledge cycles.

A19/ S6, A18/ S5, A17/ S4, A16/ S3

These are the time multiplexed address and status lines.
During T1 these are the most significant address lines for memory operations. During I/O
operations, these lines are low.
During memory or I/O operations, status information is available on those lines for T2,
T3, Tw and T4.
The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
The S4 and S3 together indicate which segment register is presently being used for
memory accesses as shown in table 1.2. These lines float to tri state off during the local
bus hold acknowledge. The status line S6 is always low. The address bits are separated
from the status bits using latched controller by the ALE signal.

Table 1.2 Selection of Segment Register

S4 S3 indications
0 0 Alternate Data
이 1 Stack
1 이 Code or None
1 1 Data

RD (Read)

Read signal when low, indicates the peripherals that the processor is performing a
memory or I/O read operation.
RD is active low and shows the state for T2, T3, Tw of any read cycle. The signal
remains tristated during the 'hold acknowledge'.

Ready
➤ This is the acknowledgement from the slow devices or memory that they have completed
the data transfer.
The signal made available by the devices is synchronized by the 8284A clock generator
to provide ready input to the 8086. The signal is active high.

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