CHAPTER FIVE

Central Processing Unit (CPU)

Internal components of a CPU
• The part of the computer that performs the bulk of data processing
operations is called the central processing unit and is referred to as
CPU.
• The brain of any computer system is the CPU.
• It controls the functioning of the other units and process the data.
• The CPU is sometimes called the processor, or in the personal computer field
called “microprocessor”.
• It is a single integrated circuit that contains all the electronics needed to execute
a program.
• The processor calculates (add, multiplies and so on), performs logical operations
(compares numbers and make decisions), and controls the transfer of data
among devices.
The components of CPU.
• A typical CPU has three major components:
 Register set
 Arithmetic logic unit(ALU)
Control unit (CU).
The components of CPU…
The components of CPU…
• The registers set stores intermediate data used during the execution
of the instructions.
• The ALU provides the circuitry needed to perform the arithmetic,
logical and shift operations demanded of the instruction set.
• The control unit is the entity responsible for fetching the instruction
to be executed from the main memory and decoding and then
executing it.
The components of CPU…
• The CPU can be divided into a data section and a control section.
• The data section, which is also called the data path, contains the
registers (known as the register file) and the ALU.
• The data path is capable of performing certain operations on data
items.
• The register file can be thought of as a small, fast memory, separate
from the system memory, which is used for temporary storage during
computation.
Instruction Formats
• Instruction includes a set of operation codes and operands that
manage with the operation codes.
• Instruction format supports the design of bits in an instruction.
• It contains fields including opcode, operands, and addressing mode.
Instruction Formats…
• Instruction formats can be:
One address.
Two address.
Zero address.
Three addresses and comparison.
THREE-ADDRESS INSTRUCTIONS
• Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory
operand.
• The program in assembly language that evaluates X = (A + B) ∗ (C + D)
is shown below, together with comments that explain the register
transfer operation of each instruction.
THREE-ADDRESS INSTRUCTIONS…
• It is assumed that the computer has two processor registers, R1 and R2.
The symbol M [A] denotes the operand at memory address symbolized by
A.
• The advantage of the three-address format is that it results in short
programs when evaluating arithmetic expressions.
• The disadvantage is that the binary-coded instructions require too many
bits to specify three addresses.
• An example of a commercial computer that uses three-address instructions
is the Cyber 170.
TWO-ADDRESS INSTRUCTIONS
• Two address instructions are the most common in commercial
computers.
• Here again each address field can specify either a processor register
or a memory word.
• The program to evaluate X = (A + B) ∗ (C + D) is as follows:
TWO-ADDRESS INSTRUCTIONS…
• The MOV instruction moves or transfers the operands to and from
memory and processor registers.
• The first symbol listed in an instruction is assumed to be both a
source and the destination where the result of the operation is
transferred.
ONE-ADDRESS INSTRUCTIONS
• One-address instructions use an implied accumulator (AC) register for
all data manipulation.
• For multiplication and division there is a need for a second register.
• However, here we will neglect the second and assume that the AC
contains the result of tall operations. The program to evaluate
X = (A + B) ∗ (C + D) is
ONE-ADDRESS INSTRUCTIONS…
ZERO-ADDRESS INSTRUCTIONS
• A stack-organized computer does not use an address field for the
instructions ADD and MUL.
• The PUSH and POP instructions, however, need an address field to
specify the operand that communicates with the stack.
• The following program shows how X = (A + B) ∗ (C + D) will be written
for a stack organized computer. (TOS stands for top of stack)
ZERO-ADDRESS INSTRUCTIONS…
ADDRESSING MODES
• Addressing mode indicates a way of locating data or operands.
• Depending up on the data type used in the instruction and the
memory addressing modes, any instruction may belong to one or
more addressing modes or same instruction may not belong to any of
the addressing modes.
•Effective address or Offset: An offset is determined by adding any
combination of three address elements: displacement, base and index.
• Displacement: It is an 8 bit or 16 bit immediate value given in the
instruction.
• Base: Contents of base register, BX or BP.
• Index: Content of index register SI or DI.
Classification of Addressing Modes:
• Data-Addressing Modes:
 This mode is related to data transfer operation, that is, data is transferred either
from the memory to internal registers of 8086 processors or from one register to
another register.
Example: MOV AX, DX
• Program Memory addressing Modes:
 This mode involves program memory addresses during various operations.
Example: JMP AX, in this instruction, the code execution control jumps to the current
code segment location addressed by the contents of AX register.
• Stack memory addressing Modes:
 This mode involves stack registry operations.
Example: PUSH AX, this instruction copies the contents of AX register to the stack.
Classification of Addressing Modes…
 Data addressing modes
• Implied (Inherent or Implicit) addressing mode:
the operand is implicitly available in the definition of
instruction, i.e. the operands are specified implicitly in the
instruction definition.
• It is a type of addressing mode where no operand
(data or memory location or register) is specified in the
instruction. Eg CLA(clear accumulator),
CMA(complement Accumulator),
• Zero address instruction are designed with implied
addressing mode.
Immediate Addressing Mode

the operand is specified in the instruction itself.

In this mode, the operand field contains the actual operand to be
used in conjunction with the operation specified in the instruction.
• the operands are contained in an operand field rather than
address field .
• This type of mode is quite useful for initializing the registers
to a constant value .
• No need to calculate Effective as well as Accumulator, as they
contain any instruction by default
• Designed like one address instruction format.
MOV AL, 35H (move the data 35H into AL register)
Immediate addressing mode
• immediate data is a part of instruction, and appears in the form of
successive byte or bytes.

• In the above example, 0005H is the immediate data. The immediate

data may be 8- bit or 16-bit in size.

EA=201 and Acc=500

Register addressing mode
• In register addressing the operand is placed in one of 8 bit or 16 bit
general purpose registers.
• Here one register reference is required to access the data. addressing
mode, the data is stored in a register and it is referred using the
particular register.
• It means that the register is the source of an operand of an
instruction.
• All the registers, except IP, may be used in this mode.

Example: MOV BX, AX

• A copies of register AX copied to register BX.
• EA=NA, R1 address is not specified, AC=R1=400
Register indirect addressing mode
• Sometimes, the address of the memory l o c a t i o n which contains data or
operands is determined in an indirect way, using the offset registers.
• This addressing mode allows data to be addressed at any memory location
through an offset address held in any of the following like Base Pointer
(BP), BX, Destination Index (DI), Source Index (SI).
• The mode of addressing is known as register indirect mode.
• In this addressing mode, the offset address of data is in either BX or SI or DI
Register.
• The default segment is either DS or ES.
Example: MOV AX, [BX].
EA=400, AC=700
 Auto Increment Addressing Mode
• similar to the register indirect addressing mode.
• The only exception is that the register is incremented after
we use its value to access memory.
• When the address that is stored in the register is defining a
data table in memory, it is crucial to increment the register
after accessing the table every time.
• It can be obtained using the increment instruction.
• EA=400, AC=700
 Auto Decrement Addressing Mode
The auto decrement addressing mode is just the opposite of
the auto increment mode. In the case of auto decrement mode,
the content present in the register is initially decremented, and
then the content that is decremented in the register is used in
the form of an effective address.
It is presented symbolically as follows: -(R)
The auto decrement mode helps us in implementing the
structure of the stack.
R1 first decreased which is R1=400, -(R1)=399, so
EA=399, AC=450
Direct addressing mode
• In the direct addressing mode, a 16-bit memory address (offset)
directly specified in the instruction as a part of it.
• The addressing mode in which the effective address of memory
location is written directly in the instruction.

The instruction address which the EA=500, the content of the

accumulator(AC) is contained in address at 500, which is 800
 Data addressing modes: Indirect addressing mode
• Indirect Addressing Mode: This is the mode of addressing where the instruction
contains the address of the location where the target address is stored.
• So in this way, it is Indirectly storing the address of the target location in another
memory location. So it is called Indirect Addressing mode.
• common techniques used to specify the memory address of an operand for an
instruction.
• involves specifying a memory address that contains the actual address of the
operand. This can be useful when the actual address of the operand is not known at
the time the instruction is executed. In indirect addressing, the address of the
operand is obtained by accessing the memory location specified by the indirect
address. For example, in the instruction “MOV AX, [BX]”, the memory location
specified by the contents of the BX register is accessed to obtain the actual address
of the operand.
• EA=800, AC=300
There are 2 types(or versions) of Indirect Addressing Mode: Memory Indirect, and Register
Indirect.

1. Memory Indirect: In this type, we directly mention the address of the memory location in
the instruction either enclosed by parenthesis or preceded by the ‘@’ character.

Example :

LOAD R1, (1005)

or
LOAD R1, @1005
2. Register Indirect: In this type, the address of the target memory location will be stored in
the register and the register will be mentioned in the instruction.

Example:
MOV R@, 1005
LOAD R1, (R2)
Data addressing modes: Indexed addressing mode
• In this addressing mode, offset of the operand is stored one of the
index registers.
• DS & ES are the default segments for index registers SI & DI
respectively.
Example: MOV AX, [SI]
• Here, data is available at an offset address stored in SI in DS.

• Index mode=XR+PC= 100+500 and the operand is 900

Data addressing modes: Register relative addressing mode

• In this addressing mode, the data is available at an effective address

formed by adding an 8-bit or 16-bit displacement with the content of
any one of the register BX, BP, SI & DI in the default (either in DS & ES)
segment.

Example: MOV AX, 50H [BX]

EA= 202+500, and AC =325
Data addressing modes: Based Addressing Mode
• In this addressing mode, the offset address of the operand is given by
the sum of contents of BX/BP register and 8/16 bit displacement.
Example: MOV DX, [BX+04]
=XR+500=600, AC=900
Base Register=Index Register
Categories of computer instructions
• The Instruction set of 8086 microprocessor is classified into 7, they
are:-
• Data transfer instructions
• Arithmetic& logical instructions
• Program control transfer instructions
• Machine Control Instructions
• Shift / rotate instructions
• Flag manipulation instructions
• String instructions
Data Transfer instructions
• Data transfer instructions are the instructions
which transfers data in the microprocessor.
• They are also called copy instructions.
• Following is the table showing the list of data
transfer instructions:
 Data Transfer instructions…
OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]

PUSH D PUSH D to the stack PUSH DX

POP pops the stack to D POP AS

D

PUSHA put all the registers into the stack PUSHA

none
POPA gets words from the stack to all registers POPA
none
XCHG exchanges contents of D and S XCHG [2050], AX
D, S

IN copies a byte or word from S to D IN AX, DX

D, S
OUT D, S copies a byte or word from D to S OUT 05, AL
XLAT none XLAT
translates a byte in AL using a table in the memory

LAHF none loads AH with the lower byte of the flag register LAHF
SAHF none SAHF
stores AH register to lower byte of the flag register
PUSHF none copies the flag register at the top of the stack PUSHF
POPF none copies a word at the top of the stack to the flag register
POPF
Process control instructions

•Process control instructions are the

instructions which control the processor’s
action by setting(1) or resetting(0) the values
of flag registers.
•Following is the table showing the list of
process control instructions:
 Process control instructions…
OPCODE OPERAND EXPLANATION EXAMPLE

STC none sets carry flag to 1 STC

CLC none resets carry flag to 0 CLC

CMC none CMC

compliments the carry flag

STD none sets directional flag to 1 STD

CLD none resets directional flag to 0 CLD

STI none sets the interrupt flag to 1 STI

resets the interrupt flag to 0

CLI none CLI
String manipulation instructions
• String is a series of data byte or word available in memory at
consecutive locations.
• It is either referred as byte string or word string.
• Their memory is always allocated in a sequential order.
• Instructions used to manipulate strings are called string manipulation
instructions.
• Following is the table showing the list of string manipulation
instructions:
String manipulation instructions…
OPCODE OPERAND EXPLANATION EXAMPLE

REP instruction repeat the given instruction till CX != 0 REP MOVSB

REPE instruction repeat the given instruction while CX = 0 REPE

REPZ instruction repeat the given instruction while ZF = 1 REPZ

REPNE instruction repeat the given instruction while CX != 0 REPNE

REPNZ instruction repeat the given instruction while ZF = 0 REPNZ

moves contents of byte given by DS:SI into

MOVSB none ES:DI MOVSB

moves contents of word given by DS:SI

MOVSW none into ES:DI MOVSW

moves contents of double word given by

MOVD none DS:SI into ES:DI MOVD

moves the byte at address DS:SI into AL;

LODSB none SI is incr/decr by 1 LODSB

moves the word at address DS: SI into AX;

LODSW none SI is incr/decr by 2 LODSW
String manipulation instructions…
OPCODE OPERAND EXPLANATION EXAMPLE

moves the double word at address DS:SI

LODSD none into EAX; SI is incr/decr by 4 LODSD

moves contents of AL to byte address

STOSB none given by ES:DI; DI is incr/dec by 1 STOSB

moves the contents of AX to the word

address given by ES:DI; DI is incr/decr by
STOSW none 2 STOSW

moves contents of EAX to the DOUBLE

WORD address given by ES:DI; DI is
STOSD none incr/decr by 4 STOSD

compares byte at ES:DI with AL and sets

SCASB none flags according to result SCASB

compares word at ES:DI with AX and sets

SCASW none flags SCASW

compares double word at ES:DI with EAX

SCASD none and sets flags SCASD

compares byte at ES:DI with byte at DS:SI

CMPSB none and sets flags CMPSB

compares word at ES:DI with word at

CMPSW none DS:SI and sets flags CMPSW
Characteristics of CISC and RISC computers

• Reduced Instruction Set Architecture (RISC) –

 The main idea behind this is to make hardware simpler by using an instruction set
composed of a few basic steps for loading, evaluating, and storing operations just like
a load command will load data, a store command will store the data.
• Complex Instruction Set Architecture (CISC) –
 The main idea is that a single instruction will do all loading, evaluating, and storing
operations just like a multiplication command will do stuff like loading data,
evaluating, and storing it, hence it’s complex.
Both approaches try to increase the CPU performance
Characteristic of RISC
• Simpler instruction, hence simple instruction decoding.
• Instruction comes undersize of one word.
• Instruction takes a single clock cycle to get executed.
• More general-purpose registers.
• Simple Addressing Modes.
• Fewer Data types.
• A pipeline can be achieved.
Characteristic of CISC
• Complex instruction, hence complex instruction decoding.
• Instructions are larger than one-word size.
• Instruction may take more than a single clock cycle to get executed.
• Less number of general-purpose registers as operations get
performed in memory itself.
• Complex Addressing Modes.
• More Data types.