148 MICROPROCESsORS AND MICROCONTROLLERS [JNTU-HYDERABAD

4.1 INTRODUCTION TO MICRO cONTROLLER

4.1.1 Overview of 8051 Miero Controtler
Q1. Draw the block diagram of microcomputer and explain each block in detail.
Answer:
The block diagram of a microcomputer is illustrated in the figure.
ESterna!
interryts

Timer Counter
4 KB 128 býtes
Interrupt inputs
conttol ROM RAM

Internal
interrupts
CPU

4 Input/output Serial
Bus
OSC port
Control ports

Po P, P. P, TxD RxD
Address/Data
Figure: Block Diagram of Microcomputer
All the components of åmicrocomputer are built on one chip.
Central Processing Unit (CPU)
It is the heart of microcomputer unit.
It (CPU) performs and controls all the operations of the microcomputer.
It consist of the following elements.
Arithmetic Logic Unit (ALU): It performs arithmetic operations like subtraction, addition,
multiplication, division and logical operations like AND, OR, NOT, XOR, and NAND etc.
Program Counter (PC) :It stores 16-bit address of the next instruction to be executed in the program
thus, it keeps track of the program sequence.
Stack Pointer (SP): It holds 8-bit address of the top of the stack (i.e., the address of the location in stack,
where the last data was stored).
Accumulator: It is a special 8-bit register in which the result of any mathematical operation gets accumulated
(stored) automatically. It can also be used to store the 8-bit data.
General purpose registers to store various data.
Timing and control unit : It is used to synchronize the internal operations of microcomputer with the
frequency of the clock signal and to control the flow of data within the microcomputer and also between the
microcomputer and external devíces.
Oscillator Circuit
It generates a series of clock pulses required to synchronize the operations of a
It is also known as clock generator.
microcomputer.
It consists of a resonator and necessary electrical components.
The frequency of the clock pulses and the fanctioning speed of the microcomputer
of resonator. depends upon the frequeny
On-chip Memories
There are two types of on-chip memories namely internal ROM (4kB) and
internal RAM (128 bytes).
Internal ROM stores the program (code) instructions, It is also
known as on-chip program (code)
memory.
Internal RAM stores the data. It is also known as on-chip
data memory.
Timers/Counters : These are two-byte registers which are used in a program to
PVent or to calculate the number of events. For example, pulse-width determine the time period o
measurement, frequency measurement,
rate generation, and counting of pulses, ete., can be done using on-chip timer/counters.
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 Introduction to Micro
NIT4:
Controllers and Interrupts
rupt Logic Circuitry Communication 149
tis the
logiccircuit which senses the
interrupts
the active interrupts and the order of thearising in the microcomputer and makes the microcomputer
aware
of

des interrupt enable register, interrupts which should be served by the microcomputer.
P'arallel I/O Ports
interrupt priority register and otther necessary
afand
uscd to interface external
clements.
These are
devices with the
The seria! VO port is meant for
transferring microcomputer.
the data between
of bits (i.e., one bit at a time) microcomputer and
by tes (i.e., &-bits of data at atime). whereas, the parallel /O port is for transferring external devices in the
the data in the form oB
Explain the
importance of 8051
microcontroller over microprocessor. May-19(R16), Q1(c)
niscuss the advantages of microcontrollerOR
based system over microprocessor based
nSwer: system.
The advantages of microcontroller based system
Microcontroller based system contains additionalover microprocessor based system are,
circuits
circuit and peripheral devices, such as RAM, ROM, input/output
interfacing
Iess hardware is required for the
system using
less access time is required for built-in microcontroller due to its in built additional features.
mictocontroller is more than the speedof a memory of microcontroller. Hence, speed of operation of
The PCB size required for installing a microprocessor.
microcontroller based system is less due to less hardware
Microcontroller based systems are more reliable. requirement.
Most of the pins of microcontroller are
multifunctioned i.e., one pin can perform multiple functions.
The cost of microçontroller based system is
less due to less hardware requirement.
The environment of common
software/hardwarè design is available from manufactures.
Microcontrollers can easily synchronize the communication between
Microcontroller have many bit handling instructions and hence peripherals of different speeds.
controlling is more affective.
List out the difference between microprocessor
and microcontroiler. May-16(R13), Q1(h)
OR
What is the difference between microprocessor
and microcontroller? April-18(R13), Q1(h)
(Refer any Five Points)
SWer:
The differences between a microprocessor and a microcontroller
are as follows,
Microprocessor Microcontroiler
Ihe architecture of a microprocessor consists of 1. The
architecture of a microcontroller consists of
|ALU, registers and control unit.
microprocessor along with memory (ROMand RAM),
VO interfacing unit and various peripheral
here are only few instructions in microprocessor2.There are units.
many instructions in microcontroller that
ihat support data handling in bits, support data handling in bits.
|n amicroprocessor, only few pins have multiple 3.|lna microcontroller, most
of the pins havè muitiple
functions. functions.
Data and programs are addressed using the same 4. Data and programs are
nemory address range. addressed using different
memory address range.
There are instYuctions in microprocessor that| 5. There are only few instructions in microcontroller
/erform datamanytransfer among memory and CPU. to perform data transfer among-memory
|It takes more time to and I/O 6. lt and CPU.
acess memory takes less time to access memory and /O devices
devices. as they are built in with a
microcontroller.
Hardware
hat requirements are
microprocessor. more for the systems 7. Less hardware is required for the systenms that
use
microcontroller.
The
designing
|very flexible. of microprocessor based systems is | 8. The designing of microcontroller is not as flexible
as that of microprocessor based
3.R has Single memory to store data and code.
systems.
9.It has separate menmory to store data andcode.

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 NIT4:introduction to Micro Controlters and Interrupts Communication 151

Pert 2
drivs
RAMAGOR
RAM Fort Pot 2 fEPROM
ROM

Program
AODR
Stack register
TNP pointe
Angiste: TMP 2 Buffer

ALU Interrupt and

Serial port and Incromenter
PSW Timer blocks
PSEN
ALE
aoiter Pragram
connter
And
COntrol DPTR
Port 1 Port 3
latch latch

HOscilator Port 1 Port 3

drivers drivers
44444AA
XTAL 1 XTAL 2
P1.0.P1.7 P3.0-P3.7

Figure: Block Diagram of 8051 Microcontroller

The individual blocksof 805 l microcontroller are discussed below.
ACC (Accumulator)
Itis an &-bit register that stores one of the operands and its immediate results of ALU operation.
It acts as a register operand for few instructions.
0t is implicit or specified in the instruction.
Register B
It is an 8-bit register that holds one of the operands while performing multiply and divide operations.
TMP 1 and TMP 2
These are temporary storage registers and are inaccessible to the user.

It perforrns arithmeticoperations like addition, subtraction, multiplication, division and logical operations
like AND, OR, NOT,XOR, etc over the operands held by temporary registers.
SW (Program Status Word)
I isan &-bit register which provides the ALr status information.
Sack Poiter
It is an 8-bit register used by the CPU to store information temporarily.
it increments/decrements the SP value by pushing/popping the data on to/from the stack.
gram Address Register
Ii is used to access internal and external program memory.
It is also interfaced to program counter and increment circuit for incrementing PC.
ierial Data Buffer
is an &bit register which consists of two registers namely, Transmit buffer (parallel in serial out register)
and Receive buffer (serial in parallel out register).
is used for data transmission and reception by writing and reading data into SBUF register respectively.
CAnerenenter
It is al6-bit register which keeps incrementing the address in accordance with the program
tow.
is also used to facilitate PC to be used for addressing modes.
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Program Counter (PC)
of eurrently fetching instruction.
Is a 16-bit register that hotds nrernes eery address
It iscapable of addressing 64 K bytes of code.
DPTR (Data Pointer)
It isa l6 bit register used to hold external dáta RAM address.
registet.
IS can be accessed as two 8-bit reeisters (DPH, DPL) Or al6-bít
RAM and RAM Address Register
7FH) and their addresses.
t stores 128 bytes of internal kAM ifrom 00H to
ROM
It is a read only program memory,
(EPROM)or flash EEPROM.
The ROM can be a masked ROM. Erasable PROM
Port Latches and drivers (P0, P1, P2, P3)
output port or the value read from an input port.
These registers specify the values to be generated on an
8-bit register in the SFR.
They are also bit addressable. Each port is connected to an
Interrup, Serial port and Timer blocks
This block includes timer and control registers.
Timer registers-Timer0 and Timer-1
timers/counters and
Control registers- These regísters have control and status information for interrupts,
serial port. These include IP, IE, TMOD, TCON, SCON and PCON registers.
Instruction Register (IR)
It holds the opcode of current instruction.
It provides information to the timing and controi unit to generate signals for executing the instructions.
Timing and control unit
It is used to generate timing and control signals for internal operation of circuit.
The control unit generates control signals like ALE, PSEN, RD, and WR.
ALE: It is an active high output signal used to latch the low address byte while accessing external memory.
PSEN: It is an active low program strobe enable used for reading the contents of external program memory.
RD: It is an active low read sighal used for reading the contents of external data memory.
WR: It isan active low write signal used for writing the contents to external data memory.
Oscillator
It generates a serial of clock pulses required to synchronize the operations of the circuit.
Q7. Explainprogram status word/flag register of 8051 microcontroller.
Answer:
Program status word (PSW) is an 8 bit register which provides the ALU status information. PsW contains
four mathematical or math flags, one user program flag and two register select bits as shown in figure.
7 4 3 1

CH AC FO RSI RSO OV P

Figure: PSW Register

Carry Flag (CF)
It is set to '1', if there is a carry from MSB, otherwise cleared to '0'. It is used in arithmetic, jump, rotal
and boolean instructions.
Auxiliary Carry Flag (AC)
It is set to 1' if there is a carry or borrow from 3«4 bit to 4th bit, otherwise cleared to *0'. It is used for BLD
arithmetic operations.
Overflow Flag (0V)
It is set whenever the result of a signed number operation is too large causing the higher order bit
to i
intothe sign bit.
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 Introduction to. Micro Controllers and Interrupts Communicatión 153
T4:

y(P)

set ifregister A contains odd number of ones and cleared if register Ahas even number of ones.
I is
F l a g(FO)

This flag is
set/cleared by software as a user defined status flag. User flag is also called general purpose flag.

RSI RSO Register Address

bank
00-07 H
1 1 08-0F H
10-17 H
1 3 18-1F H
Table: Register Select Bits
Draw and explain the function of each pin of 8051 family microcontroller. Aug.-22(R18), Q4(b)
OR
Draw the pindiagram of 8051 microcontroller and explain each pin in detail. May-19(R16), Q4(b)
OR
Draw the pin diagram of 8051microcontroller and explain the function of each pin in detail.
(Dec.-18(R13), Q9(a)| May-16(R13), Q9(b))
OR
What is the function of clock generator of 80517 What are the signals are used for clock in
8051.
(Refer only Oscillator Pins)
Swer : Dec-17(R13), Q1(h)
The 8051 microcontroller is a 40 pin dual-in-line package IC chip. The pin'diagram of 8051 microcontroller
shown in figure below.

P1.0 40 V Po
Pl.1 39 PO.0 (ADO)
P1.2 38 PO.1 (ADI)
PÌ.3 37 PO.2 (AD2) Port-0
Port-1
P1.4 36 PO.3 (AD3) or
Address/
Pl.5 6 35 P0.4 (AD4) Data
P1.6 34 PO.5 (ADS) lines
P1.7 33 PO.6 (AD6)
RST 32 PO.7 (AD7)
(RXD)P3.0 8051 31 BA
Microcontroller 30 ALE
(TXD)P3.1 11

(INTO)P3.2 12 PSEN
Port-3
or (INTI )P3.3 13 28 P2.7 (Al5)
Alternate (TO) P3.4 14 27 P2.6 (A14)
Function Port-2
lines (T1) P3.5 15 26 P2.5 (Ä13)
or
(WR)P3.6 16 P2.4 (A12) Address
(RD) P3.7 17 24 P2.3 (A11) lines

Oscillator (XTAL2 18 23 P2.2 (A10)

inputs xTALI 19 P2.1 (A9)
P2.0 (A8)
GND 20

Figure: Pin Diagram of 8051 Microcontroller

e 40 pins of 805 1 microoontroller are configured as follows,
VO Pins
The 32 VO pins of 8051 are divided into four 8-bit parallell ports P0, P1, P2 and P3 as shown in figure.
Out of the 32 pins, 24 pins (i.e., pins of P0, P2 and P3) are configured to perform alternate functions (/O
unction, address or data bus for higher order memory and some other special functions) and the remaining
8 pins are configured to perform only I/Ofunction.

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1JNTU-HYDERABAN
internal ciock generatrr, the
Port-0 (Pins 39-32) in case of
pin is connected as input to the isverting
A groupof &pins (i.e., 39-32) is confisgured as ofoscillator circuit and XTAL 2 pin is
port0.
to the output of inverting amplifier.
This port s dn 8-bie bidircctional bit sddress Control Pins
able 1/0.port: It is also used to access external 4
memory. * Pin-29 ( PSEN -Program Store Fnatie
The pins PO.0-P0.7 represent ADO-AD7 respec PSEN is. an active low, output control
tively. When microcontroller readsthe external
The lower order address byte (ADO-AD7) of memory, the PSEN signal gets activated z
the two byto address (AD0-AD15) of external every six oscillator periods.
memory is timé multiplexcd with the data being
written or rdad,Hence, the pins of port-0 can be The PSEN signal serves as the read strobe t
used to transfer data bytes between 8051 and the external program menory.
external.devices and also to address an external
This signalcauses the external program memsry
memory. toenable its contents to the 805 !.
Port-1 (Pins 1-8)
Pin-30 (ALE-Address Latch Enable)
The pins 1-8 are configured as port I.
The pins of this port are configured to perform ALE is an active high output signal.
only l/O function. While accessing the external memory, this sigrai
It acts as an 8-bit bidirectional bit addressable is used to latch the lower byte of the address
port. which is time multiplexed with port 2.
Port-2 (Pins 21-28) It can be used for exterr! timing or clocking
The pins 21-28 form a parallel I/O port (port 2). purpose.
The pins of port 2 can be configured as 1/O pins Pin-31 ( EA-External Access)
or they can be configured as higher order address
lines (AD8-ADI5) ofatwobyte external memory EA is an active low signal.
address. When the EA pin is high, i.e., EA =1the 805!
It acts as an 8-bit bidirectional bit addressable fetches the progran instructions fron the irntemal
port. program memory.
Port-3 (Pins 10-17) When the EA pin is low,i.e., EA =0, the 8051
The pins 10-17 are configured as Port 3, is also microcontroller fetches th¹ program instructioS
a bidirectional I/O port. from external program memory.
The pins of port3 can be configured to function as Pin-9 (RST-Reset)
/O pins and also to perform alternate functions. The RST pin is used to reset the 8051 microco
2. Power Supply and Ground Pins troller. To reset, 805 1, a high signa! should be
Pin-40 (V:): This is a power supply pin. An: applied to this pin for two machine cycles, wtie
external. D.C power supply of +5V iscomnected the oscillator is unning.
to this pin.
Q9. List the various registers present "
i Pin-20 (GND): This pin is the ground pin of
8051 and it is connected to the ground in order 8051 microcontroller and explain with an
to ground the circuit of 8051 microcontroller. example. Feb./March-22(R18), Q3b:

3. Oscillator Pins OR
XTALI,and XTAL2 are the input and output, of Describe briefly the register set of 80:!
amplifier. microcontroller. Dec.-17(RIJ),Q2

Tostart Oscillations in the circuit, a crystal must OR

be connected between XTALI (Pin-18) and
XTAL2 (Pin-19)pins. Explain register set of 8051i microcontroller.

May-16/R13), Q1
In case of externalclock generator, the output of
external psuillator (clock generator) connected to Answer:
nins XTAL2 and XTALIpins must be connected
to the ground.
The register set of 8051rmicrocontroller h
following registers,
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 NIT-4: Introduction to Micro Controllers and
What is the purpose of Interrupts Communication 157
o11. using VO ports of 8051?
Classify and explain them in detail.
Juty-23(R18), Q4(b)
Exolain the /O pins ports and OR
circuit details of 8051 witth its diagram. April-18(R13), Q94a)
what is the function of Port OR
3 of 8051
(Refer only Port 3) microcontroller? Dec.-17(R13), Q1(g)
ANSWer:

The 805I
P2and P3.
microcontroller has 32 /O pins which
are configured as 8-bit
bidirectionai parallel ports PO, Pi,
Cach pin can be used as
input or output or both.
Each port consists of a latch, an
output driver and an input driver.
t0: Port Opin circuit consists of a
Control Sighals latch, control logic unit, buffers and FETs T., T, as shown in figure
Address/Data
(1).
Read Latch Bit

Internal Bus Vcc

Write to Latch Control Pin
Logic 0.x

PORT SFR Latch

Read Pin Data

Figure (1): Port0 Pin Circuit Configuration

Pins 39-32 of this port can be configured either as
address and data bus for external memory. inputs or outputs or both as a bidirectional low order
Ifa port has to function as an input port then, the latch of port O
transistors. This makes the pin to float in a high impedance state isandmade high (1) by turning off the output
connects the pin tothe input buffer.
If a port has to. function as an output port then, the latch of port 0 is
made low turns on the lower FET, T, and connects the pins to ground.made low (0). The latch pins that are
The latch pins that are high will float.
So, an external pull up resistors are required.
Ifa port has to function as an address bus to the external memory then, the
internal
the address lines to the gate inputs of FETs. f an address bit is high, transistor T,control signals transfer
turns on and transistor
T, turns off. If an address bit is low, transistor T, tarns on and transistor T, turns off
providing
at the pin, Once the address is produced, the ALE puse latches the lower order address into thelogic low
external
circuits making the bus to go back and function as a data bus. To read the data from the external memory
itconfigures as an input port.
Port 1
Port l pin circuit çonsists of a latch, buffers, FET and nternal FET pull up as shown in fhgure (2)
Read Latch Bit
Vcc

Internal
Internal Bus FET
D
Pullup
Pin
Write to Latch l.x

PORT SFR Latch

Read Pin Data

Figure (2): Port 1 Pin Circuit Configuration

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JNTU-HYDERABAD)
Pins 1-9 of this port cam be configured only as Pins 10-17 of this port
can be configured only as
port I.
I/0 pins. I/Opins similar to
The i/O pins of port 3are multifunctional. Apart
aport has to function as an input port then, the
also serve the
latch of port lis made high (1) by turning offthe from being port pins, they functions
output transistor. The FET load pulls up the pin of various special functional registers such as,
andits bufter and makes the pin to float in a high p3.0-RxlD :Used for receiving serial ato
impedance state. This problem is eliminated by
adding an external circuit. The external circuit P3.1-TxD : Used for transmitting serial data
drives the input low to logic 0 or input high to
logic 1. P3.2- INTO : Used for external interrupt 0
If a port has to function as an output port, the P3.3- INTI :Used for external interrupt j
latch with high input drives the external circuit P3.4-TO :Used for external tiner 0 iDut
inputto high using the internal FET pull up and :Used for external timer 1 inDut
P3.5-TI
the latch with low input drives the external circuit
input to low turning on/off the FET and internal P3,6- WR :Used for externaB data memory wpite
FET pull respectively. signal
Port 2
P3.7- RD .Jsed for external data memory read
Port 2 pin circuit consists of a latch, control logic
signal.
unit, buffers, FET and internal FET pull-up as shown in
figre (3). Q12. Explain the logical separation of program
Control Signals and data memory.
Address
Read Latch Bit
Vec Answer: Dec.-19(R16), Q4a)
Internal
In 8051 micro controller, the program and data
Internal Bus D o FET
Pullup
memory is logically separated i.e., they have
Pin
Wite to Latch
Control
2.x
different address spaces.
Logic
The logical separation enables the 8-bit addreses
PORT SFR Latch
to access the data memory which can be stored
Read Pin Data
and manipulated more easily. Data memory of
Figure (3): Port 2 Pin Circuit Configuration 8051 has 256 bytes of intermal data memory and
Pins 21-28 of this port can be configured only as 64 kB of external data memory.
VO pins similar to port 1. It is possible to generate 16-bit data memory
Port 2 pins produce higher order address byte address by using DPTR register.
outpüt with the lower order address byte of port
0 to access the external memory. The prOgram memory is a read oniy memory.
When a higher order address byte output 8051 has 4096 (4K) bytes on internal programn
produces, the address control signals temporarily memory of 8081 can address 4 kB of on-chip
alter its port pins. program memory and 64 kB of external program
Port 3 memory. These two memories will overlap
Port 3pin circuit consists ofa latch, NAND gate, hence, they can be differentiated by using PSEN
buffers, FET and internal FET pull-up as shown (Program store enable) signal.
in figure (4).
Alternate Output The PSEN signal serves as the read strobe to the
Read L.atch Bit
Vec external program memory and enable its contents
to the 8051.
Internal
nernal Bus
FET
Pullup While accessing the external data memory, sUi
Write to Latch | Pin
|3.x
produces read (RD) and write (WR) signals.
PORTSFR Latch With RD and PSEN signals as inputs and rea
strobe to the extemai program/data memory e
Read Pin Dala Output to on AND gate, both external progra
com-
Alernale Input be
memory and external data memory can
Figure (4: Port 3 Pin Cireuit Configuration bined.
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NIT-4: Introduction to Micro Controllers. and Interrupts Communication 159
Discuss about memory organization of 8051 July-23(R18),Q44a)
microcontroller.
OR
Cxolain the concept of memory organization of 8051 microcontroller. Dec.-18(R13), Q8(a)

In 8051 mierocontroller, the available memory space is segregated as program memory and data memory.
Program memory contains the programs which have to he executed. It is imolemented using EPROJM.
Data mennory contains the intermediate results, variables and constants which are
necessary tor exeGuting
theprogran. t is implemented using RAM.
Program memory and data memory are again segregated as internal memory and external memory.
rogTAm memory

s051 microcontroller can address 4KB of on-chip program memory (0000H-OFFFH) and 64KB Of
external
program memory (0O0H-FFFH). These two memories will overlap hence: they can be differentiated by using
the PSEN signal.

Program memory is accessed through EA pin.

- If EA is high, then internal program memory is accessed till OFFFH memory location and externai
program memory is accessed from 1000H to FFFFH memory location.
’If EA pin is low, only external program memory is accessed from 000OHtoFFFFH memory locations
(64 k).
The program memory organization of 805 1is shown in figure (I).
FFFFH FFFFH
External
program
memory 64 k bytes
external
1000H
program
OFFFH memory
Internal
program
memory
0000H 0000H
(i) EA = 1 (ii) EA =0

Figure (1): Program Memory Organization

ata memory
8051 has 256 bytes of internaldata memory (00tH-FFH) and 64 KB of extermal data memory (0000H-FFFFH).
Aernai data memery
internal data memory of 256 bytes has two partitions;
00H-7FH for internal data RAM
2 80H-FFH for special function registers
Internal data RAM can beaccessed using direct or indrect addressing mode whereas memory for snecial
drect addressing mode.
uCion registers can be accessed only by using
The address map of 8051 for different versions with 256 bytes of internal RAM is from 00H to FFH. In
this, the address map of SFRs will overlap the upper l28 bytes of RAM. So, to differentiate the memories,
addressing mode is used.
accessed using indirect addressing mode
Upper 128 bytes ofinternal RAM is
addressing mode
Lower 128 bytes of internal RAM IS aceessed tusg drect or ndirect
2

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 ROM

000011

Figure (2): Internal ROM Organization

SOSI has 4kB internal ROM to store program
codes in the address space 0000H to 0FFFH.
Program addresses higher than OFFFH, causes the 8051 to
program memory. automatically fetch code byte from external
A1.3 Addressing modes and
Instruction set of 8051
Q15. List various addressing modes of 8051
each. microcontroller and explain them with an example
Fsb./March-22(R18), Q4(b)
OR
Explain about different addressingmodes of 8051
microcontroller.
OR
Discuss various addressing modes employed in 8051 uC with
examples.
Answer :
The way of specifying the operand (source or destination) in the mnemonics
as Addressing mode. There are five addressing modes in 8051 which are that moves the data is referred
described below,
Immediate Addressing Mode: In this mode, the source operand is a constant i.e., the
instruction itself. This addressing mode can be used to load information into any of operand is given in the
the registers including
DPTR register. It is also used to send data to 8051 ports.
Opcode data
Examples
1. MOVB, #data ;Load data into B
2. MOVDPTR, #0ABCDH ;DPTR - 0ABCDH
3. MOV R3, #51 ;Load the decimal SI into R3
The i6-bit DPTR can be açcessed as two 8-bit registers DPH and DPL.
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ee

Example
MOV IPTR#2550H can be written as,
MOV DPL, #50H
MOV DPH, #25H
2,
Register Addressing Mode: In this mode, the registers are used as address oftheoperand. The least signihicans
three bits of the instruction opcode indicates one register. Thus, a function code and operand address can
combined to fornm a one byte instruction.
Register
Opcode RO R7 in current bank

Exampies
1. ADD A, RO ;Contents of R0and A are added
2. MOV R7, DPL ;Content in DPL is moved to R7
3. MOV R6, A ;Save contents of ACC in R6
The source and destination registers must have same size.
This mode cannot be used between two Rn registers.
Example: MOV R4, R7 is invalid.
3 Direct Addressing Mode: All 128 bytes of internal RAM and the SFRs may be addressed directly
the single byte address assigned to each RAM lócaion and each special function register. In this using
mode, the data is in RAM memory location whose address is known and this address is addtessing
the instruction. given as a part of

Opcode RAM
Address

Examples
1 MOV RO, 40H ;Loading data in address 40H to RO
2. MOV 0A8H, 77H ;Loading data in 77H to 0A8H address
3 MOV 56H, A ;Load content of A in
;RAM location 56H
4. Register Indirect Addressing Mode: In register indirect addressing
address of an operand located in RAM. In other words, mode, a register is used to hold the
a register is used as pointer to the data.
If the data is used inside the CPU, The registers R0
and Rl only are used whereas R2 -R7 cannot be used.
The RO and Rl are preceded by @' sign.

Opcode
Register RO or RI in current bank
Example
1 MOV A, (@RO; Move contents of RAM location whose
address is held in RO into A
2 MOV (aRI, B;Move contents of Binto RAM location whose
address is held in RI
5 Indexed Addressing Mode
It is used to access data ¢lements of look-up table entries located
in the program ROM space of the 30
The instruction used for it is
"MOVC A,@A+DPTR".
It copies the contents of ROM address formed by (A +
DPTR)into the accumulator.
The data elements the saved in the program (code) space of
means codel instead of MOV.
8051, so, the instruction MOVC IS Us

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 lotroduction to Micro Controllers and Interrupts 163
INIT-4:

Communication
0t uses either program counter or data pointer as the base register and an offset (the accumulator) to form
etive address for aJMP or MOVC
Base register
inistruction.
offset ËA
PC or DPTR + ACC
Dalative addressing is only used for specific jump
instructions.
Arelative address (or offset) is a signed 8-bit value that is added to the
le address of the next instruction to be program counter (PC) to determie
executed.
Opcode Relative offset
Relative addressing (e.g., SJMP AHEAD)
The signed 8-bit offset gives the address range of -128 to+127 1ocations to
offset is added as an extra byte to the instruction. IUMP instruction. The relative
Before the addition, the PC is incremented to the address afer the iump
address is related to the following instruction and not the instruction; therefore, the new
address of the jump instruction.
Typically, jump destinations are defined as labels, and the assembler cálculates the relative offset
accordingly.
Example
010A
0109
0108
0107
0106 4
Relative offset
0105 3 from address
0102H is «g»
0104 2

0103 1

0102
0101 05
HsJMP 0107H
0100 80

0OFF

Code
memory
If the label. THERE represents an instruction at location 0107H, and the instruction
SJMP THERE is in
memory at locations 0100H and 0101H, the assembler will assign a relative offset of SH as byte 2 of the
instruction (0102H+ SH = 0107H).
¢n advantage of relative addressing is that the program code is easy to relocate in
memory in that the
addressing is relative to the position in memory.
Absolute Addressing Mode
Absolute addressing is used only with AJMP (Absolute Jump) and ACALL (Absolute Call) instructions
These 2-hvte instnuctions alow branching within the current 2K page of code memory by
providine the 1l
LSB of the destination address in the opcode (ATCA8) and byte 2 of the instruction (A7-A0)
A15 -A8 A7- A0
Opcode
Long addressing (e.g., LJMP FAR AHEAD)

The upper five bits of the destination address are the current upper five bits in the PC, so the instruction
following the brançh instruction and the destination for the branch instruction must be within the same 2K
Page, since A15-A11 do not change.

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164 MICROPROCESSORS AND
MICROCONTROLLERS
IJNTU-HYDERABADI
FFFF
2K pagc 31

F800

I000 32 × 2K 64 K
17FF
Within any 2K
page, only the lower 2K page 2
1lbits change
1000
OFFF
2K page l
0800
07FF

0000 2K page 0

(a)

A15 A10 A0

Upper 5 bits determine 11bits determine the

the 2K page address within a 2K page
(b)
Figure: Instruction Encoding in Absolute Addressing
For example, if the label THERE represents an instruction at address OF46H, and the instruction 0752 is in
memory locations 0900H and 0901H the assembler will encode the instruction as
I11000001 -1" byte (A10 -A8 +opcode)
0 10000 110 - 2nd byte (A7- A0)
The underlined bits are the low-order 1l bits of the destination address, OF46H= 0000111101000110B. Ine
upper five bits in the program counter will not change when this instruction executes.
Both the AJMP instruction and the destination are within the 2K page bounded by 0800H and OFFFH(hgure
and therefore have the upper five address bits in common.
Absolute addressing offers the advantage of short (2-byte) instructions, but has the disadvantages of
the range for the destination and providing position dependent code. limie
Q16. Classify the 8051 instructions into one byte, two byte and three
byte instructions.
Answer :
The instructions of 8051 can be çlassified into many ways but based on the length, they are classified into
three types,
1. One-byte fnstruction: One-byte instruction represents both opcode and
operand by a group Qt o
Examples: (i) ADD A, Rn
(iü) ORI. A, Rn
(iii) CLR

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 pomtei
Bytes: 1
Cycles: 2
(v) NOP( No Operation)
Operation: It does nothing. It is used to generate a delay in execution. The execution continues with the
next instruction.
Bytes: 1
Cycies: 1.
41.4 Simple Programs using StackPointer
Q23. Expiain how stack is implemented in 8051 C?
OR
How stack are accessed in the 80517
Answer:
Stack Operation in 8051
Siack is asection of RAM used by the CPU to store the information temporarity. The register used to accese
the stack is called SP (stack pointer) register and it is 8 bits wide.
The address held in stack pointer is the location in the internal RAM, where last byte of data was stored by
stack operation.
The 8 bit Stack Pointer (SP) register is used to store the address of internal RAM, hence it is called as "on
of the Stack".
When 8051 is turned on the SP register has value 07. So, 08H in the RAM location is the first location used
for the stack by the 8051.
SP points to the last used location of the stack.
By using two operation, the data'can be inserted into the stack as well as, the data
stack i.e., can be deleted from the
() PUSH
(ii) POP.
By using PUSH operation, the data can be inserted into the
last row
by incrementing the stack pointer i.e., illustrated in the figure as of the stack and next data can be inserted
shown below.
By using POP operation, the data can be retrieved from
from the stack, decrementing the stack pointer after the first row of stack and next data can be retrieved
getting the data from the stack as illustrated in the figure.
CPUAction CPUAction Retrievl
OA Store Address 0A Get SP

09
SP StoreAddress 09 Get 09 SP

SP 08
StoreAddress 08 Get SP

SP 07 Address 07 07 SF
Ihsertion
Increment of SP)
(Decrement of SP)
Figura: Stack Operation
Upper Limit of Stack
TheRAM location 08H to 1FH (24 bytes) is assigned
TEmte than 24 bytes is to be used by to stack.
stack, then the SP points to RAM
locations 30H -7FH.
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 NIT4:Introduction tó Micro Controllers"andlnterrupts Communication 179

rOgrams

The stack pointer (SP) is an 8-bit register used by the 8051 microcontroller to manage the stack. By default,
initialized
to 07H after areset.
is
itdProgram Push and Pop Operations
This demonstrates the use of push and pop instructions to store
program and retrieve data from the stack.
(ORG00H ;Origin address
MOVSP, #30H ; Initialize stack pointer to 30H
MOV A, #55H ; Load A with 55H
PUSH ACC ; Push A onto the stack:
MOVA, #0 ; Clear A
POP ACC ;Pop the top of the stack into A
uERE: SJMP HERE;Infinite loop to end the program
END
Program 2: Subroutine Call and Return
This program demonstrates callinga subroutine and returning from it, utilizing the stack to store the return
ddress.

ORG 00H ;Origin address

MOV SP, #30H ; Initialize stack pointer to 30H
MOV A, #5SH ; Load A with 55H
LCALL SUB ;Call subroutine
HERE: SJMP HERE ;Infinite loop to end the program
SUB: MOVA, #AAH ; Load A with AAH (Subroutine action)
RET ;Return from subroutine
END
# Program 3: Saving and Restoring Registers
stack.
This program saves and restores register values using the
ORG 00H Origin address
MOV SP, #30H Initialize stack pointer to 30H
MOVR0, #11H ;Load RO with 11H
MOV R1, #22H ;Load R1 with 22H
PUSH O ; Push ROonto the stack
PUSH 1 ;Push R1 onto the stack
MOV R0, #0 ;Clear RO
MOV R, #0 ;Clear RI
RI
POP 1 ;Pop the stack into
RO
POP 0 ; Pop the stack into
HERE: SJMP HERE : Infinite loop to end the program
END
Program 4: Stack Pointer Manipulation manipulation of the stack pointer.
manual
s program demonstrates
ORG 00H ;Origin address
pointer to 30H
MOV SP, #30H ; Initialize stack
5SH
MOV A, #55H : Load A with
the stack
PUSH ACC ; Push A onto
pointer manually
MOV SP, #2FH :Decrement stack
the stack into A
POP ACC Pop the top of
the program
HERE: SJMP HERE : Infinite loop to end
END
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 180 MICROPROCESSORS AND MICROCONTROLLERS LJNTU-HYDERABAÐI
### Program 5: Nested Subroutine
Calls
Ihis program demonstrates nested subroutine calls and uses the stack to manage return addresses.
ORG 0OH
;Origin address
MOVSP, #30H ; Initialize stack pointer to 30H
MOVA, #55H ;Load A with 55H
LCALL SUBI ;Call first subroutine
HERE: SJMP HERE :Infinite loop to end the program
SUBI: MOV A, #AAH ; Load Awith AAH (Subroutine I action)
LCALL SUB2 ;Call nested subroutine
RET ; Return from subroutine 1
SUB2: MOV A, #BBH :Load A with BBH (Subroutine 2 action)
RET :Return from subroutine 2
END
### Program 6: Saving and Restoring Multiple Registers
This program demonstrates saving and restoring multiple registers using the stack.
ORG 0OH
;Origin address
MOV SP, #30H ;Initialize stack pointer to 30H
MØV RO, #11H ;Load R0with 1lH
MOV RI, #22H ;Load RI with 22H
MOVR2, #33H ; Load R2 with 33H
PUSH O ; Push ROonto the stack
PUSH 1 ; Push RI onto the stack
PUSH 2 : Push R2 onto the stack
MØV RO, #0 ;Clear RO
MOVR1, #0 :Clear RI
MOV R2, #0 ;ClearR2
POP 2 ;Pop the stack into R2
POP 1 ;Pop the stack into RI
POP 0 ;Pop the stack into RO
HERE: SJMP HERE :Infinite loop to end the program
END
### Program 7: Stack Overfiow Detection
This program demonstrates a simple method to
detect stack overflow by checking the stack pointer
ORG 00H value.
;Origin address
MOV SP, #30H ; Initialize stack pointer to 30H
MOV A, #5SH ;Load A with 55H
PUSH ACC
;Push A onto the stack
CJNE SP, #FFH, NO OVERFLOW
;Compare SP with FFH, if not equal, jump to NO
SETB P1.0 ; Set P1.0 (indicate stack OVERFLOW
overflow)
NO_OVERFLOW:
MOV A, #0 ;Clear A
POP ACC ;Pop the top of the stack into A
HERE: SJMP HERE
Infinite loop to end the program
END
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 to Micro Controllers and 181
Communication
Interrupts
I n t r o d u c t i o n

sIT4:
P r o g r
Recursive Subroutine
a m
8:
ew demonstrates a simple recursive subroutine: Note that the 805 1 is not
program optimized for recursion,
This
Cxampleis purely illustrative.
ORG 0 0 H :Origin address
MOV SP. #30H ; Initializestack pointer to 30H
MOV R0, #3 ; Set the rccursion depth
LCALL RECURSE
:Call the recursive subroutine
HERE:SJMP HERE ; Infinite loop to end the program
RECURSE:

CUNE R0, #0, CONTINUE : If RO is not 0, continue recursion

RET ;Otherwise, return from subroutine
CONTINUE:

DEC RO ; Decrement RO
LCALL RECURSE
; Recursively callthe subroutine
INCRO ;Incremcnt RO (back to original value before returning)
RET ;Return from subroutine
END
Program 9: Interrupt Service Routine (ISR) Using Stack
Thisprogram demonstrates handling an interrupt and using the stack to save the context.
ORG 00H ;Origin address
MOVSP, #30H ; Initialize stack pointer to 30H
SETB EA ; Enable global interrupts
SETB EX0 Enable external interrupt 0
HERE: SJMP HERE ; Infinite loop to wait for interrupt
; Interrupt Service Routine for external interrupt 0
ORG 0003H
ISR EXO:
PUSH ACC ;Save accumulator
PUSH PSW ;Save program status word
MOV A, #0AAH ; Perform some action in ISR
POP PSW ;Restore programn status word
POP ACC ; Restore accumulator
RETI ;Retürn from interrupt
END
#Program 10: Using the Stack for Parameter Passing
This program demonstrates passing parameters to a subroutine using the stack.
ORG 00H ;Origin address
MOV SP, #30H ;Initialize stack pointer to 30H
MOV A, #0FH ; Load A with the first parameter
PUSH ACC : Push the first parameter onto the stack
MOV A, #1FH : Load Awith the second parameter
PUSH ACC :Push the second parameter onto the stack
LCALL SUB ;Call subroutine
HERE: SJMP HERE :Infinite loop to end the program
SUB:
POP ACC ;Pop the second parameter from the stack
MOV B, A ;Store the second parameter in B
POP ACC ;Pop the first parameter from the stack
MOV R0, A :Store the first paraneter in RO
; Perform some operation with parameters in RO and B
RET :Return from subroutine
END
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 182 MiCROPROCESsORS AND MICROCONTROLLERS [JNTU-HYDERABAD
addresses and errors that are detected by the assembler.
4.1.5 Assembly language
80513 programming o This file is optional, because it is not used; much and this
is accessible only with the help of editors. One can view
Q24. Define the terms machine the syntax errors in the code and only after correcting
language,
assembly language and mnemonics. these errors, the object file is ready to link with other
Answer: required files.
Machine Language After this object code is given to a linker progran
that generates a file with extension .abs', which is
A language that allows the programmers to read
and write the instructions only in binary number format referred as absolute object file. This file is then fed to
is called machine language. Machine language is a low OH (Object to Hex converter) program that generates
level programming language and it is casily understood an equivalent program called 'hexfile' with extension
by CPU. However, machine language is highly impos *hex'. The hex file obtaíned is wTitten into ROM of
sible for
humans to use since, it comprises of binary microcontroller which is ready to perform the operation
numbers i.e., 0's and 1's. The following flowchart illustrates the total
Example: Machine language instruction is, process of assembling and running an 8051 program
1000001000000110 Editor program
Assembly Language myfile.asm
A language that allows the programmers. to
read and write the instructions in a naming or keyword Assembler
format is called assembly language. Assembly language program
possesses same structure and set of commands as that
myfile.lst
of machine language but allows the programmer to use
named instructions instead of binarynumbers. It is easily myfile.obj -other obË files
understood by humans but hard for CPU. However,
Linker program
the programs written in assembly language need to be
translated into machine language. Thus, this can be done
myfile.abs
by using a program called assembler.
Example: ADD A, A7 OH program
Mnemonics
The predefined names allotted for machine myfile.hex
instructions in an assembly language is called mnemonics.
Figure: Assembling and Running 8051 Program
Example: MOV RS, #25H
Q26. Explain the basic structure of assembly
language.
Mnemonic Operands Answer:
Q25. Write the process of assembling and
running'an 8051 program. An assembly language instruction contains four
fields label, mnemonics, operands and comments. The
Answer: general structure of instruction is shown below.
The assembly language program is first written
using an editor. There exists different types of editors like [label:] mnemonic [operands] [; comment)
Notepad in Windows or MS-DOS EDIT program. The bracket specifies that they are optional.
most widely used is the MS-DOS EDIT program, as it Label: Label is a symbolic name given to a branch of
is available in all Microsoft operating systems. The only instructions for which the program is referred. The
condition on an editor is that it must be able to produce length of the label fields limited to certain
an ASCII file. and l¡bel is not mandatory to exist in an characterS
the label field is optional. instruction. So,
Assembling and Running: The code written in an editor
is known as source code. Depending on the type of Mnemonics: Mnemonics are predefined words allocate
assembler used, the extension of the source code varies to machine instruction.
Iike 'asm' or 'src'.
Operand: Operand represents the data available in
This source file is fed to an 8051 assembler, The registers and addresses to be operated. u
assembler converts the total program (instructions) into Comment: Comment field describes each line in the
machine code. Thus, the object file is created as outout program so that it becomes reasier for the
along with a list file with extensions ".obj' and lst' to read and understand thecode. programnc
respectively. The list file consists of all the opcodes. and starts with Comment is optioa
semicolon (;)
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 Inntroduction to Micro
T4:
Controllers ahd interrupts 187
The four register banks are labelled
as Bank Communicatio
1, Bank 2 and Bank 3 and the eight Overflow Flag (0OV)
sank
working
stersin cach register bank are named as RO to R7. It is set whenever the result of a sigmed umber
is addressable either by its
hregister

name or by its operation is too large causing the higher order bit to fiow
M address.
into the sign bit.
Onlyone register bank is used for an Parity (P)
instant.
knows the register bank that is currently in CPU
PSW..3 (RSO) and use Itis set if register A
contains oddnumber of ones
bythe bits PSW4 (RS1) in
status word as shown in table the and elearcd if register A has even number of ones.
program

below. User Flag (FO)

RSI RSO Register Bank Address This flag is set/cleared by software as a user de
00 H -07 H fined status flag. User flag is also calied general purpose
flag.
08 H -OF H
RSO and RS1: Register Bank Selector bits
2 10 H-17 H
3 18 H-1FH RS1 RSO Register Address
bank
Table
00- 07H
Bank Ois the default register bank as it is selected
an reset. These register banks can 1 08- OFH
be used as
general purpose RAM when not selected. 2 10- 17H
The PSWN.34 and PSW.4 can be
accessed by bit 1 3 18- 1FH
addressable instructions SCTB and CLR.
Table: Register Select Bits
smple: SETB PSW.3 will select bank register 1.
The ADD instruction affects the flags CY, P, AC
. Draw the functional block diagram of 8051 and OV.
uC and explain the functioning of PSW
Stack Pointer
register and stack pointer.
SWer : For answer refer Unit-4, Q6, Topic: Stack Pointer.
Functional Block Diagram 4.2 INTERRUPTS oMHuNICATION
For answer refer Unit-4, 06. 4.2.1 Interrupts, Interrupt Priority in the
SW Register 8051
Program status word (PSW) is an 8bit register Q32. Explain the interrupt structure of 8051
tch provides the ALU status information. PSW Microcontroller. July-23(R18), Q5(a)
ains four mathematical or math flags, one user OR
TAm iag and two register select bits as shown in Classify and explain the instruction set
of 8051 microcontroller. Aug.-22(R18),
4 3 2 Q3(b)
AC FO OV
OR
RS1 RSO
Define interrupt and Explain different
Figure: PSW Register software interrupts used in 8051
arTy Flag (CY) microcontroller.
it is set to 1,ifthere is a carry from MSB, i.e., Answer :
OR otherwise cleared to »0. It is used in arithmetic, Interrupt
, rotate and boolean instructions.
An interrupt is a signal either from hardware or
a Can be set to i using the instruction SETB C from a program that interrupts the normal processing of
ud cleared to 0 using "CLR C"", the CPU,
lIS affected by 8-bit addition or subtraction.
Rliary Carry Flag (AC) Interrupt Structure of 8051
It is set to 1 if there is a carry or borrow from The 8051 have five interrupts which are available
t to 4th bit, otherwis cleared to 0'. It is used for to users, But many manufacturers data sheets have six
arithmetic operatións.. interrupts, since they include Reset.
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 188 MICROPROCESSORS AND MICROCONTROLLERS JNTU-HYDERABAN

The six interrupts in 8051 are as follows.

location 0000H.
Wnen reset pin is cnabled, thec 80S1 imnediately goes to nemory
2.
IWO inerupts are from timers i one for timer) snd ahother for timerl. The address location of ti
interrupt is O003H and timerl interrupt is 001191.
3- hit
3.
I\WO interupts fioDm Cxternal inputs INTO and INTI), Pins of port 3, port 3- bit 2 (P3.) and port
(P3,3) are for extemal hardware interrupts INTOand INTI respectively. These externat interrupts are knou
as EXland EX2, The address location of INTO is 0003H and INTI is 0013H.
Senalcommunication contains only oneinterrupí which is uscd for both transmissiöi and reception.
Table below shows the interrupt vector table for the 8051.
ROM Location (Hex) Pin internal RAM(Hex)
Interrupt
Reset 0000 Auto
External hardware interrupt to (INTO) 0003 P3.2(12) Auto
Timer 0 interrupt (TFO) 000B Auto

Extermal hardware interrupt 1(INTI) 0013 P3.3(13) Auto

Timer Iinterrupt (TF1) 001B Auto
Serial COM interrupt (RJ and TI) 0023 Clears by programmer
Table: Interrupt Vector Table
Q33. Explain how a microcontroller provides services to many external devices.
Answer:
A microcontroller can provide service to many devices. This can be done in two methods.
1., Polling 2. Interrupt.
Polling: In this method, the microcontroller repeatedly tracks the status of a given device. If the condition
is met, mirocontroller provides service to that device and moves to another device to check the status of
that device. So, this process is continued until every device is served. Since, microcontroller is concerned
with checking the status of the device, polling is not an efficient way.
2. Interrupt: Ifany device requires service, then it sends an interruptsignal as a notification to microcontroller.
As soon as the interrupt signal is received by the microcontroller, it suspends its task and provide service
to the device. The microcontroller provides services to an interrupt by executing a
program called Interrupt
Service Routine (ISR).
034. What is an interrupt and explain how an interrupt is handled in 8051
microcontroller?
OR
Give the sequence of events that takes place when the interrupt
occurs in 8051.
Answer :
0nterrupt
For answer refer Unit-4, Q32, Topic: Interrupt.
Interrupt Service Routine: Each interrupt has an Interrupt Service Routine (ISR).
the microcontroller branches to the ISR. For each interrupt When an interrupt is recognized,
of its ISR. The group of memory locations set aside to there is a fixed location in memory that holds the addrss
hold the addresses of ISRs is called the interrupt vector
Steps in Executing an Interrupt: The 8051 examines the taoie.
Once the interrupt is recognized the miçrocontroller interrupts at the end of everymachine cycle (S6 state}
goes through the following steps,
Completes the executing instruction and saves the address of the
next instruction (PC) on the stack.
2 Saves the current status of all the interrupts internally (not
on the stack).
3. it junps to a fixed location in memory called
the interrupt vector table that holds the address of
service routine. the intetup
4. The microcomputer gets the address of the
ISR from
executing the interrupt service subroutine until it reachesthetheinterrupt
last
vector table and jumps to it. It sa
(return from interrupt). instruction ofthe subroutine which is K
5. Upon executing the RETI instruction, the micro-controller returns to the place where it was interrupted.
Pirst it gets theProgram Counter (PC) address from
the stack by popping the top two bytes of the
the PC. Then it starts to execute from that address. stack
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 190 (JNTU-HYDERABADI
MICROCONTROLLERS
VGROPROCESsORS AND
4:2.2 Timer/Counter and Sertal Communication
Xplain the concept of timers and counter of 8051 microcontroller.
Answer:
Basic Registers of Timer
timer1. Each timer register 1s of 16-bit wide
U1 mtcrocontroller consists of two timers ie.. timer) and
two registers as shown in hgurebelow
Snee, sUST is a 8-bit microcontroller. each register is separated into
THO

D1sDa| Ds D Dul DI D9DsD7Do DSs D4 D 2 DiDO

Figure (1);: Timer0 Registers

THI
TL

Dis Dia DI3|DI2Du DIo D9 D8|D7 D6 DS D4 D3 D2 DIDO

Figure (2): Timer1 Registers
Where,
DO-D7-Lower byte register
D&-D15- Higher byte register.
Timer0 16-bit register separated into two registers TLO and THO. TLOrepresents lower byte register and
THO represents higher byte register. Timer0 register is used in the same way as registers A, B, RO, R1, R2
etc.

TimerI is a l6-bit register separated into two registers TLI and TLI. TH1represents lower byte register
and THl represents higher byte register. Timerl register is accessed similar to timerO.
The timers 0 and I use TMOD register for setting different modes.
Q37. Describe the operation of timers present in 8051 microcontroller. FebJMarch-22(R18), Q3{a)
OR
Describe TMOD register.
Answer :
Timer Mode Register (TMOD): Timers of 805Imicrocontrollers has four types of modes namely mode 0, model,
mode 2 and mode3. Seletion of aparticular mode is done by setting mode bits M1 and MO in a register
known as
Timer Mode register (TMOD) as shown in figure.
7 4 3 2
Gate CT MI MOGate C/T| MI MO
Timer 1 Timer 0
Figure: Timer Mode Register (TMOD)
Gate
The gate bit decides the hardware or software control over
timer/ counter.
When TRx bit in TCON register =1,
If Gate = | then, Timer/Counter x is enabled when
INTx is high i.e., hardware control.
(i) If Gate =0 then, Timer/Counter x is enabled only
when TRx is high i.e.. software control.
Where, x indicates I/0.
cr: The timer/counter bit decides the type of operation
(timer or counter) to be performed.
JfC/T= 1, counter operation is performed.
IfCT= 0, timer operation is performed.
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 rate.
For XTAL= ll.0592 MHz 57.600
and 921.6 kHz / 16 = Hz since
Machine cycle frequency |L.0592 MHz / 12 = 921.6 kHz
SMOD |.
rate.
Ihis is the frequency used by Timer lto set the baud
for SMOD 0and SMOD=lare as follows,
For XTAL =|1.0592 MHz, the baud rates
THI Decimal Hex SMOD=0 SMOD =1
-3 FD 9600 19,200

-6 FA 4800 9600

-12 F4 2400 4800

--24 E8 1200 2400

42.3 Programming of 8051- Timers, Counters and Interrupts

Q56. Discuss in detail about timers ánd counters of 8051 microcontrolier.
Answer : JunelJuly-22 Q11b)
Timer/Counter
For answer refer Unit-4, Q36.
Modes of Operation
Mode 0
It is al3-bit timer register which consists of all 8-bits of TH1 and lower 5-bits of TL1. The upper 3-bits of
TLI are indeterminate and should be ignored.
It allows loading of values between 0000H to 1FFFH in TH and TL registers.
Once the registers are loaded, the timer starts by setting the run bit, TR using the instructions SETB TRO
for timer 0 and SETB TRI for timer 1.
Once the timer starts, it counts till the maximum value (1FFFH) is reached and then rolls to 0000H setting
the flag bit, TF high.
When TF = 1, the timer stops and clears the flag bit using the instructions ÇLR TRO for Timer 0 and CLR
TRI for Timer 1.
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 UNIT-4:introduction to Micro Controllers and Interrupts Communication 203
Operation of mode Ois illustratèd in figure (1).
OSC
2
THO TL,0 J TEO 7Internupt

tor 8 bits) (S bits)

Control
opin
TRO

Gate
INTÖpin

Figure (1)}: Mode 0 Operation

Mode 1

It is a l6-bit timer register which allows loading of values between 0000H toFFFFH in TL and TH registers.
Once the registers are loaded, the timer starts by setting the run bit, TR using the instructions SETB TRO
for timer 0 and SETB TRIfor timer 1.
Once the timer starts, it counts till the maximum value (FFFFH) isreached and then rolls to 00001 setting
the flag bit, TF high.
When TF=1,the timer stops and clears the flag bit using the instructions CLR TROfor Timer 0 and CLR
TRI for Timer 1.
Operation of mode 1 is illustrated in figure (2).

XTAL TH TL TF
+12
oscillator
overfiow
TF goes high
when FFFF>0 fiag
C/T=0. TR

Figure (2): Mode 10peration

Mode 2
It is an 8-bit timer register which allows loading of values between 00H to FFH in TH register.
Mode 2 has auto-reloading capability.
In auto-reloading, once the register is loaded, 805 l gives the copy of TH to the TL register. Then, the timer
starts by setting the run bit, TR using th» instructions SETB TRO for timer 0 and SETB TRIfor timer 1.
Once the timer starts, it counts by incrementing the TL register until the maximum value (FFH) is reached
and then rolls to 00H setting the flag bit, TF high.
When TF=1, the TL register automatically reloads the original value from TH.
Operation of mode 2 is illustrated in figure (3).
overflow

XTAL TL TF flag
+12
oscillator
reload TF goes high
TR when FF ’0
C/T=0
TH
Figure (3): Mode 2 0peration
Mode 3
Timero and i can be programmed in mode 0,1 or 2independently. This does not hold good for mode 3.
Placing timer inmode 3 causes it to stop counting. The control bit TRI and the timerl flag TFl are then
ised by timero, TimerO in mode 3becomes two completely separate 8-bit counters, TLOiscontrolled by the
gate arrangement andsets timer flag TFO whenever lt overtoWs from FFH to 0OH. THO receives the timer
Clock 1 under the control of TRÍ only and sets he 1F lag when it overfrws
SPECTRUM ALL-IN-ONE JOUKhL POR ENGINEERING STUPENTS
 (JNTU-HYDERABADI
204 MICROPROCESSORS AND MCROCONTROLLERS

Operation of mode 3 is ilustrated in tigure (4).

OSC 12 (/12) f,n
TLO
(8 bits) TFO Interrupt

To pin lControl
TRO
Gate

INTO pin THO

(8 bits) TFI interrupt
Control
TRI
Figure (4): Mode 3 Operation
Q57. Write 8051 program to initialize timer1in mode 0.
Answer :
Initialy, TMOD register must be configured for timerl operation in mode 0 as shown below.
Timer 1 Timer 0

Gate CT MI MO Gate CT MI MO
1 0 0 0

6 3 2

Consider timerl bits (i.e., four MSB's) of TMOD register

1
Since timerl is tobe initialized, the gate' bit of timer1 in TMOD register should be set to 1.
2. C/T bit should be 0 for timer operation.
3. Mode bits MIM0 must be 00 for operating in mode 0.
And rest ofthebits
of the TMOD rgister
are initialized with zeros. Hence, the §-bit hexadecimal data formed by the above settings
bits is 80 H.
TRIbit in TCON register is set to start timer1. Since, TCON register is bit addressable, TR1l bit is set using
SETB instruction. Then, timerl operation can be terminated using CLR instruction i.e., once TRI bit is reset, timerl
stops its operation.
The program to initialize timerl in mode 0 is as follows,
MOV TMOD, # 80 H;Configuring TMOD register for initializing timerl in mode 0.
SETB TRI :Timer l run operation starts.
CLR TRI ;Timer1 run operation is stopped:
SJMP ;Infinite loop.
Q58. Discuss in detail about the programming of timers of 8051 uC in
various modes of operation.
OR
Write the mode 2 programming of timers in 8051 in detail.
Answer:
Timer0 and timerl performs the same operation in mode 2.
operation.Flag TFl setiwhen TLloverflows and THI contents äre Timerl is an 8-bit counter (TLI) in mode 2
through software therefore timer 1/0in mode 2 contributes loaded into TLI. TH can also be loaded
operation
with auto reload operation in mode 2 is shown in figure below. with automatic reload. The mechanism of timer
TLI
Overfow Interrupt
TFI

Reload

THI

Figure
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