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Part A : List of Experiments using discrete components

1. RC integrating and differentiating circuits
2. Clipping and clamping circuits
3. RC coupled CE amplifier - frequency response characteristics
4. Cascode amplifier -frequency response
5. Low frequency oscillators –RC phase shift or Wien bridge
6. Transistor series voltage regulator (load and line regulation)
PART B: Simulation experiments
1. RC integrating and differentiating circuits (Transient analysis with different
inputs and frequency response)
2. Clipping and clamping circuits (Transients and transfer characteristics)
3. RC coupled CE amplifier - frequency response characteristics
4. Cascade amplifier – gain and frequency response
5. RC Phaseshift oscillator

CLIPPING CIRCUITS

Aim:

To design, set up and study various clipping circuits using diode.

Components & equipments required

DIODE 1N4007

RESISTOR 3.3 K Ω

DC Source

Breadboard

Signal generator

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CRO

Theory
The property of a diode as a switching device is utilized in clipping circuits. Clipping circuits are
linear wave shaping circuits. They are useful to clips off the positive or negative portions of an input
waveform. It can also be used to slice off an input waveform between two voltage levels. Using a positive
clipper, a moderate quality square waveform can be generated from a sine wave. The diode clippers can be
classified as series and shunt clippers.

A resistance is used to limit the current flow through the diode. The value of the series resistance used
in the clipping circuit is given by the expression R = √ (Rf X Rr).

Where Rf = forward resistance of the diode

Rr = reverse resistance of the diode.

Positive clipper with clipping level at 0V: This circuit passes only negative going half waves of the input to
the output. All the positive half cycles are bypassed through the diode since the diode gets forward biased
when the input voltage becomes positive. Due to the voltage drop across the diode the clipping occurs exactly
at + 0.6 V.

Negative clipper with clipping level at 0V: This circuit passes only positive going half waves of the input to
the output. All the negative half cycles are bypassed through the diode since the diode gets forward biased
when the input voltage becomes negative.

Due to the voltage drop across the diode the clipping occurs exactly at - 0.6 V.

Positive clipper with clipping level at +3V: Till the input becomes greater than +3V, diode is reverse biased
and the input will appear at the output. When input exceeds +3V, diode becomes forward biased and dc source
voltage becomes appears at the output. Since the diode is in series with the dc source, the clipping level is at
+3.6V.

Negative clipper with clipping level at -3V: Till the input becomes less than -3V, diode is reverse biased and
the input will appear at the output. When input is less than -3V, diode becomes forward biased and dc source
voltage becomes appears at the output. Since the diode is in series with the dc source, the clipping level is at -
3.6V.

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Double clipper with clipping levels at +3V and -3V: This circuit is the merging of positive and negative
clippers. During the positive half cycle of the input, one branch will be effective and the other remains open.
Vice versa during the negative half cycle. Actual clipping levels are +3.6V and -3.6V due to the diode drops.

Two-level slicer with slicing levels at +3V and +5V: This circuit allows the signal pass to the output only
between +3V and +5V. During the negative half cycle of the input, diode D 1 conducts and diode D2 gets
reverse biased. Thus the output remains at +3V. During the positive half cycle of the input when input exceeds
+3V, D1 is reverse biased and input appears at the output. If the input exceeds +5V, D 2 conducts and output
remains at +5V. When the diode drop is considered, actual clipping occurs at +2.4V and +5.6V.

Procedure

1. Set up the circuit after testing the diodes. Set the S.G amplitude to 20Vp-p.
2. Connect signal generator output to the circuit & channel 1 of CRO.
3. Observe the output waveform on channel 2.
4. To observe the transfer characteristics set CRO in xy mode.

Result

Different clipping circuits are studied and observed the transfer characteristics.

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CLAMPING CIRCUITS

Aim:

To study different types of clamping circuit.

Components & Equipments Required

Diode 1N4007 - 1 nos

Capacitor 1f - 1 nos

DC Source, Breadboard, Signal generator and CRO

Theory

Clamping Circuits

At some situations it is necessary to add or subtract a dc voltage to a given waveform without

changing the shape of the waveform. Circuits used for the this purposed are called clamping circuits

A capacitor which is charged to a voltage and subsequently prevented from discharging can serve as

suitable replacement for a dc source. This principle is used in clamping circuits. The clamping level

can be made at any voltage level by biasing the diode. Such clamping circuit s are called biased

clamping circuits.

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Clamper clamping + vely at 0V

Suppose the input voltage is represented by the expression Vm Sint. During one -Ve half cycle of
the input sine wave, the diode conducts and the capacitor charges to Vm with +Ve polarity at right
side of the capacitor. During the +Ve half cycle of the input sine wave, the capacitor cannot
discharge since the diode does not conduct. Thus capacitor act as a dc source of Vm volts connected
in series with input signal source. The output voltage can be expressed as Vo=Vm+ Vm Sint.

Clamper clamping -vely at 0V

During one +Ve half cycle of the input sine wave, the diode conducts and the capacitor charges to

Vm with -Ve polarity at right side of the capacitor.During the -ve half cycle of the input sine wave,

the capacitor cannot discharge since the diode does not conduct. Thus capacitor act as a dc source of

Vm volts connected in series with input signal source. The output voltage can be expressed as Vo= -

Vm+ Vm Sint.

Clamping +vely at –3V

During one -Ve half cycle of the input sine wave, the capacitor charges through the dc source and

diode till (Vm-3) volts with +Ve polarity at right side. The charging of the capacitor is limited to

(Vm-3) volts due to the presence of dc source. The output voltage can be expressed as Vo=(Vm-3)+

Vm Sint.

Clamping -vely at +3V

During one +Ve half cycle of the input sine wave, the capacitor charges through the dc source and
diode till (Vm-3) volts with -Ve polarity at right side. The charging of the capacitor is limited to
(Vm-3) volts due to the presence of dc source. The output voltage can be expressed as Vo= -(Vm-3)
+ Vm Sint.

Clamping negatively at –3 V
During one + half cycle of the input sine wave, capacitor charges through the dc source and the diode
till Vm+3 volts with –Ve polarity of the capacitor at its right side. The charging of the capacitor is
extended up to vm +3 volts due to the presence of the dc source .The out put is then expressed as
Vo= -(Vm+3)+Vm Sint.
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Clamping positively at +3 V
During one - half cycle of the input sine wave, capacitor charges through the dc source and the diode

till Vm+3 volts with +Ve polarity of the capacitor at its right side. The charging of the capacitor is

extended up to Vm +3 volts due to the presence of the dc source .The out put is then expressed as

Vo= (Vm+3)+Vm Sint.

Procedure

1. Set up the circuit.

2. Apply 20V p-p input signal to clamping circuit.
3. Observe the output waveform on CRO.

Result

Studied different types of clamping circuits.

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RC COUPLED CE AMPLIFIER

AIM:

To design, set up and plot the frequency response of RC coupled common emitter amplifier.
To calculate its voltage gain, current gain, input and out impedances.

Components and equipments required.

TRANSISTOR BC 107

RESISTOR 10K, 2.2K, 2.7K, 47K, 560

4.7K pot.

CAPACITOR 10F, 22F

DMM, Signal generator, CRO, DC Source, Breadboard.

Theory
RC coupled CE amplifier is widely used in audio frequency applications in radio and TV receivers. It
provides current, voltage and power gains. Base current controls the collector current of a common emitter
amplifier. A small increase in base current results in a relatively large increase in collector current. Similarly a
small decrease in base current cause a large decrease in collector current. The emitter-base junction must be
forward biased and collector-base junction must be reverse biased for the proper functioning of amplifier.
Voltage divider bias is used in this amplifier.

The input impedance of the amplifier is given by the expression Zin = R1 || R2 || re and output
impedance is Zout = RC

Voltage gain = vo / vi

Current gain = Io / Ii = Vo/ Zo

Vi / Zi

Procedure
1. Set up the circuit
2. Check the dc conditions and apply a sinusoidal input signal of 10mV from the signal generator.
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3. Observe the output amplitude on CRO for different frequencies at the input.
4. Plot the frequency response and find Bandwidth.
5. To measure input impedance, connect 4.7K in series with the function generator and adjust the pot
until the output amplitude reduces to 50% of its no load voltage. Remove the pot from the circuit and
measure its resistance-using multimeter.
6. To measure output impedance connect 4.7K pot at the output of circuit. Adjust the pot until the
voltage across it is 50% of no load voltage. Remove the pot and measure its resistance.
7. Calculate the voltage gain and current gain.

Result
Plotted the frequency response of RC coupled CE amplifier and calculated its Bandwidth, voltage gain,
current gain, input and output impedances.

Design

Let the required Mid-band voltage gain of the amplifier = 100.

Selection of transistor - select transistor BC 107 since its minimum hFE is 100.

DC biasing conditions VCC = 12 V, IC = 2mA, VRC = 40% of VCC = 4.8 V,

VRE = 10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V.

Design of RC VRC = IC  RC = 4.8 V

From this we get RC = 2.4 K. Use 2.2 K std.

Design of RE VRE = IE  RE = 1.2 V

From this we get RE = 600. Use 680  std.

Design of voltage divider R1 and R2

From the data sheet of BC 107 its minimum hFE is 100.

IB = IC ∕ hFE = 2 mA ∕ 100 = 20 A.

Assume the current through R1 = 10 IB and current through R2 = 9IB to avoid loading of potential
divider by the base current.

VR2 = VBE + VRE

i.e., VR2 = 0.6 + 1.2 = 1.8 V. Also VR2 =9IBR2 = 1.8 V

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Then R2 = VR2 ∕ 9 IB = 10 K.

VR1 = VCC  VR2 = 12 V  1.8 V = 10.2 V

Also VR1 = 10 IB R1 = 10.2 V

Then R1 = VR1 ∕ 10 IB = 51 K. select 47 K std.

Design of RL

Gain of the is given by the expression AV = ( rC || re )

Rc=Rc//RL

Here re = 25mV ∕ IE = 25mV ∕ 2 mA = 12.5 

Substituting the values we get RL = 2.7K

Design of coupling capacitors CC1, CC2, CC3

XC1 at the lowest frequency (say 100 Hz), should be equal to one-tenth or less of the series impedance being
driven by the signal passing through the capacitor. Here the series impedance is Rin.

Then XC1  Rin ∕ 10. where Rin = R1 || R2 || hFE re

We get Rin = 1.1 K. Then XC1  110 .

So, CC1  1 ∕ 2fL  110 = 14 F. Select 15 F std.

Similarly XC2  Rout ∕ 10. where Rout = RC

Then XC2 =  240 .

So, CC2  1 ∕ 2fL  240 = 6.6 F. Select 10 F std.

Take CC2 = CC3 since the designs are same.

Design of bypass capacitor CE

To bypass the lowest frequency (100 Hz) XCE Should be equal to one tenth or less than the resistance RE

Then XC1  RE ∕ 10. CE  1 ∕( 2 x 100  68) = 23 F. Select 22 F std.

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Circuit diagram

RC PHASE SHIFT OSCILLATOR

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AIM

To design and set up a RC phase shift oscillator of 1KHz using single BJT and to observe the
waveform.

Components & Equipments required

Transistor BC 107

Resistors 47 K, 10 K, 2.2 K, 680 -1No 4.7 K -3Nos

Capacitors 0.01F -3Nos

1 F 22F – 1no

DC source, CRO, DMM, Breadboard

Theory

An oscillator is an electronic circuit for generating an ac signal voltage with a dc supply as the only
input requirement. The frequency of the generated signal is decided by the circuit contents. An oscillator
requires an amplifier, a frequency selective network, and a positive feed back from the output to the input. The
Barkhausen criterion for the sustained oscillation is A=1 where A is the gain of the amplifier,  is the feed
back factor. The unity gain means signal is in phase. If a common emitter amplifier is used, with a resistive
collector load, there is a180 0 phase shift between the voltages at the base and the collector. Feed back network
between the collector and base must be introduced an additional 1800 phase shift at a particular frequency.

In figure shown, 3 sections of phase shift networks are used so that each section introduced
approximately 600 phase shift at a resonant frequency. By analysis, resonant frequency F can be expressed by
the equation,

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Design

DC biasing conditions : VCC = 12 V, IC = 2mA, VRC = 40% of VCC = 4.8 V,

VRE = 10% of VCC = 1.2 V and VCE = 50% of VCC = 6 V.

Design of RC : VRC = IC  RC = 4.8 V

From this we get RC = 2.4 K. Use 2.2 K std.

Design of RE : VRE = IE  RE = 1.2 V

From this we get RE = 600. Use 680  std.

Design of voltage divider R1 and R2

From the data sheet of BC 107 its minimum hFE is 100.

IB = IC ∕ hFE = 2 mA ∕ 100 = 20 A.

Assume the current through R1 = 10 IB and current through R2 = 9IB to avoid loading of potential
divider by the base current.

VR2 = VBE + VRE

i.e., VR2 = 0.6 + 1.2 = 1.8 V. Also VR2 = 9IBR2 = 1.8 V

Then R2 = VR2 ∕ 9 IB = 10 K.

VR1 = VCC  VR2 = 12 V  1.8 V = 10.2 V

Also VR1 = 10 IB R1 = 10.2 V

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Then R1 = VR1 ∕ 10 IB = 51 K. select 47 K std

Design of bypass capacitor CE

i.e, XCE  RE ∕ 10 Then CE  1 ∕ 2100  68 = 22 F.

Design of frequency selective network

= 1 KHz

Take R= 4.7 K to avoid loading of RC by the RC network. Then C= 0.01 F.

Procedure

1. Set up the amplifier part of the circuit.

2. Verify the working of amplifier.
3. Complete the circuit with feed back network.
4. Observe the output waveform in CRO.

Result

Amplitude & frequency of sine wave is…….V & ……….Hz respectively.

Circuit diagram
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CASCODE AMPLIFIER

Aim
To design, set up and to plot the frequency response of a cascade amplifier.

Component & Equipment required

Transistor BC 107 – 2nos

Resistors 22 K, 33 K, 12 K, 560 , 1.2 K, 330 

Capacitors 15 F – 3nos

22 F – 1no

DC source, CRO, Signal generator, DMM, Breadboard.

Theory

A cascode amplifier comprises of a common emitter and a common base amplifier stages in cascade.
In the circuit diagram shown in figure, transistor T1 is in CE configuration and T2 in CB configuration.
Principal advantage of this circuit is its low input capacitance which is a limiting factor of voltage gain at high
frequencies. Cascode amplifier is able to amplify higher frequencies than that are possible with CE amplifier
because no high frequency feedback occurs from the output back to input through the miller capacitance as it
occurs in transistor CE configuration. Cascode amplifier provides same voltage gain of CE amplifier but in
wide range of frequencies. The advantages of CE and CB stages are put together in cascode connection. The
transistor must be identical for good performance of cascade amplifier.

Design

Let the required Mid-band voltage gain of the amplifier AV = 20.

Select BC 107 as transistors T1 and T2

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DC bias conditions VCC = 12 V, IC = 2mA, VCE1 = VCE2 = 35% of VCC = 4.2 V,

VRC = 20% of VCC = 2.4 V, VRE = 10% of VCC = 1.2 V.

Design of RC VRC = IC  RC = 2.4 V

Then RC = 1.2 K.

Design of RE VRE = IE  RE = 1.2 V

From this we get RE = 600. Use 560  std.

Design of R1 and R2

From the circuit we can obtain VCC = VR1 + VCE2 + VBE1 + VRE

VR1 = 12 – 4.2 – 0.6 – 1.2 = 6 V

IB = IC ∕ hFE = 20 A. If 10IB is assumed flowing through R1,

we get R1 = VR1 ∕ 10IB = 6 V ∕ (10  20 A) = 30 K. Use 33 K std.

Again, from the circuit we can obtain VCC = VR1 + VR2 + VBE2 + VRE

VR2 = VCC – VR1 – VBE2 – VRE

= 12 – 6 – 0.6 – 1.2 = 4.2 V

If 9IB flows through R2, 9IBR2 = 4.2 V.

Then R2 = 4.2 V ∕ (9  20 A) = 23.33 K. Use 22 K std.

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Design of R3 VR3 = VBE2 + VRE = 1.8 V

Similarly if remaining 8IB flows through R3, 8IBR3 = 1.8 V

Then R3 = 11.25 K. Use 12 K std.

Design of RL AV = gm(RC || RL). But gm = IC ∕ VT = 2 mA ∕ 26 mV.

Since the required gain AV is 20, we get RL = 330 .

Design of coupling capacitors CC1, CC2, C C3

The rule for the design of coupling capacitor is

XC1  Rin ∕ 10. Here Rin = R2 || R3 || hFERE

We get Rin = 1K. Then XC1  100 .

So, CC1  1 ∕ 2fL  100 = 15.9 F (assuming FL = 100 Hz).

Take CC1 = CC2 = CC3 = 15 F std.

Design of bypass capacitor CE

To bypass the lowest frequency (say 100 Hz), XCE should be equal to one-tenth or less of the
resistance RE.

i.e., XCE  RE ∕ 10.

Then CE  1 ∕ 2fL  60 = 26.54 F. Use 22 F std.

Procedure

1. Test all the components and verify the dc conditions.

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2. Apply a 100 mV sinusoidal signal from the signal generator to the circuit input. The amplitude of the
sinusoidal signal must be 100mV peak to peak. Observe the input and output waveforms on a dual
trace CRO screen.
3. Keeping the input amplitude constant, vary the frequency of the input signal from 0Hz to a few MHz
and note down corresponding output amplitude from CRO and enter it in the table.
4. Pot the frequency response characteristics on a graph sheet with gain along Y-axis and log(f) on X-
axis. Mark the frequencies log fL and log fH which are corresponding to -3dB of the maximum gain.
5. Calculate the bandwidth of the amplifier using the expression BW = f H - fL.

Result

Cascode amplifier is designed and plotted its frequency response.

Bandwidth = ……..Hz.

Circuit diagram

R1=33K,R2=22K,R3=12K,RE=560,CE=22F,RC=1.2K,CC1=CC2=CC3=15F

Q1=Q2=BC107 RL=330
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SERIES VOLTAGE REGULATOR WITH FEEDBACK

Aim

To design and set up a series voltage regulator with feed back and to plot line and load regulation.

Components & Equipments required

Zener diodes 5.1 V

Transistors SL 100

BC 107

Resistors 470Ω, 560Ω,

47KΩ, 68KΩ, 10K potentiometer

Rheostat 1200 Ω

Ammeter 0 – 100 mA

Variable DC source, DMM.

Theory

An ideal regulated power supply is an electronic circuit designed to provide a predetermined dc

voltage Vo which is independent of the load current drawn from Vo, of the temperature, and also of any
variations in the line voltage. In this circuit transistor T1 is the series pass element which functions as a
emitter follower and T2 functions as a voltage comparator and DC amplifier. Working of the circuit is as
follows.

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Suppose the load voltage increases due to an increase in the load current. Then the voltage fed back to
the base of T2 rises. Since the emitter potential is held constant by the zener diode, its base to emitter voltage
increases which results in an increase in the collector current of T2. For a constant I R3, the base current of
T1decreases which will cause an increased V CE of T1 thus reducing the load voltage to the regulated output
level. Similarly any decrease in the load voltage will cause a reduction in V CE of T1 and the output voltage is
maintained to the regulated level. Now if the input voltage increases beyond the designed value, the current in
R3 increases resulting in an increased voltage drop across R3 and the output voltage will be reduced to the
regulated level.

Design

Specification
SL 100

Max.Power dissipation-1000mW

hfe – 50 : VCE max = 50V

BC 107

Max. Power dissipation – 300mW

Hfe – 260; VCE max = 50V

Selection of feed back amplifier

Select a low current capacity, but with high hfe . Select BC 107.

Selection of pass transistor

For pass element select a high current carrying capacity transistor compared to BC 107
So select SL100.

Given data:- Vi = 12V , V0 = 10 V , I L = 50mA.

Selection of Zener
Since V0 = 10 V,select 5.1V zener( V2 = V0 / 2 = 5V)

Calculation of RZ

V R2 = V 0 - V2 = 10 - 5.1 = 4.9

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RZ = V RZ / I RZ current through zener diode = 10mA

R Z = 4.9 / 10mA = 490W select 470W standard value.

Design of RB

RB =V R3 / I R3

Now IRB = IC2 + IB1 = 2 I B1 (Assume I B1@ I C2)

But IB1 = IC1 / hfe1, where IC1 @ IE1 = IL + IZ

= 50 + 10mA = 60mA

Hence IB1 = 60 / 50 = 1.2mA

IRB = 2  IB1 = 2.4mA; RB = 1.3 / 2.4mA = 541.66W, Use 560W standard.

Design of R1 and R2.

VR2 = VZ + VBE2 = 5.1 + 0.7 = 5.8V

R2 = VR2 / IR2 = 5.8 / IR2

But IC2 = IB1 = 1.2 mA

I B2 = ( IC2 / hfe 2 ) = ( 1.2  10 – 3 ) / 260 = 4.62 mA

Now 20 IB2 = 20  4.62 mA = 92.4 mA

Hence R2 = 62.8 K, Use 68 K standard.

IR1 = IR2 + IB2 = 21 IB2 = 96.915 mA

R1 = VR1 / IR1 = (Vo –VR2) / IR1 = 43.32 K, Use 47 K standard.

Procedure

1. Set up the circuit and apply an input voltage of 12V

2. Adjust the load current to 50mA by adjusting the load rheostat. Adjust the pot 10K to get an
output voltage of 10 V (regulated output value). Check the dc conditions at this working
mode.
3. Keeping input voltage constant at 12 V, the load current is varied from 20 to 100mA.
Corresponding values of output voltage is noted. Plot of Vo vs IL gives the load regulation.
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4. The load current is held constant at 50mA and the input voltage is varied from 8V to 16V.
Note the corresponding output voltages. Plot of Vo vs Vi gives the line regulation.

Result

Series voltage regulator is designed and plotted its line and load regulation.

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CASCADE AMPLIFIER

AIM:

To Design and Construct a Cascade Amplifier and to determine its: a. DC Characteristics b. Maximum Signal
Handling Capacity c. Gain of the amplifier d. Bandwidth of the amplifier e. Gain -Bandwidth Product

DESIGN PROCEDURE:

Given specifications:
VCC= 14 V, IC1=1.2mA, RL = 40KΏ hFE= 100
(i) To calculate R5 :
Assume VE1 = 5V , VCE1 = VCE2 = 3V;
VB2 = VC1 = VE1 + VCE1 = 5V + 3V = 8V
VE2 = VB2 – VBE = 8V – 0.7V = 7.3V
VR5 = Vcc – VE2 – VCE2 = 14V – 7.3V – 3V = 3.7V
Choose R5 = RL / 10 = 40KΩ / 10 = 4KΩ ;
IC2 = ( VR5 / R5 ) = 3.7V / 3.9KΩ = 1000μA
(ii) To calculate R6 :
VR6 = VE2 / IC2 = 7.7KΩ;
IC2 = VE2 / R6 = 7.3V / 8.2 KΩ = 890μA
(iii) To calculate R1, R2 , R3 & R4:
Voltage across resistor R3 is given by
VR3 = Vcc – VC1 = 14V – 8V = 6V
R3 = VR3 / IC1 = 6V / 1mA = 6KΩ
R4 = VE1 / IC1 = 5V/ 1mA = 4.7KΩ
Voltage across resistor R2 is given by
VR2 = VE1 – VBE = 5V + 0.7V =5.7V
R2 = 10 R4 = 4.7 KΩ
VR1 = VCC – VB1 = 14V + 5.7V =8.3V
R1 = [ VR1 x R2 / VR2] = 68.4 KΩ
THEORY:
A cascade is type of multistage amplifier where two or more single stage amplifiers are connected
serially. Many times the primary requirement of the amplifier cannot be achieved with single stage
amplifier, because Of the limitation of the transistor parameters. In such situations more than one
amplifier stages are cascaded such that input and output stages provide impedance 51 | P a g e

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matching requirements with some amplification and remaining middle stages provide most of the
amplification. These types of amplifier circuits are employed in designing microphone and loudspeaker.
PROCEDURE:
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the amplifier using DC analysis.
3. Determine Maximum input voltage that can be applied to amplifier using AC analysis.
4. Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 0Hz to 1MHz in
incremental steps and note down the corresponding output voltage Vo for atleast 20 different values for
the considered range.
5. The voltage gain is calculated as Av = 20log (V0/Vi)
6. Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking
frequency on x-axis and gain in dB on y-axis.,
Bandwidth, BW = f2-f1 where f1 - lower cut-off frequency
f2 - upper cut-off frequency
a. DC ANALYSIS:
It is the procedure to find the operating region of transistor
Steps:
I) Set Vin = 0 by reducing the amplitude of the input signal from signal generator
II) Open circuit the capacitors since it blocks DC voltage
III) Set VCC= +10v and measure the voltage drop across the Resistor VRC, voltage across Collector-
Emitter Junction VCE and Voltage drop across base emitter junction. VBE
IV) Find the Q-point of the transistor and draw the DC load line.
To verify dc condition
1. VBE : (forward bias)
2. VRC = ____________
3. VCE = _______ (REVERSE BIAS)
4. Ic( Ic = (Vcc – VCE ) / Rc) =________
Q point analysis:
It is the procedure to choose the opearating point of transistor
Q-point: ( ICQ =_____ ; VCEQ =______ ) 52 | P a g e

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b. Maximum signal handling capacity:

It is the process to find the maximum input voltage that can be handled by the amplifier, so that it
amplifies the input signal without any distortion.
Procedure:
i. Apply input signal Vin = 20 mV of 1Khz frequency to the amplifier using the signal generator between
base emitter junction of the transistor. Find the sinusoidal output using CRO across RL.
ii. By increasing the amplitude of the input signal find maximum input voltage
V MSH across VBE at which the sinusoidal signal gets distorted during the process which can be seen in the
CRO. The amplitude obtained at this point is maximum voltage that can be applied to the transistor for
efficient operating of transistor.
V MSH = _________ volts
TABULATION

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CLASS AB POWER AMPLIFIER

Aim
To design and set up a complementary symmetry class-AB push-pull audio power amplifier.

Components & equipment required

TRANSISTOR SK 100, SL 100

RESISTOR 180 -2nos, 47, 2W -2nos

DIODE 1N 4007 –2nos

CAPACITOR 10F – 3nos

DMM, Signal generator, CRO, Decade Resistance Box, DC Source, Breadboard

Theory

A complementary symmetry circuit uses two transistors NPN and PNP with identical
characteristics. Both the transistors are connected as emitter follower with emitters connected
together. In order to minimize cross over distortion in class-B power amplifiers, the transistors must
operate in class AB mode. When the collector current flows for more than one half cycle of the input
signal, then the amplifier is class AB. In class AB mode a slight base bias is applied so that, a small
standby current flows at zero excitation. Class AB operation results in low distortion, but efficiency
reduce due to wastage of standby power.

Design

Dc biasing conditions
Vcc = 9V VCE1 = VCE2 = 4.5V

Selection of transistors
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Select SK 100 as Q1 and SL100 as Q2 as the matched pair transistors.

Specifications: IC = 100mA, hFE min. = 40

Selection of diodes
Select diodes 1N 4007 since diodes and transistors should be made of same material (silicon).
Design of RC
RC = ( Vcc – VCE )  IC = 4.5  100mA = 45. Use 47 , 2W std.
Design of RB
IB = IC  hFE = 100  40 = 2.5mA
Assume IRB = 10IB in order to avoid the loading of biasing networks by base currents.
Vcc = 2VR + 2VD
9 = 2VR + 1.4
VR = 3.8V
R = VR  10IB = 152 , use 180  std.

Selection of coupling capacitors

Since the frequency of operation is in audio range take C = 10 F.

Procedure

1. Set up circuit.
2. Apply 3Vpp at the input and observe output voltage on CRO for different values of load
resistance. (1 - 12)
3. Plot load impedance versus output power. Note the impedance for which output power is
maximum. This is the value of optimum load.

Result

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Circuit diagram

R = 180, Rc = 47, Q1 = SK 100, Q2 = SL 100,

D1 = D2 = 1N 4007, Cc1 = Cc2 = Cc3 = 10F

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RC INTEGRATOR AND DIFFERENTIATOR

AIM

1. To design and set up a RC integrator circuit, RC differentiator circuit and study the response to square
wave.
2. To observe the response of the designed circuits for the given square waveform for RC<<T,RC=T,
RC>>T.

COMPONENTS & EQUIPMENTS REQUIRED

Resistor 5.6KΩ - 1No:

Capacitor 2.2µF ,0.1µF, 0.22µF,1µF - 1 No:

Function Generator - 1 No:

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CRO - 1 No:

Bread board - 1 No:

Connecting Wires

THEORY

An RC integrator is constituted by a resistance in series and a capacitor parallel with the output. This
circuit produces an output voltage that is proportional to the integral of the input. Here the time constant is
very large in comparison with the time required for the input signal to change. Under this condition the
voltage drop across C will be very small in comparison with the drop across R. The current is V in/R since
almost all current appears across R. Output voltage across C is

τ
1
For RC>>τ,V O =V C = ∫ V ¿ dt
RC 0

Voltage drop across C increases as time increases.A square waveform has positive and negative
excursions with respect to its reference zero. If the input is square wave, capacitor charges and discharges
from negative voltage to the positive voltage and back.For the circuit to work as a good integrator θ=90 0 .As
tan θ=ωRC; tan90=infinity, which is practically impossible. Therefore a reasonable criterion for good
integration is θ=89.40 if θ=89.40, ωRC=95.480. So RC>16T will give the integrating practically.

An RC differentiator circuit is constituted with a capacitor connected in series and a resistor

connected in parallel to the output. The time constant RC of the circuit is very small in comparison with the
time period of the input signal. The voltage drop across R will be very small in comparison with the drop
dV ¿
across C. The current through the capacitor is C .Hence the output is proportional to the derivative of the
dt
input. Output voltage across R is

d V¿
For RC<<τ,V O =V R ≅ RC
dt

Differentiated output is proportional to the rate of change of input. When the input rises to maximum
value, differentiated output follows it because the sudden change of voltage is transferred to the output by the
capacitor. Since the rate of change of voltage is positive ,differentiated output is also positive. When input
remains maximum for a period of time, the rate of change of voltage is zero. So output falls to zero. During
this time, input acts like a dc voltage and capacitor offers high impedance to it. So the charges in capacitor
drains to earth through the resistance. When input falls to zero, rate of change of input voltage is negative.
Then the output also goes to negative.

For the circuit to work as a good differentiator θ=90 0 .As tan θ=1/ωRC; tan90=infinity. This result can
be obtained only if R=0 or C=0, which is practically impossible. Therefore a reasonable criterion for good

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1
differentiation is θ=89.40 if =100.So RC=0.0016T will give the differentiating practically. Assume
wRC
RC=0.01T for getting good spike waveforms. The peak of the output of the differentiator gets doubled when
the square wave is fed to the input.

CIRCUIT DIAGRAM

RC Integrator

RC Differentiator

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DESIGN

RC Integrator

Case 1: RC>>T

To avoid loading, select R=10 times the output impedance of signal generation. If output
impedance=600Ω, select R=6000Ω Use R=5.6KΩ

RC=10T

where R=5.6KΩ and T=1ms

then C=10T/R=1.78µF (2.2µF standard)

Case2:RC=T

RC=T

where R=5.6KΩ and T=1ms

then C=T/R=0.22µF (0.22µF standard)

Case3:RC<<T

RC=0.1T

where R=5.6KΩ and T=1ms

then C=0.1T/R=0.0178µF (0.01µF standard)

RC Differentiator

Case 1: RC<<T
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To avoid loading, select R=10 times the output impedance of signal generation.If output impedance=600Ω,
select R=6000Ω.,Use R=5.6KΩ.

RC=0.01T

where R=5.6KΩ and T=1ms

then C=0.01T/R=1.78nF (2.2nF standard)

Case2:RC=T

RC=T

where R=5.6KΩ and T=1ms

then C=T/R=0.22µF (0.22µF standard)

Case3:RC>>T

RC=5T

where R=5.6KΩ and T=1ms

then C=5T/R=0.89µF (1µF standard)

PROCEDURE

1. Set up the circuit as per the diagram of integrator.

2. Switch on the function generator and set a square wave of 2Vpp,1KHz.
3. Observe the input and output on the X and Y channels of CRO respectively.
4. Note down the output waveforms for the following conditions:
 RC<<T
 RC=T
 RC>>T (Integrator)
5. Repeat the same steps for differentiator.

OUTPUT WAVEFORMS

Integrator

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Differentiator

RESULT
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RC Integrator and differentiator circuits are designed and observed the waveforms for different time
constants.

VIVA QUESTIONS

1. Mention one application of the RC integrator.

2. What is the requirement of a low pass filter to act as integrator?
3. What is time constant of an RC circuit?
4. Mention one application of the RC differentiator.
5. What is the requirement of a high pass filter to act as differentiator?

RC INTEGRATOR
AIM

To design and construct RC integratorcircuit and study its pulse response.

EQUIPMENTS / COMPONENTS

Sl. no. Name and specification Quantity

1. Capacitor 22 µF 1 no.
2. Resistor 1 KΩ 1 no.
3. Function generator 0 to 1 MHz 1 no.
4. Oscilloscope 0 to 20 MHz 1 no.
5. Multimeter 1 no.
6. Breadboard 1 no.
7. Connecting wires

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THEORY

An RC integrator circuit is a wave shaping circuit. It constitutes a resistor in series and a

capacitor in parallel to the output. As the name suggests it does the mathematical operation
‘integration’ on the input signal. The time constant RC of the circuit is very large in comparison with
the time period of the input signal. Under this condition the voltage drop across C will be very small
in comparison with the voltage drop across R. For satisfactory integration it is necessary that RC ≥
16T, where T is time period of the input.

When pulse waveform is given at the input, capacitor charges through R and output voltage
builds up slowly. Capacitor continues to charge as long as input voltage is present. When input falls
to zero, capacitor discharges and output falls to zero slowly. As the value of RC >> T, the charging
current is almost constant and the output become linear. Hence a square pulse input provides a
triangular output.

PROCEDURE

1) Test the components

2) Assemble the circuit on a breadboard

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3) Connect the output of a function generator to the input of the differentiator circuit
4) Switch on the function generator and set the output at 5V, 1KHz pulse
5) Connect the output of the differentiator to an oscilloscope
6) Observe the output waveform and its amplitude for the following condition by varying the
time period (T) of the input

(i) RC >> T (f = 1 KHz) that is RC >> 16T

(ii) RC > T (f = 100 Hz)
(iii) RC < T (f = 10 Hz)
(iv) RC << T (f = 1 Hz)

7) Study the behavior of the circuit for different values of T

8) Plot all the input and output waveforms

CIRCUIT DIAGRAM

DESIGN

Let the input be a square pulse of 1 KHz

Then T = 1ms
For an integrator RC ≥ 16T
To avoid loading select R as 10 times the output impedance of the function generator
If it is 100 Ω, then R = 1KΩ
Substituting the value of R in the expression, RC = 16T, we get C = 16µF
Therefore C should be greater than 16µF. Hence choose C = 22µF

OBSERVATIONS

To observe the response of the circuit, you can change either the RC value of the circuit or T of
the input. Here T of the input is changed.

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SIMULATION –LT SPICE

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FAMILIARIZATION OF PSPICE SIMULATION SOFTWARE

Aim:
To familiarize with PSPICE simulation software environment.

Components&equipment
Computer with LTspice installed.
Theory:

LTspice is a fully-functional, freely-available circuit simulator. Linear Technology, Inc. originally

designed it so engineers could simulate their switching power supply controller integrated circuits. It is an
excellent SPICE simulator, rivaling costly commercial products like Electronic Workbench and PSpice. Some
important advantages to LTspice are that it is free, circuit sizes are unlimited, it is very easy to add new
models, and the user can easily modify the simulator’s behavior. However, PSpice and Electronic
Workbench have other advantages and are better at mixed analog/digital circuits than LTspice.

Procedure

Steps for circuit analysis

There are Four main steps involved in circuit simulation using PSpice.They are:

Step 1. Creating a New Project and Schematic Diagram.

Step 2. Selecting circuit components, connecting them together and setting component
Values, properties and saving the schematic diagram.

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Step 3. Creating a New Simulation Profile and setting up the simulation.

Step 4. Simulating the circuit and observing the simulation results.

To create a new LTSpice project

Step 1: Install LTspice and open the software (Click No if requested update). Current version: LTspice XVII

Current version: LTspiceXVII.

Step 2: Create a new schematic, or open an existing schematic file.

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Step 3: Add/Modify/Delete electrical components into the schematic

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• Shortcut keys and buttons; zoom in/out or rotate components if needed. Also available to view in
“Control Panel”.

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Step 4: Add components from the library, and place them at proper positions. • Components will be placed
where you left click the mouse, until you press “ESC” to stop placing that component.

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Step 5: Add wires (click and release) to connect all components; fulfill the circuit/schematic.

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Step 6: Right click on the components, and change their values.

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Step 7: “Run” the simulation. • Fill in the simulation duration (stop time) and precision (timestep).
Simulation command will be generated automatically. You can modify the command after you learn more
about LTspice or other SPICE.

Analyses

The type of simulation performed by LTSpice depends on the source specifications and control
statements.

LtSpice supports the following types of analyses:

• DC Analysis – It is used for circuits with time–invariant sources (e.g. steady-state DC

sources). It calculates all nodal voltages and branch currents over a range of values.
Supported types include Linear sweep, Logarithmic sweep, and Sweep over List of values.

a. Set up the dc operating point analysis and save results as follows.

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• On the menu at the top of the window, left click Simulate > Edit Simulation
Command.
• Left click the DC op pnt tab There are no parameters to specify, so left click OK.
A box will attach itself to the cursor.
• Move the cursor to an empty part of the schematic and left click.
• The dot command .op will appear. You can use the Move function to move the .op
command text somewhere else.
b. Run the .op simulation by clicking Simulate > Run (looks like a running person) on the
main menu.
 For MS Windows users, a window with the results will appear.
c. Open a new document in MS Word or a similar word processor, then copy and paste the
results in it as follows.
 Click on the window with the .op simulation results to make it active.
 MS Windows can copy the .op results window to the clipboard by pressing keys
Alt-PrtScr at the same time when that window is active.
d. Copy the schematic to the document as follows.
 Return to LTspice and copy the schematic to the document as follows.
 Close the .op results window.
 Right click on the schematic window and select View > Zoom to Fit . This will
expand the schematic to maximum size.
 On the menu, left click Tools > Copy bitmap to Clipboard.

• Transient Analysis – It is used for circuits with time variant sources (e.g., sinusoidal
sources/switched DC sources). It calculates all nodes voltages and branch currents over a
time interval and their instantaneous values are the outputs. You could use the battery
source for this since it is a fully- functional independent voltage source. However, you will
change it to the general voltage source you saw earlier.

A Change the voltage source.

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 Delete the battery source.

 Open the Select Component Symbol window as done earlier.

B. Adjust the source to be a 1 Vp-p, 1 kHz sine wave as follows.

 Right click on the source and the Voltage Source dialog box will appear.
 Left click Advanced and the Independent Voltage Source box will appear.
 Select SINE and then fill in the information as follows.
 DC offset: 0
 Amplitude: 1
 Freq (Hz): eg.1000
 Leave all others blank.
 Left click OK

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C. You will now set up the transient simulation to run for four sine wave cycles. A 100
smaximum timestep is specified to ensure a smooth curve. You do not always have to
specify a maximum timestep, but it is useful at times.
• Left click Simulate > Edit Simulation Command.
• Left click the Transient tab and enter the simulation parameters below.
• Stop Time: eg.4e-3
• Maximum Timestep:eg. 100u
• Left click OK.

 Place the .tran statement on the schematic. If the .op statement is still there,
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it will now have a semicolon in front, which comments it out and makes it
inoperative.
 .op when a .tran simulation is active. In this case, you may have to delete
existing simulation commands on the schematic and re-enter.
 You can manually add and remove semicolons and periods to select the one
simulation you want by editing each simulation command independently.
D. Run the simulation and examine the waveforms.
 Left click the menu Simulate > Run and a blank plot window will appear.
 Right click in the middle of the plot window and select Add Trace.
 Left click on the output node voltage and the input node voltage, then left
click OK. A plot with both waveforms will appear.
 Add a grid to the plot as follows
 Right click on an empty part of the plot window then select View and check
the box next to Grid.

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You can also select Plot Settings on the menu and check the Grid box.
 Before copying the plot to the clipboard for insertion in the document, it is
essential to remove the black background. Never use plots with black
backgrounds in documents.
 On the menu bar, left click Tools > Color Preferences.
 Left click the Waveform tab.
 In the Select Item box, choose Background.
 Move the three sliders all the way right so the numbers in the boxes are 255.
 Left click OK and you will return to the plot.
 The axes are grey and a better choice for a white background is black.
 Return to the Color Preferences box.
 Select Axis and move the sliders all the way to the left so the numbers in the
boxes are 0.
 Click Apply.
 Now select Grid and make it black.
 The trace colors that look good with a black background may not with a white
background, particularly light green. You will change this trace to the same
color as V[11] but you need to see what its color numbers are first.
 Select Trace V[11] and note the color numbers.
 Select Trace V[1] and change the color numbers to the ones you just found.
 Left click OK.
 The trace font size should be made larger than the default value.
 On the menu bar, left click Tools > Control Panel.
 Click on Reset to Default Values to see what those settings are.
 Under Pen thickness[*] drop down menu, select 4.
 Change the Font to Arial with 20-point size and select Bold font.
 Left click OK.

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E. Adjust the plot axis scaling and copy it to the document.

 Adjust the time axis as follows.

 Move the mouse over the horizontal axis until it displays a small ruler.
 Right click and the Horizontal Axis dialog box appears.
 Replace 4 ms with 2 ms.
 Click OK.
 Copy the plot to the clipboard.
 On the menu, left click Tools > Copy bitmap to Clipboard.

 AC Analysis – It is used for small signal analysis of circuits with sources of varying
frequencies. It calculates the magnitudes and phase angles of all nodal voltages and branch

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currents over a range of frequencies.

a. Adjust the voltage source to be a 1 V ac source as follows.
 Right click on the source and the Voltage Source dialog box will appear.
 Left click Advanced and the Independent Voltage Source box will appear.
 In the Small signal AC analysis area, set the amplitude to 1.
 Leave the sine wave time domain configuration as is. It will not affect the ac
analysis simulation.
b. Now set up the ac analysis simulation to sweep from 100 Hz to 1 MHz
 On the menu, left click Simulate > Edit Simulation Command.
 Left click the AC Analysis tab and enter the simulation parameters below. A
decade frequency sweep uses logarithmic point spacing over each 10:1
frequency decade. By choosing 101 points per decade, the plot should be
smooth ad there is a point on each decade boundary and 100 frequencies in
between.
 Type of Sweep: Decade
 Number of points per decade: 101
 Start Frequency: 100
 Stop Frequency 1e6
 Left click OK and place the .ac command on the schematic
c. Run the simulation and examine the waveforms.
 Left click the Simulate button and a blank plot window will appear.
 Traces for the input and output may already be present. If so, delete the input
trace using the Delete tool.
 If no traces are present,
 Right click in the middle of the plot window and select Add Trace.
 Left click on the output node voltage then left click OK. Plots of the output
magnitude and phase will appear
 Because your input signal had 1 V amplitude, a plot of the output signal is the

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same as the gain, which is why 1 V was used.

 Place two cursors on the plot and measure the 3 dB cutoff frequency as follows.
 Right click on the trace name at the top of the plot and the Expression Editor will
appear.
 In the Attached Cursors box, select 1st& 2nd.
 Left click OK.
 On the plot menu, select Plot Settings > Notes and Annotations > Label Curs.
Pos.
 You can right click on the label text and change or delete it.
 You can also delete the label and arrow using the Delete tool.

d. Copy the plot and paste it in the document.

• Left click Tools > Copy bitmap to Clipboard (Mac Users: Use Screenshot)
• Paste the plot in the document.

The operating temperature of an analysis can be set to any desired value, and nodal parameters are
assumed to be measured at a nominal temperature, by default 27 °C. Minimum requirements to run a DC
sweep analysis

Circuit should contain one of the following:

• Voltage source with a DC specification (VDC, for example).

• Current source with a DC specification (IDC, for example).

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Result:

LTSPICE simulation software environment is familiarized.

CLIPPING CIRCUITS

Aim:

To verify and simulate the input and output waveforms of clipper circuits.
Equipment Required:
PC installed with LTSpice Software.

Procedure:

1. Create a new project and a new schematic page

2. Place necessary circuit components and source. Select the circuit ground

Interconnect the components using Wire tool.

3. Set up the required analysis in the Simulation settings window.

4. Under Analysis type, TransientSweep. Select General Settings

option. Set the Run to time and Maximum step size values. Then click “Apply” and “Ok”

to save the simulation profile.

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5. After the parameters are set you can start simulation by selecting Run option.

6. Input and Output Waveforms will be shown in the graph. Observe the Graph.

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CIRCUIT DIAGRAMS

Positive clipper

Negative clipper

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Positive clipper at +3v

Negative clipper at -3v

Double clipper circuit

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Slicer

Positive clipper at 0V
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Negative clipper

Positive clipper at +3v

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Negative clipper at -3v

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Double clipper circuit

Slicer

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CLAMPING CIRCUITS

Aim:

To verify and simulate the input and output waveforms of clamping circuits.
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Equipment Required:
PC installed with LTSpice Software.

Procedure:

1. Create a new project and a new schematic page

2. Place necessary circuit components and source. Select the circuit ground

Interconnect the components using Wire tool.

3. Set up the required analysis in the Simulation settings window.

4. Under Analysis type, TransientSweep. Select General Settings

option. Set the Run to time,Time to start saving data andMaximum step size values. Then click “Apply”
and “Ok”

to save the simulation profile.

5. After the parameters are set you can start simulation by selecting Run option.

6. Input and Output Waveforms will be shown in the graph. Observe the Graph.

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Positive clamper at 0v

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Negative clamper at 0v

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Positive clamper at -3v

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Negative clamper at +3v

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Positive clamper at +3v

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Negative clamper at -3v

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INTEGRATOR AND DIFFERENTIATOR

Aim:

To verify and simulate the input and output waveforms of integrator and differentiator
Equipment Required:
PC installed with LTSpice Software.

Procedure:

1. Create a new project and a new schematic page

2. Place necessary circuit components and source. Select the circuit ground

Interconnect the components using Wire tool.

3. Set up the required analysis in the Simulation settings window.

4. Under Analysis type, TransientSweep. Select General Settings

option. Set the Run to time,Time to start saving data and Maximum step size values. Then click “Apply”
and “Ok”

to save the simulation profile.

5. After the parameters are set you can start simulation by selecting Run option.

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6. Input and Output Waveforms will be shown in the graph. Observe the Graph.

differentiator

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Integrator

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Observations

V(vout) V(vin)
5V

4V

3V

2V

1V

0V

-1V

-2V

-3V

-4V

-5V
0.0ms 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

Integrator output

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V(vin) V(vout)
5V

4V

3V

2V

1V

0V

-1V

-2V

-3V

-4V

-5V
0.0ms 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms 3.5ms 4.0ms 4.5ms 5.0ms

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RC COUPLED AMPLIFIER

Aim:

To obtain frequency response of RC Coupled Amplifier

Equipment Required:
PC installed with LTSPICE Simulation Software.

Procedure:

1. Create a new project and a new schematic page

2. Place necessary circuit components and sources. Select the circuit ground. Interconnect
the components using Wire tool.
3. Set up the required analysis in the Simulation settings window.
4. Under Analysis type, select AC analysis. Enter necessary parameter values (start,end
and increment values for Logarithmic sweep type). Then click “ok” to save the
simulation profile.

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RC coupled amplifier

Frequency respone

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RC PHASE SHIFT OSCILLATOR

Aim:

To obtain frequency response of RC Phase shift oscillator

Equipment Required:
PC installed with LTSPICE Simulation Software.

Procedure:

1. Create a new project and a new schematic page

2. Place necessary circuit components and source. Select the circuit ground

Interconnect the components using Wire tool.

3. Set up the required analysis in the Simulation settings window.

4. Under Analysis type, TransientSweep. Select General Settings

option. Set the Run to time,Time to start saving data and Maximum step size values. Then click “Apply”
and “Ok”

to save the simulation profile.

5. After the parameters are set you can start simulation by selecting Run option.

6. Output Waveformwill be shown in the graph. Observe the Graph.

Rc Phase shift oscillator

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Dept of Electronics& communication Engg Al -Ameen Engg.College