Embedded Systems
Lecture #11
• Agenda
1. Counters, continued
Page 1
Counters
• Ring Counters in VHDL
- to mimic the shift register behavior, we need access to the signal value before and after clock'event
- consider the following concurrent signal assignments:
architecture ….
begin
Q0 <= Q3;
Q1 <= Q0;
Q2 <= Q1;
Q3 <= Q2;
end architecture…
- since they are executed concurrently, it is equivalent to Q0=Q1=Q2=Q3, or a simple wire…
NOT THIS
Page 2
Counters
• Ring Counters in VHDL
- since a process doesn't assign the signal values until it suspends, we can use this to model the
"before and after" behavior of a clock event.
process (Clock, Reset)
begin
if (Reset = ‘1') then
Q0<='1'; Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process
- notice that the signals DO NOT appear in the sensitivity list. If they did the process would
continually execute and not be synthesized as a flip-flop structure
Page 3
Counters
• Johnson Counters in VHDL
process (Clock, Reset)
begin
if (Reset = ‘1') then
Q0<='0'; Q1<='0'; Q2<='0'; Q3<='0';
elsif (Clock'event and Clock='1') then
Q0<=not Q3; Q1<=Q0; Q2<=Q1; Q3<=Q2;
end if;
end process
Page 4
Counters
• Ripple Counters in VHDL, are nothing but FSM
• But can be designed implicitly
- strong type casting in VHDL can make modeling counters difficult (at first glance)
- the reason for this is that the STANDARD and STD_LOGIC Packages do not define
"+", "-", or inequality operators for BIT_VECTOR or STD_LOGIC_VECTOR types
Page 5
Counters
• Counters in VHDL using STD_LOGIC_UNSIGNED
use IEEE.STD_LOGIC_ARITH.ALL; -- call the package
entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
Page 6
Counters
• Counters in VHDL using STD_LOGIC_UNSIGNED
architecture counter_arch of counter is
signal count_temp : unsigned (3 downto 0); -- Notice internal signal
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= "0000";
elsif (Clock='1' and Clock'event) then
if (Direction='0') then
count_temp <= count_temp + '1'; -- count_temp can be used on both LHS and RHS
else
count_temp <= count_temp - '1';
end if;
end if;
end process;
Count_Out <= std_logic_vector(count_temp); -- assign to Port after the process
end counter_arch;
Page 7
Counters
• Counters in VHDL using STD_LOGIC_ARITH
use IEEE.STD_LOGIC_ARITH.ALL; -- call the package
entity counter is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Direction : in STD_LOGIC;
Count_Out : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
Page 8
Counters
• Counters in VHDL using STD_LOGIC_ARITH
architecture counter_arch of counter is
signal count_temp : integer range 0 to 15; -- Notice internal integer specified with Range
begin
process (Clock, Reset)
begin
if (Reset = '0') then
count_temp <= 0; -- integer assignment doesn't requires quotes
elsif (Clock='1' and Clock'event) then
if (count_temp = 15) then
count_temp <= 0; -- we manually check for limits
else
count_temp <= count_temp + 1;
end if;
end if;
end process;
Count_Out <= conv_std_logic_vector (count_temp, 4); -- convert integer into a 4-bit STD_LOGIC_VECTOR
end counter_arch;
Page 9
