Designing with VHDL

(control questions)

© V. Angelov VHDL Vorlesung SS2009 1

 Simple concurrent
assignments
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

entity a2of3 is
port (a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
y : out std_logic);
end a2of3;
architecture a1 of a2of3 is architecture a2 of a2of3 is
signal g0, g1, g2 : std_logic; signal g0, g1, g2 : std_logic;

begin begin
g0 <= a0 and a1; g2 <= a2 and a0;
g1 <= a1 and a2; y <= g0 or (g1 or g2);
g2 <= a2 and a0; g1 <= a1 and a2;
y <= g0 or g1 or g2; g0 <= a0 and a1;
end; end;

The two architectures are 1) equivalent; 2) different

© V. Angelov VHDL Vorlesung SS2009 2

 Port-signal mapping

carr: a2of3
port map(
... => ...,
... => ...,
... => ...,
... => ...);
port signal
1) =>
name name
signal port
2) => Which one is correct?
name name

© V. Angelov VHDL Vorlesung SS2009 3

 Instantiation of sub-blocks
-- component declaration
component a2of3 is
port (a0 : in std_logic;
a1 : in std_logic;
a2 : in std_logic;
y : out std_logic);
end component;

a) b) c)
...
carr: a2of3 ...
...
port map( carr: a2of3
carr: a2of3
a0 => a, port map(a, cin, b, cout);
port map(a, b, cin, cout);
a1 => b, ...
...
a2 => cin,
y => cout);
...

The three instantiations are 1) equivalent; 2) all different;

3) one (which?) differs from the others

© V. Angelov VHDL Vorlesung SS2009 4

 Multiple drivers
...
(A, B, C : in std_logic;
Y : out std_logic);
...
begin

Y <= not C;
Y <= A or B;

end;

This code is
1) OK, the first assignment will be just ignored;
2) not allowed;
3) allowed, but represents an inverter and an
or-gate with outputs shorted together

© V. Angelov VHDL Vorlesung SS2009 5

 Multiple drivers
...
begin
Y <= A when OE_A='1' else 'Z';
Y <= B when OE_B='1' else 'Z';
end;

This is allowed only when the signals are of the type

1) std_logic

2) std_ulogic

3) bit

© V. Angelov VHDL Vorlesung SS2009 6

 Ports and signals
port (
a : in std_logic;
b : in std_logic;
c : in std_logic;
ya : out std_logic;
yao : out std_logic);
…
begin
ya <= a and b;
yao <= ya or c;
...

1) This code is OK

2) A modification is necessary to get this code

compiled (what?)

© V. Angelov VHDL Vorlesung SS2009 7

 Data types
subtype reg_data is std_logic_vector(31 downto 0);
subtype reg_cmd is std_logic_vector( 0 downto 3);
subtype byte is std_logic_vector( 8 downto 1);
subtype fixedp is std_logic_vector( 7 downto -2);
type mem_array is array(0 to 63) of reg_data;
type dat_array is array(7 to 0) of reg_data;
type addr_data is std_logic_vector(15 downto 0);
type state_type is (idle, run, stop, finish);
type state_type is (idle, out, stop, finish);

Which declarations are not correct and why?

© V. Angelov VHDL Vorlesung SS2009 8

 Ranges
generic (N : Natural := 4);
port (
a : in std_logic_vector(0 to N-1);
c : out std_logic_vector(N-1 downto 0);
…
c <= a;

1) The code is not correct, as the indexes of the two

vectors have different directions
2) The code is correct, c(0) is connected to a(N-1)
3) The code is correct, c(0) is connected to a(0)

© V. Angelov VHDL Vorlesung SS2009 9

 Constants
constant Nbits : Integer := 8;
constant Nwords : Natural := 6;
constant LowIdx : Positive := 0;

constant all0 : std_logic_vector(Nbits-1 downto 0) = (others => '0');

constant Tco : real := 5 ns;

constant Tsetup : time := 2 ns;
constant Thold : integer := 1 ns;
constant Tdel : time := 3;

Which declarations are not correct and why?

© V. Angelov VHDL Vorlesung SS2009 10

 Concurrent assignments
y <= (a or b) and not c;
y <= a or b and not c;
y <= a and b or not c;
y <= a and b and not c;
y <= (a nor b) nor c;
y <= a nor b nor c;
y <= (a nand b) nand c;
y <= a nand b nand c;
y <= a xor b and c;
y <= (a xor b) and c;

Which assignments are not correct and why?

© V. Angelov VHDL Vorlesung SS2009 11

 Conditional and selected
assignments
y <= (a or b) when c ='0';

with a & b & c select

y <= '1' when "110"| "100"| "010",
'0' when "011"| "111";

with a & b & c select

y <= '1' when "110"| "100"| "010",
'0' when "011"| "110",
'-' when others;

Why these assignments are not correct?

© V. Angelov VHDL Vorlesung SS2009 12

 Generate
...
generic (N : Natural := 4);
port (
a : in std_logic_vector(N-1 downto 0);
g : in std_logic;
c : out std_logic_vector(N-1 downto 0) );
end for_gen;
architecture ... of for_gen is
The declaration of i is signal i : Integer;
necessary begin
? gn: for i in 0 to N-1 generate
i is automatically declared c(i) <= a(i) and g;
within the for…generate end generate;

loop
The range must be exactly the same
incl. the direction (downto) as in the
declaration of c() and a()
?
The index i of c(i) and a(i) must be within
the limits 0..N-1

© V. Angelov VHDL Vorlesung SS2009 13

 The integer type
How many bits will be used to store the following
integers:

signal my_int1 : Integer range -1 to 16;

5 6 4

signal my_int2 : Integer range -32 to 2;

6 8 7

© V. Angelov VHDL Vorlesung SS2009 14

 Mathematical operations with
integers
process
variable byte : Integer range 0 to 16#FF#;
variable sint : Integer range -128 to 127;
variable word : Integer range 0 to 16#FFFF#;
variable intg : Integer range -2**15 to 2**15-1;
begin

byte := 20; Which assignments are

byte := -20; not correct and why?
sint := -20;

sint := 150;

word := -1;

word := 1000**2;

word := 16#1000#;

© V. Angelov VHDL Vorlesung SS2009 15

 Adder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
This adder was designed for adding
USE IEEE.STD_LOGIC_UNSIGNED.all; two std_logic_vectors
entity adder is representing unsigned integers.
generic (N : Natural := 8);
port (
cin : in std_logic;
a : in std_logic_vector(N-1 downto 0); Can we use the
b : in std_logic_vector(N-1 downto 0);
cout: out std_logic;
generated hardware
y : out std_logic_vector(N-1 downto 0)); to add correctly a
end adder;
architecture behav of adder is and b if they
signal sum : std_logic_vector(N downto 0);
begin represent signed
sum <= cin + ('0' & a) + ('0' & b);
y <= sum(y'range);
integers?
cout <= sum(sum'high);
end;

© V. Angelov VHDL Vorlesung SS2009 16

 Signal vs. variable

signal si : Integer range -7 to 7;

begin Hint: the leftmost is the initial value
process
variable vi : Integer range -7 to 7;
begin si vi
si <= 0;
vi := 0;
si <= si + 1;
vi := vi + 1;
Which is the
wait for 10 ns;
si <= si + 1;
1 -6 1 -6 correct value of
vi := vi + 1; si and vi after
wait for 10 ns; -5 2 -5 2
si <= si + 1; the waits?
vi := si;
wait for 10 ns; -4 3 -5 -4 2 3
wait;
end process;

© V. Angelov VHDL Vorlesung SS2009 17

 DFF with asynchronous reset
process(clk, rst_n)
begin
Find the errors!
if rst_n = '0' then q <= '0'; end if;
if clk'event and clk='1' then
q <= d; process(clk)
end if; begin
end process; if rst_n = '0' then q <= '0';
elsif clk'event and clk='1' then
q <= d;
process(clk, rst_n) end if;
begin end process;
if rst_n = '0' then q := '0';
elsif clk'event and clk='1' then
q := d;
end if; process(clk, rst_n)
end process; begin
if rst_n = '0' then q <= '0';
elsif clk'event and clk then
q <= d;
end if;
end process;

© V. Angelov VHDL Vorlesung SS2009 18

 Decoder with enable
This entity is supposed to be a decoder with enable, but
has a bug (syntax & compile is OK)
…
port (
a : in std_logic_vector(1 downto 0);
e : in std_logic;
y : out std_logic_vector(2 downto 0));
…
process(a, e)
begin
if a = "00" then y <= "00" & e;
elsif a = "01" then y <= '0' & e & '0';
elsif a = "10" then y <= e & "00";
end if;
end process;

© V. Angelov VHDL Vorlesung SS2009 19

 DFFs with variables(1)

process(clk) q2
variable q1v, q2v : std_logic; clk C Q
q1
begin d D
FD
if rising_edge(clk) then

q1v := d; q2v := q1v;

?
q2v := q1v; q1v := d;

end if; q1

q1 <= q1v;
C Q q2
q2 <= q2v;
D
end process;
clk C Q FD
d D
FD

© V. Angelov VHDL Vorlesung SS2009 20

 DFFs with variables(2)
process(clk)
clk CLK variable qv : std_logic;
CLRN Q q
begin
Y D
VCC PRN if rising_edge(clk) then
DFF qv := a and b;
a IN1 Y
q <= qv;
b IN2
AND2 end if;
? end process;
?
signal qv : std_logic;
… clk CLK
CLRN Q q
process(clk) Y D
begin VCC CLK PRN

if rising_edge(clk) then CLRN Q DFF

a IN1 Y D
qv <= a and b;
b IN2 PRN
q <= qv; AND2 DFF
end if;
end process;

© V. Angelov VHDL Vorlesung SS2009 21

 State machines in VHDL
type state_type is (S0, SL, SR, SA); L L
signal present_st, next_st : state_type; R R LL LL
begin W W LR LR
process(present_st, L, R, W) clk clk
begin rst_n rst_n
next_st <= present_st; statem
case present_st is
when S0 => if W = '1' then next_st <= SA; LR <= '1'; LL <= '1';
elsif L = '1' then next_st <= SL; LL <= '1';
elsif R = '1' then next_st <= SR; LR <= '1';
end if;
when SL => if L = '0' and R = '1' then next_st <= SR; LR <= '1'; LL <= '0';
else next_st <= S0; LR <= '0'; LL <= '0';
end if;
when SR => if L = '1' then next_st <= SL; LL <= '1';
else next_st <= S0; LL <= '0'; LR <= '0';
end if;
when SA => next_st <= S0; LL <= '0'; LR <= '0';
end case; synthesis without
end process; errors!
process(clk, rst_n)
begin
if rst_n = '0' then present_st <= S0;
elsif clk'event and clk='1' then present_st <= next_st;
end if;
end process;
end;
What is wrong in this description?

© V. Angelov VHDL Vorlesung SS2009 22

 State machine - encoding
1. A state machine with 5 states, encoded
binary will have:
a) 8 states in total
b) 5 states in total
c) 32 states in total
2. The same state machine encoded one-hot
will have:
a) 5 states in total
b) 32 states in total
c) 8 states in total

© V. Angelov VHDL Vorlesung SS2009 23

 Synchronize input signals
D Q

CLK

D Q

CLK Which one of the two

schemes should be
avoided and why?
D Q

D Q CLK

CLK

D Q

CLK

© V. Angelov VHDL Vorlesung SS2009 24

 Simple test bench example
rst1
clk1
d1
rst2
clk2
d2

200 400 600 800 1 us

Find the waveform of each signal!

process
signal clk1 : std_logic := '1'; begin
signal rst1 : std_logic; rst2 <= '0';
signal d1 : std_logic; process d2 <= '0';
signal clk2 : std_logic; begin wait for 300 ns;
signal rst2 : std_logic; clk2 <= '0'; rst2 <= '1';
signal d2 : std_logic; wait for 50 ns; wait for 100 ns;
begin clk2 <= '1'; d2 <= '1';
clk1 <= not clk1 after 50 ns; wait for 50 ns; wait for 300 ns;
rst1 <= '0' after 0 ns, end process; rst2 <= '0';
'1' after 300 ns, wait for 200 ns;
'0' after 400 ns; d2 <= '0';
d1 <= '0' after 0 ns, wait;
'1' after 400 ns, end process;
'0' after 500 ns;
© V. Angelov VHDL Vorlesung SS2009 25
 Digital Filters(1)
x[n] x[n]
x3 x2 x1
x1 x2 x3

y[n] y[n]

1) FIR Are the two filters 1) FIR

2) IIR equivalent? 2) IIR

x[n] x[n]

plot the
response

y[n] y[n]

© V. Angelov VHDL Vorlesung SS2009 26

 Digital Filters(2)
x[n] What kind of filter is this one?

1 1 1) FIR
8 8 2) IIR

y[n]
6
8

x[n]

Sketch the response of the filter

y[n]

© V. Angelov VHDL Vorlesung SS2009 27

 I/O
• The unused unconnected input
pins should be VCC

– pulled high or low by internal

resistors

– left free in order to save power

– programmed as outputs driving '0'

© V. Angelov VHDL Vorlesung SS2009 28

 Timing(1)
• Positive setup time means D Q

– the D input must be stable some time

CK
before the rising edge of the clock
– the D input must be stable some time
after the rising edge of the clock D

• Positive hold time means CLK

– the D input must be stable some time

before the rising edge of the clock
– the D input must be stable some time
after the rising edge of the clock

© V. Angelov VHDL Vorlesung SS2009 29

 Timing(2)
• The operation of a chip at 1 Hz can be
affected by:
– setup time violations
– hold time violations
• The operation of a chip at 100 MHz can be
affected by:
– setup time violations
– hold time violations

© V. Angelov VHDL Vorlesung SS2009 30

 Special cores, I/O timing
• In order to multiply the input clock by 5/7
we can use a
– PLL
– DLL
• In order to achieve identical setup/hold
times on all bits of a synchronous 32-bit
input bus we must first use the D-flip-flops
– in the core logic cells
– in the I/O cells

© V. Angelov VHDL Vorlesung SS2009 31