Lecture 3

VHDL Data Types and Operators

 Translation of VHDL code to circuit
 Code structure

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 Translation of VHDL code to circuit
◦ What main example did we use?
 Code structure
◦ What are 3 important sections of VHDL code
structure?
◦ In the section that you implement the behavior, is
the default flow sequential or concurrent?

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 Translation of VHDL code to circuit
◦ What main example did we use? D flip-flop
 Code structure
◦ What are 3 important sections of VHDL code
structure?
◦ Library, Entity, and Architecture
◦ In the section that you implement the behavior, is
the default flow sequential or concurrent?
Concurrent

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 VHDL Data types
 Operators and Attributes
 Generic

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 VHDL Data types
 Operators and Attributes
 Generic

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 Pre-defined
 User-defined
 Subtypes

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Data types Synthesizable values
BIT, BIT_VECTOR ‘0’, ‘1’
STD_LOGIC, STD_LOGIC_VECTOR ‘X’, ‘0’, ‘1’, ‘Z’ (resolved)
BOOLEAN True, False
INTEGER From -2,147,483,647 to
+2,147,483,647
SIGNED From -2,147,483,647 to
-2,147,483,647 (binary rep).
UNSIGNED From 0 to +2,147,483,647
(binary rep).
User-defined integer type Subset of INTEGER
User-defined enumerated type Collection enumerated by user
SUBTYPE Subset of any type ( pre- or user-
defined)

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Data types Synthesizable values
BIT, BIT_VECTOR ‘0’, ‘1’
STD_LOGIC, STD_LOGIC_VECTOR ‘X’, ‘0’, ‘1’, ‘Z’ (resolved)
BOOLEAN True, False
INTEGER From -2,147,483,647 to Pre-
+2,147,483,647 defined
SIGNED From -2,147,483,647 to
-2,147,483,647 (binary rep).
UNSIGNED From 0 to +2,147,483,647
(binary rep).
User-defined integer type Subset of INTEGER
User-defined enumerated type Collection enumerated by user
SUBTYPE Subset of any type ( pre- or user-
defined)

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 They are parts of packages/libraries
 Package standard of library std: Defines BIT,
BOOLEAN, and INTEGER data types
 Do you remember how you would include this
in your VHDL code?

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 They are parts of packages/libraries
 Package standard of library std: Defines BIT,
BOOLEAN, and INTEGER data types.
 Do you remember how you would include this
in your VHDL code?
 LIBRARY STD;
 USE STD.STANDARD.ALL;

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 They are parts of packages/libraries
 Package standard of library std: Defines BIT,
BOOLEAN, and INTEGER data types.
 Do you remember how you would include this
in your VHDL code?
 LIBRARY STD;
 USE STD.STANDARD.ALL;

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 Resolved Logic System

X 0 1 Z W L H -
X X X X X X X X X
0 X 0 X 0 0 0 0 X
1 X X 1 1 1 1 1 X
Z X 0 1 Z W L H X
W X 0 1 W W W W X
L X 0 1 L W L W X
H X 0 1 H W W H X
- X X X X X X X X

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SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
-- Assignments across data types are illegal.
a <= b(5); --
b(0) <= a; --
c <= d(5); --
d(0) <= c; --
a <= c; --
b <= d; --

e <= b; --
e <= d; --

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SIGNAL a: BIT;
SIGNAL b: BIT_VECTOR(7 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: INTEGER RANGE 0 TO 255;
-- Assignments across data types are illegal
a <= b(5); -- legal (same scalar type: BIT)
b(0) <= a; -- legal (same scalar type: BIT)
c <= d(5); -- legal (same scalar type: STD_LOGIC)
d(0) <= c; -- legal (same scalar type: STD_LOGIC)
a <= c; -- illegal (type mismatch: BIT x STD_LOGIC)
b <= d; -- illegal (type mismatch: BIT_VECTOR x
-- STD_LOGIC_VECTOR)
e <= b; -- illegal (type mismatch: INTEGER x BIT_VECTOR)
e <= d; -- illegal (type mismatch: INTEGER x
-- STD_LOGIC_VECTOR)
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 Pre-defined
 User-defined
 Subtypes

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 Integers – declare name and range

 Enumerated – declare name and values

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 Integers – Ex:
◦ TYPE my_integer IS RANGE -32 TO 32;
◦ -- A user-defined subset of integers.
◦ TYPE student_grade IS RANGE 0 TO 100;
◦ -- A user-defined subset of integers or naturals.

 Enumerated – EX:
◦ TYPE state IS (idle, forward, backward, stop);
◦ -- An enumerated data type, typical of finite state
machines.
◦ TYPE color IS (red, green, blue, white);
◦ -- Another enumerated data type.

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 Pre-defined
 User-defined
 Subtypes

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 Any type with the addition of a constraint
 Main reason for subtypes
◦ Operations between different types aren’t allowed
◦ Operations between type and subtype are allowed
 Examples:
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';
SIGNAL a: BIT;
SIGNAL b: STD_LOGIC;
SIGNAL c: my_logic;
...
b <= a; --
b <= c; --

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 Any type with the addition of a constraint
 Main reason for subtypes
◦ Operations between different types aren’t allowed
◦ Operations between type and subtype are allowed
 Examples:
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';
SIGNAL a: BIT;
SIGNAL b: STD_LOGIC;
SIGNAL c: my_logic;
...
b <= a; -- illegal (type mismatch: BIT versus STD_LOGIC)
b <= c; -- legal (same "base" type: STD_LOGIC)

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 VHDL Data types
 Operators and Attributes
 Generic

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 Some operators do different things in
different contexts

 EX: “<=“ is used as “less than or equal too”

◦ IF (a <= b) THEN …

 Ex: “<=“ is used as assignment

◦ a <= b;

 We will show you how to differentiate

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 Assignment
 Logical operators
 Arithmetic operators
 Comparison operators
 Attributes

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 Are used to assign values to signals,
variables, and constants
 Three assignment operators:
◦ <= Used to assign a value to a SIGNAL
◦ := Used to assign a value to a VARIABLE,
CONSTANT, or GENERIC. Used also for establishing
initial values.
◦ => Used to assign values to individual vector
elements or with OTHERS

 Let’s look at examples

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 Given signal/variable declarations:
◦ SIGNAL x : STD_LOGIC;
◦ VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); --
Leftmost bit is MSB
◦ SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is
-- MSB

◦ x <= '1';
◦ --
◦ y := "0000";
◦ --
◦ w <= "10000000";
◦ w <= (0 =>'1', OTHERS =>'0');
◦ --

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 Given signal/variable declarations:
◦ SIGNAL x : STD_LOGIC;
◦ VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); --
Leftmost bit is MSB
◦ SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is
-- MSB

◦ x <= '1';
◦ -- '1' is assigned to SIGNAL x using "<="
◦ y := "0000";
◦ -- "0000" is assigned to VARIABLE y using ":="
◦ w <= "10000000";
◦ w <= (0 =>'1', OTHERS =>'0');
◦ -- LSB is '1', the others are '0'

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 Assignment
 Logical operators
 Arithmetic operators
 Comparison operators
 Attributes

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 Same as boolean logic operators you may be
familiar with
◦ NOT, AND, OR,NAND, NOR, XOR, XNOR
 Main thing to keep in mind is that the NOT
operator has precedence over all other
operators
 Examples:
◦ y <= NOT a AND b; -- (a'.b)
◦ y <= NOT (a AND b); -- (a.b)’
◦ y <= a NAND b; -- (a.b)'

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 Assignment
 Logical operators
 Arithmetic operators
 Comparison operators
 Attributes

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 Arithmetic can be performed on INTEGER,
SIGNED, and UNSIGNED
 Also, if the std_logic_signed or the
std_logic_unsigned package of the ieee
library is used, then STD_LOGIC_VECTOR can
also be employed directly in addition and
subtraction operations

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 Again the operators are similar to what you
are used too
◦ + Addition
◦ - Subtraction
◦ * Multiplication
◦ / Division
◦ ** Exponentiation
◦ MOD Modulus
◦ REM Remainder
◦ ABS Absolute value

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 Assignment
 Logical operators
 Arithmetic operators
 Comparison operators
 Attributes

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 Used for making comparisons
 Similar to what you are used to
 Can be only used within IF and WAIT
statements
 = Equal,
 /= Not equal to,
 < Less than,
 > Greater than,
 <= Less than or equal to,
 >= Greater than or equal to

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 Code example

SIGNAL counter : INTEGER;

SIGNAL clock: INTEGER;

PROCESS (counter)
BEGIN
IF (counter <= 10) THEN --

clock <= 0; --

ELSIF (clock <= 20) THEN

clock <= 1; --

END IF;
END PROCESS;
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 Code example

-- Signals entity port definitions

SIGNAL counter : INTEGER; -- counts from 1 to 20 then resets
SIGNAL clock: INTEGER;

-- Excerpt of code
PROCESS (counter)
BEGIN
IF (counter <= 10) THEN --

clock <= 0; --

ELSIF (counter > 10) THEN

clock <= 1; --
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END IF;
END PROCESS;
 Code example

-- Signals entity port definitions

SIGNAL counter : INTEGER; -- counts from 1 to 20 then resets
SIGNAL clock: INTEGER;

-- Excerpt of code
PROCESS (counter)
BEGIN
IF (counter <= 10) THEN -- less than or
equal to
clock <= 0; -- assignment
ELSIF (counter > 10) THEN
clock <= 1; -- assignment
END IF;
END PROCESS;
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 Assignment
 Logical operators
 Arithmetic operators
 Comparison operators
 Attributes

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 Ways to specify certain parts of data:
 Synthesizable types:
◦ d’LOW: Returns lower array index
◦ d’HIGH: Returns upper array index
◦ d’LEFT: Returns leftmost array index
◦ d’RIGHT: Returns rightmost array index
◦ d’LENGTH: Returns vector size
◦ d’RANGE: Returns vector range
◦ d’REVERSE_RANGE: Returns vector range in reverse
order

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 If given:
◦ SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);

 Then:
◦ d'LOW=
◦ d'HIGH=
◦ d'LEFT=
◦ d'RIGHT=
◦ d'LENGTH=
◦ d'RANGE=
◦ d'REVERSE_RANGE=(0 to 7)

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 If given:
◦ SIGNAL d : STD_LOGIC_VECTOR (7 DOWNTO 0);

 Then:
◦ d'LOW=0 --lower array index
◦ d'HIGH=7 --high array index
◦ d'LEFT=7 --leftmost array index
◦ d'RIGHT=0 --rightmost array index
◦ d'LENGTH=8 --size
◦ d'RANGE=(7 downto 0)
◦ d'REVERSE_RANGE=(0 to 7)

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 Or if given:
◦ SIGNAL x: STD_LOGIC_VECTOR (0 TO 7);

 Then the LOOP statements below are

equivalent:
◦ FOR i IN RANGE (0 TO 7) LOOP ...
◦ FOR i IN x'RANGE LOOP ...
◦ FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ...
◦ FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ...

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 All signals also have attributes too
 For a SIGNAL s:
◦ s’EVENT: Returns true when an event occurs on s
◦ s’STABLE: Returns true if no event has occurred on s
◦ s’ACTIVE: Returns true if s = ‘1’
◦ s’QUIET <time>: Returns true if no event has
occurred during the time specified
◦ s’LAST_EVENT: Returns the time elapsed since last
event
◦ s’LAST_ACTIVE: Returns the time elapsed since last
s = ‘1’
◦ s’LAST_VALUE: Returns the value of s before the last
event.
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 VHDL Data types
 Operators and Attributes
 Generic

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  What if you want a parity detector?
 Parity detector: a circuit that provide
◦ output = ‘0’ when the number of ‘1’s in the input
vector is even
◦ output ‘1’ otherwise

input (1 downto 0) output

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 input (2 downto 0) output

 3 input parity detector

ENTITY parity_det IS
PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
output: OUT BIT);
END parity_det;

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 input (2 downto 0) output

 3 input parity detector

ENTITY parity_det IS
PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
output: OUT BIT);
END parity_det;
input (3 downto 0) output
 4 input parity detector
ENTITY parity_det IS
PORT ( input: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
output: OUT BIT);
END parity_det;

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 input (2 downto 0) output

 3 input parity detector

ENTITY parity_det IS
PORT ( input: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
output: OUT BIT);
END parity_det;
input (3 downto 0) output
 4 input parity detector
ENTITY parity_det IS
PORT ( input: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
output: OUT BIT);
END parity_det;
 Redundant much?

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 A way of specifying a generic parameter
 Different for different applications
 Example syntax:
◦ GENERIC (parameter_name : parameter_type :=
parameter_value);
 Generic parity detector
ENTITY parity_det IS
GENERIC (n : INTEGER := 8); -- 8 input
PORT ( input: IN STD_LOGIC_VECTOR (n DOWNTO 0);
output: OUT BIT);
END parity_det;

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 VHDL Data types
 Operators and Attributes
 Generic

 Next class
◦ Concurrent programming
◦ Sequential programming
◦ Signals and variables

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