 signal clock : bit;

 file f3 : int_file open write_mode is “test.out”;

VHDL Quick Card  alias enable : bit is addr(31);
 attribute delay : time;
 component n_input_nand is
Entity generic ( n : integer := 2 );
Entity e1 is port ( data : in bit_vector ( 1 to n );
Generic( n1: integer := 2; n2: integer :=22); result : out bit );
end component;
Port( dataA, dataB : in bit_vector(1 to n);
 function square ( i : integer ) return integer;
Result : out bit);
 for store : use configuration latch;
End e1;
--port definitions: in | out | inout | buffer
Attributes
Attribute Result type Result
Architecture -- type my_array is array ( 9 downto 0 ) of
Architecture a1 of e1 is any_type;
--Declarations -- variable an_array : my_array;
Begin  my_array’high any_type 9
--Statements and/or component instances  my_array‘left any_type 9
End a1;  my_array‘low any_type 0
 my_array‘right any_type 0
Operators  my_array‘ascending boolean false
 Logical operators: and, or, xor, nand, nor, xnor,  my_array‘length integer 10
not  my_array‘range integer 9 downto 0
 Relational operators: =, /=, <, <=, >, >=  my_array‘reverse_range integer 0 to 9
 Shift left/right logical operators: sll, srl -- type fourval is ( ‘0’, ‘1’, ‘Z’, ‘X’ );
 Shift left/right arithmetic operators: sla, sra  fourval‘leftof(‘0’) fourval error
 Rotate left/right logical operators: rol, ror  fourval‘leftof(‘1’) fourval ‘0’
 Arithmetic operators: + , - , * , /  fourval‘pos(‘Z’) integer 2
 Other operators : &, **, abs, rem, mod  fourval‘pred(‘1’) fourval ‘0’
 fourval‘rightof(‘1’) fourval ‘Z’
 fourval‘succ(‘Z’) fourval ‘X’
Predefined data types  fourval‘val(3) fourval ‘X’
 Bit : [‘0’, ‘1’]
-- signal sig : sigtype;
 Bit_vector : Array of bit
-- constant T : time := 10 ns;
 Boolean : [true, false]
 sig‘active boolean True if activity on sig
 Character : 7-bit ASCII
 sig‘delayed(T) sigtype Copy of sig delayed by T
 Integer : signed 32 bit, -(231-1) to (231-1)
sig‘driving_value sigtype Value of driver on
 Natural : integer >= 0
sig
 Positive : integer > 0
 sig‘event boolean True if event on sig
 Real : Floating point : -1e38 to +1e38
 sig‘last_active time Time since last activity
 String : Array of characters
 sig‘last_event time Time since last event
 Time : hr, min, sec, ms, us, ns, ps, fs
 sig‘last_value sigtype Value before last event
 sig‘quiet(T) boolean Activity ( now – T ) to now
User defined data types  sig‘stable(T) boolean Event ( now – T ) to now
 Type number is integer;  sig‘transactio bit Toggles on activity on sig
 Type voltage is range 0 to 5;
 Type fourval is (A,B,C,D); Concurrent Assignments
 Type instruction is record  Normal assignment.
Opcode : bit;  y_out <= a and b;
 bit_a <=’1’;
Operand : bit;
 Vector_c <= “011110”;
End record;  Conditional assignment (When - else)
 Subtype positive_value is integer range 0 to 1000;  MUX2 <= A when (sel=’1’) else B;
 Selected assignment (With - select)
With sel select MUX2 <=
Declarations
A when ‘1’, B when ‘0’, ‘Z’ when others;
 constant bus_width : integer := 32;
 variable read_flag : bit := 0; Concurrent Objects
-- only in processes and subprograms  P1 : process ( sensivity list ) -- label is optional
-- variable declarations
 begin Note: VHDL-2008 allows conditional and selected assignments
-- sequential statements in sequential statements.
end process;
Concurrent and sequential statements
 -- Component instantiation enable <= select after 1 ns;
--Ommit generic map if component has not assert (a = b) report “a is not equal to b” severity
generic U1_n_input_nand : n_input_nand note;
generic map ( n => 2 ) -- severity levels : note | warning | error | failure
port map ( data => my_data; result =>
my_res ); IEEE.STD_LOGIC_1164 package
 top_block : block  type std_ulogic is ( ‘U’, ‘X’, ‘0’, ‘1’, ‘W’, ‘L’, ‘H’ );
 type std_ulogic_vector is array ( natural range <> ) of
-- declaration
std_ulogic;
begin  function resolved ( s : std_ulogic_vector ) return std_ulogic;
-- concurrent statements  subtype std_logic is resolved std_ulogic;
end block;  type std_logic_vector is array ( natural range <> ) of
std_logic;
 label_A : for i in (1 to 3) generate  function to_bit (s : std_ulogic; xmap : bit := ‘0’) return bit;
label_B : nand2( a(i), b(i), c(i) );  function to_bitvector ( s : std_logic_vector; xmap : bit
--Parallel statements := ‘0’ ) return bitvector;
end generate;  function to_stdlogicvector ( b : bit_vector ) return
std_logic_vector;
 label_0 : if ( i < 4 ) generate  function rising_edge ( signal s : std_ulogic ) return boolean;
label_1 : nor2( a(i), b(i), c(i) );  function falling_edge ( signal s : std_ulogic ) return boolean;
--Parallel statements  function is_x ( s : std_logic_vector ) return boolean;
end generate;
IEEE.NUMERIC_STD package
type unsigned is array ( natural range <> ) of
Sequential statements
-- contained in processes and subprograms std_logic; type signed is array ( natural range <> )
 read_flag := 0; -- read_flag is a variable of std_logic; function shift_left ( arg : unsigned;
--Expression is evaluated and assigned immediately count : natural ) return unsigned;
-- Other functions: shift_right(), rotate_left(),
 if ( x < y ) then max := y;
-- rotate_right()
elsif ( x > y ) then
function rsize ( arg : signed; new_size : natural )
max := x1; -- optional
return signed;
else
max := x2; -- optional
end if; Package declarations
 package two_level is
 case a is -- type, signal, functions declarations
when ‘1’ | ‘0’ => d <= ‘1’; end two_level;
when ‘Z’ => d <= ‘0’;  package body two_level is
when others => d <= ‘X’; -- optional end -- subprogram definitions
case; end two_level;
 while ( x < y ) loop package DEMO_PACK is
next when ( x > 5 ); -- usage of next constant SOME_FLAG : bit_vector := "11111111";
x := x + 1; type STATE is (RESET,IDLE,ACKA);
end loop; component HALFADD
port(A,B : in bit;
 for i in ( 0 to 100 ) loop SUM,CARRY : out bit);
x := x + i; end component;
exit when ( x = 0 ); -- usage of exit end DEMO_PACK;
end loop;
 null; -- does nothing Library usage declarations
-- using the two_level package.
 wait on a,b; library work;
 wait for TDelay; -- TDelay is a time constant use work.two_level.all; -- all objects used
use work.two.level.vcc; -- only the “vcc” object used
 wait on sig1, sig2 until ( sig = ‘1’ ) for 30 ns;

 wait until ( clk’event and clk = ‘1’ );

Sistemes Electronics Digitals – 2024-25