College of EngineeringTrivandrum

Department of Electronics and Communication Engineering

222TEC060 MIXED SIGNAL CIRCUIT DESIGN

Switched Capacitor Circuits-Part 2
Dr. Resmi E.,
Assistant Professor in ECE
[email protected]
[email protected]
 SC Gain Circuits- Parallel RC

▪ SC circuits can be used for signal amplification

▪ General Gain circuit with two parallel RC:

▪ SC implementation:

▪ circuit amplifies 1/f noise as well as Opamp offset

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 SC Gain Circuits- Resettable Gain Circuit

▪ Resettable Gain Circuit

– Resets integrating capacitor C2 every clock cycle
▪ performs offset cancellation
▪ filters 1/f noise of Opamp
▪ However, requires a high slew-rate from Opamp

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 SC Gain Circuits- Resettable Gain Circuit
Here, the voltage across the
integrating capacitor, C2, is cleared on
each ϕ₂, while on ϕ₁ the input voltage
charges C1 and the charging current
flows across C2 at the same time. In
this way, the change in charge across
C2, ΔQC2, equals the change in
charge across C1, ΔQC1, and
therefore, at the end of ϕ₁, the output
voltage is related to the input voltage
by:

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 SC Gain Circuits- Resettable Gain Circuit

To see this offset cancellation, consider the

gain circuit during ϕ₂ (i.e., when it is being
reset) as shown in Fig. (a).

The effect of the input offset voltage is

being modelled as a voltage source, Voff,
which is placed in series with one of the
opamp inputs.

In this case, it is placed in series with the

positive input, which results in the analysis
being marginally simpler.

During ϕ₂, both the voltages across C₁ and C₂ are

equal to the opamp offset voltage, Voff.
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 SC Gain Circuits- Resettable Gain Circuit

Next, during ϕ₁ the circuit is configured as shown in

Fig. (b), and at the end of ϕ₁ the voltage across C₁ is
given by

Since Vc2(n-1/2) = -Voff

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SC Gain Circuits- Resettable Gain Circuit

Since one side of capacitor C₂ is connected to the

virtual ground of the op-amp, which is at Voff, the
output voltage is given by

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 SC Gain Circuits- Capacitive Reset
• Instead of resetting the op-amp output to zero every clock cycle (which is time- and power-
consuming), the circuit uses capacitors to reset internal nodes and cancel the offset voltage.
This allows the system to maintain its dynamic operation and eliminate slew problem.

• The basic idea of the gain circuit is to couple the opamp’s output to the inverting input during the
reset phase with a capacitor that has been previously charged to the output voltage.

• The property of this gain circuit is that the opamp’s output need only change by the opamp’s
offset voltage between clock phases.

• In addition, since the circuit is insensitive to the opamp’s input offset voltage, it also reduces the
effect of the opamp’s 1/f noise

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 SC Gain Circuits- Capacitive Reset

• The capacitive-reset gain circuit is shown in

Fig.
• Capacitor C₄ is an optional “deglitching”
capacitor used to provide continuous-time
feedback during the nonoverlap clock times
when all the switches are open.
• This deglitching technique works well and
should be used on almost all switched-
capacitor circuits that would otherwise have
no feedback connection at some instant of
time. This capacitor would normally be
small (around 0.5 pF or less).

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 SC Gain Circuits- Capacitive Reset

• This gain circuit can be either inverting or

noninverting depending on the clock phases of the
input stage.
• While the inverting circuit creates its output as a
delay-free version of the input, the output for the
noninverting case would be one-half clock cycle
behind the input signal.

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 SC Gain Circuits- Capacitive Reset
• Consider the inverting circuit during the reset phase of φ₂, as shown in Fig. (a).

• We have assumed capacitor C₃ was charged to the

output voltage during the previous φ₁ clock phase.
•
• Here we see that capacitors C₁ and C₂ are charged
to the opamp’s input-offset voltage, Voff, in the same
manner as in the resettable gain circuit

One side of each of C₁ and C₂ is now grounded.

Since C₁ and C₂ hold equal but opposite charges,
grounding one end of both capacitors cancels their
charges. As a result, no net charge is transferred to
C₃ during this phase.

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 SC Gain Circuits- Capacitive Reset
The next clock phase of φ₁ is shown in Fig.(b),

During ϕ₁, capacitor C₃ is charged to the output

voltage. The output voltage is

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 SC Gain Circuits- Differential Capacitive Reset

▪ Accepts differential inputs and partially cancels switch clock- feedthrough

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 SC Gain Circuits- Correlated Double Sampling (CDS) Techniques

▪ Preceding SC gain circuit is an example of CDS

– Minimizes errors due to Opamp offset and 1/f noise
▪ When CDS used, Opamps should have low thermal noise (often use n- channel input transistors)
▪ Often use CDS in only a few stages:
– input stage for oversampling converter
– some stages in a filter (where low-frequency gain is high)
▪ Basic approach:
– Calibration phase: store input offset voltage
– Operation phase: error subtracted from signal

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 High-Freq CDS Amplifier

▪ φ2 : C1‘, C2‘ used but include errors

▪ φ1 : C1‘, C2‘ used but here no offset errors
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 Sample and Hold Circuits

▪ S/H is used to sample an analog signal and to store its value for some length of time

▪ Also called “track-and-hold” circuits

– Often needed in A/D converters
– Conversion may require held signal
• reduces errors due to different delay times in A/D converter

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 Sample and Hold Circuits

▪ Performance parameter and errors in S/H:

▪ Sampling pedestal or Hold Step
– errors in going from track to hold: held voltage is different to sampled input
voltage
– should be minimized and signal independent for no distortion
▪ Signal feedthrough: should be small during hold
▪ Speed at which S/H can track input voltage
– limitations to bandwidth and slew-rate
▪ Droop rate: slow change in output voltage during hold mode
▪ Aperture (or sampling) jitter — effective sampling time changing every T
– difficult in high-speed designs
▪ Other errors: dynamic range, linearity, gain, and offset error

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 Sample and Hold Circuits- Basic Concept
▪ If φclk is high, V’ follows Vin
▪ If φclk is low, V’ will stay constant, keeping the value when went φclk low
▪ Basic circuit has some practical problems:
▪ Charge Injection of Q1
– Causes (negative) hold step
▪ Aperture Jitter
– Sampling time variation as a function of Vin

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Sample and Hold Circuits- Basic Concept

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Sample and Hold Circuits- Charge Injection
▪ When φclk goes low, Q1 turns off.
▪ However, Q1, being a MOSFET, still has channel charge stored
inside it.
▪ This stored charge has to redistribute when the switch turns off.
▪ If the clock transition is very fast, the redistribution is symmetric
— exactly half of the channel charge goes to each side.

▪ Channel charge:

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 Sample and Hold Circuits - Charge Injection

▪ ΔV‘ linearly related to Vin: gain error

▪ ΔV‘ also linearly related to Vtn, which is nonlinearly related to Vin: distortion error
(due to Body effect)
– Often gain error can be tolerated but not distortion
▪ Additional change in V’ due to the overlap capacitances
Here, Lov​ is the overlap length, and
VSS​ is the ground voltage (typically
0V).

▪ Causes DC offset effect

– Which is signal independent
– Usually smaller than charge injection component
– Can be important of Clk signal has power supply noise → can lead to poor power-
supply rejection ratio

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Sample and Hold Circuits

▪ Transmission gate: Charge of equally sized p and n

transistor cancel out
– Charge cancels only when Vin in middle between VDD and
VSS
– Finite slopes of clock edges make turn of times of p
and n transistor different and signal dependent

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 S/H With High Input Impedance

▪ When the clock φclk is high, the circuit responds similarly to an Opamp in
a unity-gain feedback configuration
▪ When goes low, Vin at that time is stored on Chld, similarly to a simple S/H
▪ DC offset of buffer is divided by the gain of input Opamp

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 S/H With High Input Impedance

▪ Disadvantages:
– in hold mode, the Opamp is open loop, resulting in its output saturating at
one of the power supply voltages
• Opamp must have fast slew rate to go from saturation to Vin in next
clk cycle
– Sample time, charge injection — input signal dependent
– Speed reduced due to overall feedback

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 S/H With Lower Slew Rate Requirement

Without a track-and-hold, the amplifier

must quickly respond to a fast-
changing input. It needs a very high
slew rate (volts/µs) to faithfully track
the input signal without distortion.

• Track-and-Hold stage isolates the fast-changing input from the output

amplifier, reducing how fast the amplifier must react - lower slew rate
requirement

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 S/H With Lower Slew Rate Requirement
Sampling Phase (ϕ_clk = High):
•Q1 closes , Q2 is open, and Q3 is closes.
•Vin is sampled and stored across the capacitor Chld.

Hold Phase (ϕ_clk = Low):

•Q1 opens (disconnects from Vin), Q2 closes, and Q3
open.
•Chld now holds the voltage that was sampled.
•Now, the output buffer drives the output independently.

• Since the buffer has high input impedance, the charge

on Chld remains almost constant, preserving the sampled
voltage.

• Since the output stage doesn't have to continuously track rapid input changes
anymore, the slew rate demand on it is significantly lower.

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S/H With Reduced offset (Single Ended)

▪ Charge injected by Q1 matched by Q2 into C’hld

– If fully differential design, matching occurs naturally
leading to lower offset.

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S/H With Reduced offset (Differential)

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BiCMOS S/H Circuits -1

▪ Inverting S/H
– When in track mode, Q1 is on and Q2 is off,
resulting in the S/H acting as an inverting
low-pass circuit with Ω-3dB = 1/(RC)
– When Q1 turns off, Vout will remain constant
▪ Needs Opamp capable of driving resistive loads
– Difficult to implement in CMOS
▪ Good high-speed BiCMOS configuration
▪ Q2 minimizes feedthrough

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BiCMOS S/H Circuits -2

▪ Opamp in unity gain follower mode during

sampling
▪ In hold mode input signal is stored across C1,
since Q1 is turned off
▪ Charge injection of transistors cancel
▪ Clock signals are signal dependent
▪ Good speed, moderate accuracy

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