Memory Management
Memory Management
Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne ©2009
Chapter 8: Memory Management
Background
Swapping
Contiguous Memory Allocation
Paging
Structure of the Page Table
Segmentation
Example: The Intel Pentium
Operating System Concepts – 8th Edition 8.2 Silberschatz, Galvin and Gagne ©2009
Objectives
To provide a detailed description of the Intel Pentium, which supports both pure segmentation and
segmentation with paging
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Background
Program must be brought (from disk) into memory and placed within a process for it to be run
Main memory and registers are only storage CPU can access directly
Memory unit only sees a stream of addresses + read requests, or address + data and write requests
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Base and Limit Registers
A pair of base and limit registers define the logical address space
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Hardware Address Protection with Base and Limit Registers
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Address Binding
Inconvenient to have first user process physical address always at 0000
How can it not be?
Further, addresses represented in different ways at different stages of a program’s life
Source code addresses usually symbolic
Compiled code addresses bind to relocatable addresses
i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
i.e. 74014
Each binding maps one address space to another
Operating System Concepts – 8th Edition 8.7 Silberschatz, Galvin and Gagne ©2009
Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three different stages
Compile time: If memory location known a priori, absolute code can be generated; must
recompile code if starting location changes
Load time: Must generate relocatable code if memory location is not known at compile time
Execution time: Binding delayed until run time if the process can be moved during its execution
from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers)
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Multistep Processing of a User Program
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Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate physical address space is central to
proper memory management
Logical address – generated by the CPU; also referred to as virtual address
Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-time address-binding schemes;
logical (virtual) and physical addresses differ in execution-time address-binding scheme
Logical address space is the set of all logical addresses generated by a program
Physical address space is the set of all physical addresses generated by a program
Operating System Concepts – 8th Edition 8.10 Silberschatz, Galvin and Gagne ©2009
Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical address
To start, consider simple scheme where the value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses; it never sees the real physical addresses
Execution-time binding occurs when reference is made to location in memory
Logical address bound to physical addresses
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Dynamic relocation using a
relocation register
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Dynamic Loading
Routine is not loaded until it is called
Useful when large amounts of code are needed to handle infrequently occurring cases
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Dynamic Linking
Static linking – system libraries and program code combined by the loader into the binary program image
Dynamic linking –linking postponed until execution time
Small piece of code, stub, used to locate the appropriate memory-resident library routine
Stub replaces itself with the address of the routine, and executes the routine
Operating system checks if routine is in processes’ memory address
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries
Consider applicability to patching system libraries
Versioning may be needed
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Swapping
A process can be swapped temporarily out of memory to a backing store, and then brought back
into memory for continued execution
Total physical memory space of processes can exceed physical memory
Backing store – fast disk large enough to accommodate copies of all memory images for all
users; must provide direct access to these memory images
Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority
process is swapped out so higher-priority process can be loaded and executed
Major part of swap time is transfer time; total transfer time is directly proportional to the amount
of memory swapped
System maintains a ready queue of ready-to-run processes which have memory images on disk
Does the swapped out process need to swap back in to same physical addresses?
Depends on address binding method
Plus consider pending I/O to / from process memory space
Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows)
Swapping normally disabled
Started if more than threshold amount of memory allocated
Disabled again once memory demand reduced below threshold
Operating System Concepts – 8th Edition 8.15 Silberschatz, Galvin and Gagne ©2009
Schematic View of Swapping
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Context Switch Time including Swapping
If next processes to be put on CPU is not in memory, need to swap out a process and swap in target
process
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of 50MB/sec
Plus disk latency of 8 ms
Swap out time of 2008 ms
Plus swap in of same sized process
Total context switch swapping component time of 4016ms (> 4 seconds)
Can reduce if reduce size of memory swapped – by knowing how much memory really being used
System calls to inform OS of memory use via request memory and release memory
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Contiguous Allocation
Main memory usually into two partitions:
Resident operating system, usually held in low memory with interrupt vector
User processes then held in high memory
Each process contained in single contiguous section of memory
Relocation registers used to protect user processes from each other, and from changing operating-system
code and data
Base register contains value of smallest physical address
Limit register contains range of logical addresses – each logical address must be less than the limit
register
MMU maps logical address dynamically
Can then allow actions such as kernel code being transient and kernel changing size
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Hardware Support for Relocation
and Limit Registers
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Contiguous Allocation (Cont.)
Multiple-partition allocation
Degree of multiprogramming limited by number of partitions
Hole – block of available memory; holes of various size are scattered throughout memory
When a process arrives, it is allocated memory from a hole large enough to accommodate it
Process exiting frees its partition, adjacent free partitions combined
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
OS OS OS OS
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Dynamic Storage-Allocation Problem
Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size
Produces the smallest leftover hole
Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole
First-fit and best-fit better than worst-fit in terms of speed and storage utilization
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Fragmentation
External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous
Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size
difference is memory internal to a partition, but not being used
First fit analysis reveals that given N blocks allocated, 0.5 N blocks lost to fragmentation
1/3 may be unusable -> 50-percent rule
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Fragmentation (Cont.)
Reduce external fragmentation by compaction
Shuffle memory contents to place all free memory together in one large block
Compaction is possible only if relocation is dynamic, and is done at execution time
I/O problem
Latch job in memory while it is involved in I/O
Do I/O only into OS buffers
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Paging
Physical address space of a process can be noncontiguous; process is allocated physical memory
whenever the latter is available
To run a program of size N pages, need to find N free frames and load program
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Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in
physical memory
Page offset (d) – combined with base address to define the physical memory address that is sent to
the memory unit
p d
m-n n
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Paging Hardware
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Paging Model of Logical and Physical Memory
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Paging Example
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Paging (Cont.)
Calculating internal fragmentation
Page size = 2,048 bytes
Process size = 72,766 bytes
35 pages + 1,086 bytes
Internal fragmentation of 2,048 - 1,086 = 962 bytes
Worst case fragmentation = 1 frame – 1 byte
On average fragmentation = 1 / 2 frame size
So small frame sizes desirable?
But each page table entry takes memory to track
Page sizes growing over time
Solaris supports two page sizes – 8 KB and 4 MB
Process view and physical memory now very different
By implementation process can only access its own memory
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Free Frames
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Implementation of Page Table
Page table is kept in main memory
The two memory access problem can be solved by the use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers (TLBs)
Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process
to provide address-space protection for that process
Otherwise need to flush at every context switch
On a TLB miss, value is loaded into the TLB for faster access next time
Replacement policies must be considered
Some entries can be wired down for permanent fast access
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Associative Memory
Associative memory – parallel search
Page # Frame #
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Paging Hardware With TLB
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Effective Access Time
Associative Lookup = time unit
Can be < 10% of memory access time
Hit ratio =
Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to
number of associative registers
Consider = 80%, = 20ns for TLB search, 100ns for memory access
Consider = 80%, = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 120 + 0.20 x 220 = 140ns
Consider slower memory but better hit ratio -> = 98%, = 20ns for TLB search, 140ns for memory
access
EAT = 0.98 x 160 + 0.02 x 300 = 162.8ns
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Memory Protection
Memory protection implemented by associating protection bit with each frame to indicate if read-only or
read-write access is allowed
Can also add more bits to indicate page execute-only, and so on
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Valid (v) or Invalid (i)
Bit In A Page Table
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Shared Pages
Shared code
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window
systems)
Similar to multiple threads sharing the same process space
Also useful for interprocess communication if sharing of read-write pages is allowed
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Shared Pages Example
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Structure of the Page Table
Memory structures for paging can get huge using straight-forward methods
Consider a 32-bit logical address space as on modern computers
Page size of 4 KB (212)
Page table would have 1 million entries (232 / 212)
If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone
That amount of memory used to cost a lot
Don’t want to allocate that contiguously in main memory
Hierarchical Paging
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Hierarchical Page Tables
Break up the logical address space into multiple page tables
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Two-Level Page-Table Scheme
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Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is divided into:
a page number consisting of 22 bits
a page offset consisting of 10 bits
Since the page table is paged, the page number is further divided into:
a 12-bit page number
a 10-bit page offset
p1 p2 d
12 10 10
where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page
table
Known as forward-mapped page table
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Address-Translation Scheme
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64-bit Logical Address Space
Even two-level paging scheme not sufficient
If page size is 4 KB (212)
Then page table has 252 entries
If two level scheme, inner page tables could be 210 4-byte entries
Address would look like
p1 p2 d
42 10 12
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Three-level Paging Scheme
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Hashed Page Tables
Common in address spaces > 32 bits
Each element contains (1) the virtual page number (2) the value of the mapped page frame (3) a pointer to
the next element
Virtual page numbers are compared in this chain searching for a match
If a match is found, the corresponding physical frame is extracted
Operating System Concepts – 8th Edition 8.46 Silberschatz, Galvin and Gagne ©2009
Hashed Page Table
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Inverted Page Table
Rather than each process having a page table and keeping track of all possible logical pages, track all
physical pages
Entry consists of the virtual address of the page stored in that real memory location, with information
about the process that owns that page
Decreases memory needed to store each page table, but increases time needed to search the table
when a page reference occurs
Use hash table to limit the search to one — or at most a few — page-table entries
TLB can accelerate access
Operating System Concepts – 8th Edition 8.48 Silberschatz, Galvin and Gagne ©2009
Inverted Page Table Architecture
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Segmentation
Memory-management scheme that supports user view of memory
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User’s View of a Program
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Logical View of Segmentation
1
4
1
3 2
4
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Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps two-dimensional physical addresses; each table entry has:
base – contains the starting physical address where the segments reside in memory
limit – specifies the length of the segment
Segment-table base register (STBR) points to the segment table’s location in memory
Operating System Concepts – 8th Edition 8.53 Silberschatz, Galvin and Gagne ©2009
Segmentation Architecture (Cont.)
Protection
With each entry in segment table associate:
validation bit = 0 illegal segment
read/write/execute privileges
Protection bits associated with segments; code sharing occurs at segment level
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Segmentation Hardware
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Example of Segmentation
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Example: The Intel Pentium
Supports both segmentation and segmentation with paging
Each segment can be 4 GB
Up to 16 K segments per process
Divided into two partitions
First partition of up to 8 K segments are private to process (kept in local descriptor table LDT)
Second partition of up to 8K segments shared among all processes (kept in global descriptor
table GDT)
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Logical to Physical Address
Translation in Pentium
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Intel Pentium Segmentation
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Pentium Paging Architecture
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Linear Address in Linux
Linux uses only 6 segments (kernel code, kernel data, user code, user data,
task-state segment (TSS), default LDT segment)
Linux only uses two of four possible modes – kernel and user
Uses a three-level paging strategy that works well for 32-bit and 64-bit systems
Linear address broken into four parts:
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Three-level Paging in Linux
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End of Chapter 7
Operating System Concepts – 8th Edition Silberschatz, Galvin and Gagne ©2009
Chapter 9: Virtual Memory
Operating System Concepts Essentials – 8th Edition Silberschatz, Galvin and Gagne ©2011
Chapter 9: Virtual Memory
Background
Demand Paging
Copy-on-Write
Page Replacement
Allocation of Frames
Thrashing
Memory-Mapped Files
Allocating Kernel Memory
Other Considerations
Operating-System Examples
Operating System Concepts Essentials – 8 th Edition 9.2 Silberschatz, Galvin and Gagne ©2011
Objectives
To describe the benefits of a virtual memory system
To explain the concepts of demand paging, page-replacement algorithms, and allocation of page frames
Operating System Concepts Essentials – 8 th Edition 9.3 Silberschatz, Galvin and Gagne ©2011
Background
Code needs to be in memory to execute, but entire program rarely used
Error code, unusual routines, large data structures
Entire program code not needed at same time
Consider ability to execute partially-loaded program
Program no longer constrained by limits of physical memory
Program and programs could be larger than physical memory
Operating System Concepts Essentials – 8 th Edition 9.4 Silberschatz, Galvin and Gagne ©2011
Background
Virtual memory – separation of user logical memory from physical memory
Only part of the program needs to be in memory for execution
Logical address space can therefore be much larger than physical address space
Allows address spaces to be shared by several processes
Allows for more efficient process creation
More programs running concurrently
Less I/O needed to load or swap processes
Operating System Concepts Essentials – 8 th Edition 9.5 Silberschatz, Galvin and Gagne ©2011
Virtual Memory That is
Larger Than Physical Memory
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Virtual-address Space
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Virtual Address Space
Enables sparse address spaces with holes left for growth, dynamically linked libraries, etc
System libraries shared via mapping into virtual address space
Shared memory by mapping pages read-write into virtual address space
Pages can be shared during fork(), speeding process creation
Operating System Concepts Essentials – 8 th Edition 9.8 Silberschatz, Galvin and Gagne ©2011
Shared Library Using Virtual Memory
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Demand Paging
Could bring entire process into memory at load time
Or bring a page into memory only when it is needed
Less I/O needed, no unnecessary I/O
Less memory needed
Faster response
More users
Lazy swapper – never swaps a page into memory unless page will be needed
Swapper that deals with pages is a pager
Operating System Concepts Essentials – 8 th Edition 9.10 Silberschatz, Galvin and Gagne ©2011
Transfer of a Paged Memory to
Contiguous Disk Space
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Valid-Invalid Bit
With each page table entry a valid–invalid bit is associated
(v in-memory – memory resident, i not-in-memory)
Initially valid–invalid bit is set to i on all entries
Example of a page table snapshot:
….
i
i
page table
During address translation, if valid–invalid bit in page table entry
is I page fault
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Page Table When Some Pages
Are Not in Main Memory
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Page Fault
If there is a reference to a page, first reference to that page will trap to operating system:
page fault
1. Operating system looks at another table to decide:
Invalid reference abort
Just not in memory
2. Get empty frame
3. Swap page into frame via scheduled disk operation
4. Reset tables to indicate page now in memory
Set validation bit = v
5. Restart the instruction that caused the page fault
Operating System Concepts Essentials – 8 th Edition 9.14 Silberschatz, Galvin and Gagne ©2011
Aspects of Demand Paging
Extreme case – start process with no pages in memory
OS sets instruction pointer to first instruction of process, non-memory-resident -> page fault
And for every other process pages on first access
Pure demand paging
Actually, a given instruction could access multiple pages -> multiple page faults
Pain decreased because of locality of reference
Hardware support needed for demand paging
Page table with valid / invalid bit
Secondary memory (swap device with swap space)
Instruction restart
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Instruction Restart
Consider an instruction that could access several different locations
block move
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Steps in Handling a Page Fault
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Performance of Demand Paging
Stages in Demand Paging
1. Trap to the operating system
2. Save the user registers and process state
3. Determine that the interrupt was a page fault
4. Check that the page reference was legal and determine the location of the page on the disk
5. Issue a read from the disk to a free frame:
1. Wait in a queue for this device until the read request is serviced
2. Wait for the device seek and/or latency time
3. Begin the transfer of the page to a free frame
6. While waiting, allocate the CPU to some other user
7. Receive an interrupt from the disk I/O subsystem (I/O completed)
8. Save the registers and process state for the other user
9. Determine that the interrupt was from the disk
10. Correct the page table and other tables to show page is now in memory
11. Wait for the CPU to be allocated to this process again
12. Restore the user registers, process state, and new page table, and then resume the interrupted
instruction
Operating System Concepts Essentials – 8 th Edition 9.18 Silberschatz, Galvin and Gagne ©2011
Performance of Demand Paging (Cont.)
Page Fault Rate 0 p 1
if p = 0 no page faults
if p = 1, every reference is a fault
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Demand Paging Example
Memory access time = 200 nanoseconds
Average page-fault service time = 8 milliseconds
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Demand Paging Optimizations
Copy entire process image to swap space at process load time
Then page in and out of swap space
Used in older BSD Unix
Demand page in from program binary on disk, but discard rather than paging out when freeing frame
Used in Solaris and current BSD
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Copy-on-Write
Copy-on-Write (COW) allows both parent and child processes to initially share the same pages in memory
If either process modifies a shared page, only then is the page copied
COW allows more efficient process creation as only modified pages are copied
In general, free pages are allocated from a pool of zero-fill-on-demand pages
Why zero-out a page before allocating it?
vfork() variation on fork() system call has parent suspend and child using copy-on-write address
space of parent
Designed to have child call exec()
Very efficient
Operating System Concepts Essentials – 8 th Edition 9.22 Silberschatz, Galvin and Gagne ©2011
Before Process 1 Modifies Page C
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After Process 1 Modifies Page C
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What Happens if There is no Free Frame?
Page replacement – find some page in memory, but not really in use, page it out
Algorithm – terminate? swap out? replace the page?
Performance – want an algorithm which will result in minimum number of page faults
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Page Replacement
Prevent over-allocation of memory by modifying page-fault service routine to include page replacement
Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are written to disk
Page replacement completes separation between logical memory and physical memory – large virtual
memory can be provided on a smaller physical memory
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Need For Page Replacement
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Basic Page Replacement
3. Bring the desired page into the (newly) free frame; update the page and frame tables
4. Continue the process by restarting the instruction that caused the trap
Note now potentially 2 page transfers for page fault – increasing EAT
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Page Replacement
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Page and Frame Replacement Algorithms
Evaluate algorithm by running it on a particular string of memory references (reference string) and
computing the number of page faults on that string
String is just page numbers, not full addresses
Repeated access to the same page does not cause a page fault
In all our examples, the reference string is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
Operating System Concepts Essentials – 8 th Edition 9.30 Silberschatz, Galvin and Gagne ©2011
Graph of Page Faults Versus
The Number of Frames
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First-In-First-Out (FIFO) Algorithm
Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
3 frames (3 pages can be in memory at a time per process)
1 7 2 4 0 7
2 0 3 2 1 0 15 page faults
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FIFO Page Replacement
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FIFO Illustrating Belady’s Anomaly
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Optimal Algorithm
Replace page that will not be used for longest period of time
9 is optimal for the example on the next slide
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Optimal Page Replacement
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Least Recently Used (LRU) Algorithm
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LRU Algorithm (Cont.)
Counter implementation
Every page entry has a counter; every time page is referenced through this entry, copy the clock into
the counter
When a page needs to be changed, look at the counters to find smallest value
Search through table needed
Stack implementation
Keep a stack of page numbers in a double link form:
Page referenced:
move it to the top
requires 6 pointers to be changed
But each update more expensive
No search for replacement
LRU and OPT are cases of stack algorithms that don’t have Belady’s Anomaly
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Use Of A Stack to Record The
Most Recent Page References
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LRU Approximation Algorithms
LRU needs special hardware and still slow
Reference bit
With each page associate a bit, initially = 0
When page is referenced bit set to 1
Replace any with reference bit = 0 (if one exists)
We do not know the order, however
Second-chance algorithm
Generally FIFO, plus hardware-provided reference bit
Clock replacement
If page to be replaced has
Reference bit = 0 -> replace it
reference bit = 1 then:
– set reference bit 0, leave page in memory
– replace next page, subject to same rules
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Second-Chance (clock) Page-Replacement Algorithm
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Counting Algorithms
Keep a counter of the number of references that have been made to each page
Not common
MFU Algorithm: based on the argument that the page with the smallest count was probably just brought in
and has yet to be used
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Page-Buffering Algorithms
Keep a pool of free frames, always
Then frame available when needed, not found at fault time
Read page into free frame and select victim to evict and add to free pool
When convenient, evict victim
Possibly, keep list of modified pages
When backing store otherwise idle, write pages there and set to non-dirty
Possibly, keep free frame contents intact and note what is in them
If referenced again before reused, no need to load contents again from disk
Generally useful to reduce penalty if wrong victim frame selected
Operating System Concepts Essentials – 8 th Edition 9.43 Silberschatz, Galvin and Gagne ©2011
Applications and Page Replacement
All of these algorithms have OS guessing about future page access
Some applications have better knowledge – i.e. databases
Memory intensive applications can cause double buffering
OS keeps copy of page in memory as I/O buffer
Application keeps page in memory for its own work
Operating system can given direct access to the disk, getting out of the way of the applications
Raw disk mode
Bypasses buffering, locking, etc
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Allocation of Frames
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Fixed Allocation
Equal allocation – For example, if there are 100 frames (after allocating frames for the OS) and 5
processes, give each process 20 frames
Keep some as free frame buffer pool
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Priority Allocation
Use a proportional allocation scheme using priorities rather than size
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Global vs. Local Allocation
Global replacement – process selects a replacement frame from the set of all frames; one process can
take a frame from another
But then process execution time can vary greatly
But greater throughput so more common
Local replacement – each process selects from only its own set of allocated frames
More consistent per-process performance
But possibly underutilized memory
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Non-Uniform Memory Access
So far all memory accessed equally
Many systems are NUMA – speed of access to memory varies
Consider system boards containing CPUs and memory, interconnected over a system bus
Optimal performance comes from allocating memory “close to” the CPU on which the thread is scheduled
And modifying the scheduler to schedule the thread on the same system board when possible
Solved by Solaris by creating lgroups
Structure to track CPU / Memory low latency groups
Used my schedule and pager
When possible schedule all threads of a process and allocate all memory for that process within the
lgroup
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Thrashing
If a process does not have “enough” pages, the page-fault rate is very high
Page fault to get page
Replace existing frame
But quickly need replaced frame back
This leads to:
Low CPU utilization
Operating system thinking that it needs to increase the degree of multiprogramming
Another process added to the system
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Thrashing (Cont.)
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Demand Paging and Thrashing
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Locality In A Memory-Reference Pattern
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Working-Set Model
working-set window a fixed number of page references
Example: 10,000 instructions
if D > m Thrashing
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Working-set model
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Keeping Track of the Working Set
Approximate with interval timer + a reference bit
Example: = 10,000
Timer interrupts after every 5000 time units
Keep in memory 2 bits for each page
Whenever a timer interrupts copy and sets the values of all reference bits to 0
If one of the bits in memory = 1 page in working set
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Page-Fault Frequency
More direct approach than WSS
Establish “acceptable” page-fault frequency rate and use local replacement policy
If actual rate too low, process loses frame
If actual rate too high, process gains frame
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Working Sets and Page Fault Rates
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Memory-Mapped Files
Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to
a page in memory
A file is initially read using demand paging
A page-sized portion of the file is read from the file system into a physical page
Subsequent reads/writes to/from the file are treated as ordinary memory accesses
Simplifies and speeds file access by driving file I/O through memory rather than read() and write()
system calls
Also allows several processes to map the same file allowing the pages in memory to be shared
But when does written data make it to disk?
Periodically and / or at file close() time
For example, when the pager scans for dirty pages
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Memory-Mapped File Technique for all I/O
Some OSes uses memory mapped files for standard I/O
Process can explicitly request memory mapping a file via mmap() system call
Now file mapped into process address space
For standard I/O (open(), read(), write(), close()), mmap anyway
But map file into kernel address space
Process still does read() and write()
Copies data to and from kernel space and user space
Uses efficient memory management subsystem
Avoids needing separate subsystem
COW can be used for read/write non-shared pages
Memory mapped files can be used for shared memory (although again via separate system calls)
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Memory Mapped Files
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Memory-Mapped Shared Memory
in Windows
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Allocating Kernel Memory
Treated differently from user memory
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Buddy System
Allocates memory from fixed-size segment consisting of physically-contiguous pages
Memory allocated using power-of-2 allocator
Satisfies requests in units sized as power of 2
Request rounded up to next highest power of 2
When smaller allocation needed than is available, current chunk split into two buddies of next-lower
power of 2
Continue until appropriate sized chunk available
For example, assume 256KB chunk available, kernel requests 21KB
Split into AL and Ar of 128KB each
One further divided into BL and BR of 64KB
– One further into CL and CR of 32KB each – one used to satisfy request
Advantage – quickly coalesce unused chunks into larger chunk
Disadvantage - fragmentation
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Buddy System Allocator
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Slab Allocator
Alternate strategy
If slab is full of used objects, next object allocated from empty slab
If no empty slabs, new slab allocated
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Slab Allocation
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Other Considerations -- Prepaging
Prepaging
To reduce the large number of page faults that occurs at process startup
Prepage all or some of the pages a process will need, before they are referenced
But if prepaged pages are unused, I/O and memory was wasted
Assume s pages are prepaged and α of the pages is used
Is cost of s * α save pages faults > or < than the cost of prepaging
s * (1- α) unnecessary pages?
α near zero prepaging loses
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Other Issues – Page Size
Sometimes OS designers have a choice
Especially if running on custom-built CPU
Page size selection must take into consideration:
Fragmentation
Page table size
Resolution
I/O overhead
Number of page faults
Locality
TLB size and effectiveness
Always power of 2, usually in the range 212 (4,096 bytes) to 222 (4,194,304 bytes)
On average, growing over time
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Other Issues – TLB Reach
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Other Issues – Program Structure
Program structure
Int[128,128] data;
Each row is stored in one page
Program 1
for (j = 0; j <128; j++)
for (i = 0; i < 128; i++)
data[i,j] = 0;
Program 2
for (i = 0; i < 128; i++)
for (j = 0; j < 128; j++)
data[i,j] = 0;
Operating System Concepts Essentials – 8 th Edition 9.71 Silberschatz, Galvin and Gagne ©2011
Other Issues – I/O interlock
Consider I/O - Pages that are used for copying a file from a device must be locked from being selected for
eviction by a page replacement algorithm
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Reason Why Frames Used For
I/O Must Be In Memory
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Operating System Examples
Windows XP
Solaris
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Windows XP
Uses demand paging with clustering. Clustering brings in pages surrounding the faulting page
Processes are assigned working set minimum and working set maximum
Working set minimum is the minimum number of pages the process is guaranteed to have in memory
When the amount of free memory in the system falls below a threshold, automatic working set trimming
is performed to restore the amount of free memory
Working set trimming removes pages from processes that have pages in excess of their working set
minimum
Operating System Concepts Essentials – 8 th Edition 9.75 Silberschatz, Galvin and Gagne ©2011
Solaris
Maintains a list of free pages to assign faulting processes
Scanrate is the rate at which pages are scanned. This ranges from slowscan to fastscan
Pageout is called more frequently depending upon the amount of free memory available
Priority paging gives priority to process code pages
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Solaris 2 Page Scanner
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End of Chapter 8
Operating System Concepts Essentials – 8th Edition Silberschatz, Galvin and Gagne ©2011