DS1215

DS1215
Phantom Time Chip

FEATURES PIN ASSIGNMENT

• Keeps track of hundredths of seconds, seconds, min-
X1 1 16 VCCI
utes, hours, days, date of the month, months, and
years X2 2 15 VCCO
WE 3 14 BAT2
• Adjusts for months with fewer than 31 days BAT1 4 13 RST

• Leap year automatically corrected up to 2100 GND 5 12 OE

D 6 11 CEI
• No address space required Q 7 10 CEO
GND 8 9 ROM/RAM
• Provides nonvolatile controller functions for battery
backup of RAM 16–PIN DIP (300 MIL)

• Supports redundant batteries for high–reliability X1 1 16 VCCI

applications X2 2 15 VCCO
WE 3 14 BAT2
• Uses a 32.768 KHz watch crystal BAT1 4 13 RST
GND 5 12 OE
• Full ±10% operating range D 6 11 CEI

• Operating temperature range 0°C to 70°C

Q 7 10 CEO
GND 8 9 ROM/RAM

• Space-saving, 16–pin DIP package and SOIC 16–PIN SOIC (300 MIL)

• Optional industrial temperature range –40°C to +85°C PIN DESCRIPTION

(IND) X1, X2 – 32.768 KHz Crystal Connections
WE – Write Enable
DESCRIPTION BAT1 – Battery 1 Input
The DS1215 Phantom Time Chip is a combination of a
GND – Ground
CMOS timekeeper and a nonvolatile memory controller.
D – Data In
In the absence of power, an external battery maintains
Q – Data Out
the timekeeping operation and provides power for a
ROM/RAM – ROM/RAM Select
CMOS static RAM. The watch keeps track of hun-
CEO – Chip Enable Out
dredths of seconds, seconds, minutes, hours, day, date,
CEI – Chip Enable Input
month, and year information. The last day of the month
OE – Output Enable
is automatically adjusted for months with less than 31
RST – Reset
days, including correction for leap year every four years.
BAT2 – Battery 2 Input
The watch operates in one of two formats: a 12–hour
VCCO – Switched Supply Output
mode with an AM/PM indicator or a 24–hour mode. The
VCCI – +5 VDC Input
nonvolatile controller supplies all the necessary support
NOTE: Both pins 5 and 8 must be grounded.
circuitry to convert a CMOS RAM to a nonvolatile
memory. The DS1215 can be interfaced with either ORDERING INFORMATION
RAM or ROM without leaving gaps in memory. DS1215 16–pin DIP
DS1215S 16–pin SOIC
DS1215N 16–pin DIP (IND)
DS1215SN 16–pin SOIC (IND)

Copyright 1997 by Dallas Semiconductor Corporation. 032697 1/15

All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
 DS1215

OPERATION CEO remains high during this time, disabling the con-
The block diagram of Figure 1 illustrates the main ele- nected memory.
ments of the Time Chip. Communication with the Time
Chip is established by pattern recognition of a serial bit Data transfer to and from the timekeeping function is ac-
stream of 64 bits which must be matched by executing complished with a serial bit stream under control of chip
64 consecutive write cycles containing the proper data enable input (CEI), output enable (OE), and write en-
on data in (D). All accesses which occur prior to recog- able (WE). Initially, a read cycle using the CEI and OE
nition of the 64-bit pattern are directed to memory via the control of the Time Chip starts the pattern recognition
chip enable output pin (CEO). sequence by moving a pointer to the first bit of the 64 bit
comparison register. Next, 64 consecutive write cycles
After recognition is established, the next 64 read or write are executed using the CEI and WE control of the Time
cycles either extract or update data in the Time Chip and Chip. These 64 write cycles are used only to gain ac-
cess to the Time Chip.

TIMING BLOCK DIAGRAM Figure 1

X1

32.768 kHz CLOCK/CALENDAR LOGIC

ROM/RAM
X2
CEO
UPDATE
READ
CEI
OE WRITE
CONTROL TIMEKEEPING REGISTER
WE LOGIC
POWER-FAIL
RST

ACCESS
ENABLE COMPARISON REGISTER
SEQUENCE
DETECTOR

D DATA
I/O BUFFERS
Q
INTERNAL VCC

VCCI POWER–FAIL VCCO

DETECT
LOGIC

BAT1 BAT2

032697 2/15
 DS1215

When the first write cycle is executed, it is compared to 64 cycles will cause the Time Chip to either receive data
bit 1 of the 64–bit comparison register. If a match is on D, or transmit data on Q, depending on the level of
found, the pointer increments to the next location of the OE pin or the WE pin. Cycles to other locations outside
comparison register and awaits the next write cycle. If a the memory block can be interleaved with CEI cycles
match is not found, the pointer does not advance and all without interrupting the pattern recognition sequence or
subsequent write cycles are ignored. If a read cycle oc- data transfer sequence to the Time Chip.
curs at any time during pattern recognition, the present
sequence is aborted and the comparison register point- A 32,768 Hz quartz crystal can be directly connected to
er is reset. Pattern recognition continues for a total of 64 the DS1215 via pins 1 and 2 (X1, X2). The crystal se-
write cycles as described above until all the bits in the lected for use should have a specified load capacitance
comparison register have been matched. (This bit pat- (CL) of 6 pF. For more information on crystal selection
tern is shown in Figure 2.) With a correct match for 64 and crystal layout considerations, please consult
bits, the Time Chip is enabled and data transfer to or Application Note 58, “Crystal Considerations with Dal-
from the timekeeping registers may proceed. The next las Real Time Clocks”.

TIME CHIP COMPARISON REGISTER DEFINITION Figure 2

HEX
VALUE
7 6 5 4 3 2 1 0

BYTE 0 1 1 0 0 0 1 0 1 C5

BYTE 1 0 0 1 1 1 0 1 0 3A

BYTE 2 1 0 1 0 0 0 1 1 A3

BYTE 3 0 1 0 1 1 1 0 0 5C

BYTE 4 1 1 0 0 0 1 0 1 C5

BYTE 5 0 0 1 1 1 0 1 0 3A

BYTE 6 1 0 1 0 0 0 1 1 A3

BYTE 7 0 1 0 1 1 1 0 0 5C

NOTE:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated
and causing inadvertent entry to the Time Chip are less than 1 in 1019.

032697 3/15
 DS1215

NONVOLATILE CONTROLLER OPERATION TIME CHIP REGISTER INFORMATION

The operation of the nonvolatile controller circuits within Time Chip information is contained in 8 registers of
the Time Chip is determined by the level of the 8 bits, each of which is sequentially accessed one bit at
ROM/RAM select pin. When ROM/RAM is connected to a time after the 64–bit pattern recognition sequence has
ground, the controller is set in the RAM mode and per- been completed. When updating the Time Chip regis-
forms the circuit functions required to make static ters, each must be handled in groups of 8 bits. Writing
CMOS RAM and the timekeeping function nonvolatile. and reading individual bits within a register could pro-
A switch is provided to direct power from the battery in- duce erroneous results. These read/write registers are
puts or VCCI to VCCO with a maximum voltage drop of defined in Figure 5.
0.3 volts. The VCCO output pin is used to supply uninter-
rupted power to CMOS SRAM. The DS1215 also per- Data contained in the Time Chip registers is in binary
forms redundant battery control for high reliability. On coded decimal format (BCD). Reading and writing the
power–fail, the battery with the highest voltage is auto- registers is always accomplished by stepping though all
matically switched to VCCO. If only one battery is used in 8 registers, starting with bit 0 of register 0 and ending
the system, the unused battery input should be con- with bit 7 of register 7.
nected to ground.

The DS1215 safeguards the Time Chip and RAM data AM–PM/12/24 MODE
by power–fail detection and write protection. Power–fail Bit 7 of the hours register is defined as the 12– or
detection occurs when VCCI falls below VTP, which is 24–hour mode select bit. When high, the 12–hour mode
equal to 1.26 x VBAT. The DS1215 constantly monitors is selected. In the 12–hour mode, bit 5 is the AM/PM bit
the VCCI supply pin. When VCCI is less than VTP, a com- with logic high being PM. In the 24–hour mode, bit 5 is
parator outputs a power–fail signal to the control logic. the second 10–hour bit (20 –23 hours).
The power–fail signal forces the chip enable output
(CEO) to VCCI or VBAT–0.2 volts for external RAM write OSCILLATOR AND RESET BITS
protection. During nominal supply conditions, CEO will Bits 4 and 5 of the day register are used to control the
track CEI with a maximum propagation delay of 20 ns. reset and oscillator functions. Bit 4 controls the reset pin
Internally, the DS1215 aborts any data transfer in prog- (Pin 13). When the reset bit is set to logic 1, the reset in-
ress without changing any of the Time Chip registers put pin is ignored. When the reset bit is set to logic 0, a
and prevents future access until VCCI exceeds VTP. A low input on the reset pin will cause the Time Chip to
typical RAM/Time Chip interface is illustrated in abort data transfer without changing data in the time-
Figure 3. keeping registers. Reset operates independently of all
other inputs. Bit 5 controls the oscillator. When set to
When the ROM/RAM pin is connected to VCCO, the con- logic 0, the oscillator turns on and the watch becomes
troller is set in the ROM mode. Since ROM is a read– operational.
only device that retains data in the absence of power,
battery backup and write protection is not required. As a
result, the chip enable logic will force CEO low when ZERO BITS
power fails. However, the Time Chip does retain the Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that
same internal nonvolatility and write protection as de- will always read logic 0. When writing these locations,
scribed in the RAM mode. In addition, the chip enable either a logic 1 or 0 is acceptable.
output is set at a low level on power–fail as VCCI falls be-
low the level of VBAT. A typical ROM/Time Chip interface
is illustrated in Figure 4.

032697 4/15
 DS1215

RAM/TIME CHIP INTERFACE Figure 3

CMOS STATIC RAM

A0 – AN ADD
DATA I/O D0 – D7

WE

OE

CE VCC

DS1215

10 15
CEO VCCO
12 6
OE D
3 7
WE Q
11
CE CEI VCCI +5 VDC
13 ROM/ 9
RST RST RAM
4 14 OR TIE TO GND FOR
BAT1 BAT2
X1 X2 ONE–BATTERY
+ + OPERATION
BAT1 BAT2
1 2

32.768 KHz

ROM/TIME CHIP INTERFACE Figure 4

ROM

A0 – AN ADD VCC

DATA I/O D0 – D7
A2

OE OE

A0 CE

DS1215

6 10
D CEO
12 7
OE Q
3 16
WE VCCI +5 VDC
11 15
CE CEI VCCO
13 ROM/ 9
RST RST RAM
4 14 OR TIE TO GND FOR
BAT1 BAT2
X1 X2 ONE–BATTERY
+ + OPERATION

BAT1 BAT2
1 2

32.768 KHz

032697 5/15
DS1215

TIME CHIP REGISTER DEFINITION Figure 5

REGISTER RANGE
(BCD)
7 6 5 4 3 2 1 0

0 0.1 SEC 0.01 SEC 00–99

1 0 10 SEC SECONDS 00–59

2 0 10 MIN MINUTES 00–59

12/24 0 10 HR HOUR 01–12

3
A/P 00–23

4 0 0 OSC RST 0 DAY 01–07

5 0 0 10 DATE DATE 01–31

6 0 0 0 10 MONTH 01–12
MONTH

7 10 YEAR YEAR 00–99

032697 6/15
 DS1215

ABSOLUTE MAXIMUM RATINGS*

Voltage on any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds

* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V 1
Logic 1 VIH 2.2 VCC+0.3 1
Logic 0 VIL –0.3 +0.8 V 1
VBAT1 or VBAT2 Battery Voltage VBAT 2.5 3.7 V 7

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current ICCI 5 mA 6
Supply Current VCCO = VCCI–0.3 ICCO1 80 mA 8
Input Leakage IIL –1.0 +1.0 µA 11
Output Leakage ILO –1.0 +1.0 µA
Output @ 2.4V IOH –1.0 mA 2
Output @ 0.4V IOL 4.0 mA 2

DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC < 4.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CEO Output VOH1 VCCI or V 9
VBAT–0.2
VBAT1 or VBAT2 Battery Current IBAT 1 µA 6
Battery Backup Current ICCO2 10 µA 10
@ VCCO = VBAT–0.2V

032697 7/15
DS1215

AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC = 4.5 to 5.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CEI Access Time tCO 100 ns
OE Access Time tOE 100 ns
CEI to Output Low Z tCOE 10 ns
OE to Output Low Z tOEE 10 ns
CEI to Output High Z tOD 40 ns
OE to Output High Z tODO 40 ns
Read Recovery tRR 20 ns
Write Cycle tWC 120 ns
Write Pulse Width tWP 100 ns
Write Recovery tWR 20 ns 4
Data Setup tDS 40 ns 5
Data Hold Time tDH 10 ns 5
CEI Pulse Width tCW 100 ns
RST Pulse Width tRST 200 ns
CEI Propagation Delay tPD 5 10 20 ns 2, 3
CEI High to Power–Fail tPF 0 ns

AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC > 4.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery at Power–Up tREC 2 ms
VCC Slew Rate 4.5 – 3.0V tF 0 ms

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 5 10 pF
Output Capacitance COUT 5 10 pF

032697 8/15
 DS1215

AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO (0°C to 70°C; VCC = 5V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CEI Access Time tCO 100 ns
OE Access Time tOE 100 ns
CEI to Output in Low Z tCOE 10 ns
OE to Output in Low Z tOEE 10 ns
CEI to Output in High Z tOD 40 ns
OE to Output in High Z tODO 40 ns
Address Setup Time tAS 20 ns
Address Hold Time tAH 10 ns
Read Recovery tRR 20 ns
Write Cycle Time tWC 120 ns
CEI Pulse Width tCW 100 ns
OE Pulse Width tOW 100 ns
Write Recovery tWR 20 ns 4
Data Setup Time tDS 40 ns 5
Data Hold Time tDH 10 ns 5
RST Pulse Width tRST 200 ns
CEI Propagation Delay tPD 5 10 20 ns 2, 3
CEI High to Power Fail tPF 0 ns

AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO (0°C to 70°C; VCC < 4.5V)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Recovery at Power–Up tREC 2 ms
VCC Slew Rate 4.5 – 3.0V tF 0 ms

032697 9/15
DS1215

TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND

WE = VIH

tRC
tRR
CEI
tCO

tOD

OE tOE

tOEE
tODO

ÉÉÉ ÉÉÉ
tCOE

ÉÉÉ ÉÉÉ
Q
OUTPUT DATA VALID

TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND

OE = VIH

tWC
WE tWR
tWP

tWR
CEI
tCW

tDH
tDS

ÉÉÉÉÉ ÉÉÉÉÉÉÉ
D tDH

ÉÉÉÉÉ DATA IN STABLE

ÉÉÉÉÉÉÉ

032697 10/15
 DS1215

TIMING DIAGRAM: READ CYCLE ROM/RAM = VCCO

ÇÇÇÇÇÇ
tRC

ÇÇÇÇÇÇ
tCO tRR

ÇÇÇÇÇÇ
CEI

ÇÇÇÇÇÇÇ
tOD
tRR

ÇÇÇÇÇÇÇ
tRC

ÇÇÇÇÇÇÇ
OE tOE

tODO
tAS

ÉÉÉÉÉ
tAH
tAS tAH

ÉÉÉÉÉ
WE
tOEE

tCOE

Q OUTPUT DATA VALID

TIMING DIAGRAM: WRITE CYCLE ROM/RAM = VCCO

tWC

ÇÇÇÇÇÇ
tWR
tCW

ÇÇÇÇÇÇ
CEI

ÇÇÇÇÇÇÇ
tWR
tWC

OE
ÇÇÇÇÇÇÇ tOW

ÇÇÇÇÇ
tAS tAH
tAS

ÇÇÇÇÇ
tAH

ÇÇÇÇÇ
WE

tDS tDH
tDS tDH

D DATA IN STABLE

032697 11/15
DS1215

TIMING DIAGRAM: POWER DOWN

ÇÇÇÇÇÇÇÇÇÇ
tCE

ÇÇÇÇÇÇÇÇÇÇ
CEI
VIH

ÇÇÇÇÇÇÇÇÇÇ
VIL

tPD
tPF

tCE VBAT - 0.2V

ROM/RAM = GND CEO
VIH
VIL

ROM/RAM = VCCO CEO

VCCI
4.5V
tF
3V

TIMING DIAGRAM: POWER UP

ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
VIH
CEI
VIL

BAT - 0.2V

ROM/RAM = GND CEO

VIL
tREC

tPD

ROM/RAM = VCCO CEO

4.5V

VCCI

TIMING DIAGRAM: RESET FOR TIME CHIP

tRST
RST

032697 12/15
 DS1215

NOTES:
1. All voltages are referenced to ground.

2. Measured with load shown in Figure 6.

3. Input pulse rise and fall times equal 10 ns.

4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.

5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.

6. Measured without RAM connected.

7. Trip point voltage for power–fail detect. VTP = 1.26 x VBAT. For 10% VCC= 5V + 10% operation VBAT = 3.5V max.;
for 5% operation VBAT = 3.7V max.

8. ICC01 is the maximum average load current the DS1215 can supply to memory.

9. Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to VCCO, CEO will go
to a low level as VCCI falls below VBAT.

10. ICC02 is the maximum average load current that the DS1215 can supply to memory in the battery backup mode.

11. Applies to all input pins except RST. RST is pulled internally to VCCI.

OUTPUT LOAD Figure 6

+5V

1.1KΩ

50 pF
680Ω

032697 13/15
DS1215

DS1215 TIME CHIP

B D J

1
A

PKG 16–PIN

DIM MIN MAX

C
A IN. 0.740 0.780
MM
F
B IN. 0.240 0.260
K E MM
G
C IN. 0.120 0.140
MM

D IN. 0.300 0.325

MM

E IN. 0.015 0.040

MM

F IN. 0.110 0.140

MM

G IN. 0.090 0.110

MM

H IN. 0.300 0.370

MM

J IN. 0.008 0.012

MM

K IN. 0.015 0.021

MM

032697 14/15
 DS1215

DS1215S SERIAL TIMEKEEPER 16–PIN SOIC

K G

B H

C F

E phi L
J

PKG 16–PIN

DIM MIN MAX

A IN. 0.402 0.412

MM 10.21 10.46

B IN. 0.290 0.300

MM 7.37 7.65

C IN. 0.089 0.095

MM 2.26 2.41

E IN. 0.004 0.012

MM 0.102 0.30

F IN. 0.094 0.105

MM 2.38 2.68

G IN. 0.050 BSC

MM 1.27 BSC

H IN 0.398 0.416
MM 10.11 10.57

J IN 0.009 0.013
MM 0.229 0.33

K IN. 0.013 0.019

MM 0.33 0.48

L IN 0.016 0.040
MM 0.40 1.02

PHI 0° 8°

032697 15/15