3/5/2025

UNIT-I

INTRODUCTION TO
EMBEDDED COMPUTING
AND ARM PROCESSORS

UNIT-I
INTRODUCTION TO EMBEDDED COMPUTING
AND ARM PROCESSORS

Concept of RISC, RISC vs CISC, RISC-V Architecture

– Pipeline – RISC-V Ecosystem – Applications of
RISC-V in Embedded Systems,

ARM Processor Fundamentals, Instruction Set and

Programming using ARM Processor,

Embedded system design process – Design example

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RISC and CISC

• RISC (reduced instruction set computer) and CISC
(complex instruction set computer) refer to the popular
processor architectures that utilize different data
processing instruction sets to perform basic logical and
input/output operations.

• RISC and CISC represent key processor architectures

developed to boost CPU performance.

• CPU performance can be optimized in either of two

ways:
• Reduce the number of instructions per program, or
• Minimize cycles per instruction.

• The fundamental difference between the two is that

• RISC has less number of instructions , with each one
capable of performing a single operation,
• while CISC has a large number of complex
instructions capable of carrying out multiple internal
operations.
• Example: ADD 1800, 1801
CISC
• The ADD instruction picks up numbers from memory
locations 1800 and 1801 or registers. Later, the picked-
up numbers are added and eventually stored in location
1800.

• Moreover, these instructions consume minimum RAM as

the hardware takes care of most tasks while decoding
the instructions in the beginning stages.

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• Hence, in CISC architectures, the CPU is

entitled to put in more work to perform a
single instruction. As the execution of the
instruction takes more time, clock speeds
a r e c o m p r o m i s e d . M o r e o v e r, C I S C
operations require more transistors to
decode complex instructions.

• Commonly known examples of CISC

processors are AMD, Intel x86, VAX,....

RISC
Let’s consider the same ADD instruction and look at how
RISC devices accomplish it.
• To begin with, RISC machines do not execute the ADD
instruction in one step. Instead, it is broken down into
multiple steps.
• For example, you need to load the numbers from
memory through a LOAD instruction, followed by an ADD
instruction that adds them, and finally, a STORE
instruction that stores the result in memory.

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Load X, 1600
Load Y, 1601
ADD X, Y
Store 1600, X
• Each of these instructions consumes only one clock
cycle, the entire addition operation is accomplished in
much fewer clock cycles.
• However, such time benefits also present some
disadvantages.
• For instance, since RISC processors use simpler
instruction sets, the complex and high-level instructions
need to be divided into multiple, simple instructions.

• The task of breaking down complex commands into

simpler ones is accomplished by compilers .
• As a result, software components have more work to do
in RISC than the processor’s hardware, as seen in CISC.
• Unlike CISC processors, the logic of RISC machines is
simple to decode.
• Consequently, fewer transistors are required to
complete tasks.
• RISC architecture uses a simplified set of instructions
that tend to work less but execute at a significant pace.

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• The key feature of such machines is that they enable

developers to fit in more general registers in CPUs and
thereby focus on employing parallel threads to
complete complex yet optimized instructions.
• It boosts internal parallelism and speeds up the CPU’s
instruction execution time.

• ARM (Advanced RISC Machine) is a well-known example

of the RISC framework.
• Its processors are observed in desktops, laptops,
smartphones, gaming consoles, and several other smart
IoT devices that are battery-operated where energy
efficiency is essential.

• The CISC architecture tries to elevate CPU performance by

finishing a task in minimal lines of assembly code,
• while RISC relies on the strategy of l owering the execution
time of each instruction.
• For example, on an Intel 8086 processor (CISC device),
multiple operations on two 8-bit numbers may require
around 70 to 77 clock cycles.
• In contrast, a PIC microcontroller (RISC device) may take up
to 38 clock cycles.
• As the example reveals, the RISC device is 2x faster than its
CISC counterpart.
• Since CISC devices take more time to execute a single
operation, the architecture does not support the parallel
processing and pipelining of instructions.
• On the contrary, in the RISC architecture, every instruction is
completed in one clock cycle, thereby promoting the
pipelining of instructions.

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Sno CISC RISC

1. CISC is the short form for Complex RISC refers to Reduced

Instruction Set Computer. Instruction Set Computer.

2. The CSIC architecture processes The RISC architecture executes

complex instructions that require simple yet optimized instructions
several clock cycles for execution. in a single clock cycle. It
On average, it takes two to five processes instructions at an
clock cycles per instruction (CPI). average speed of 1.5 clock cycles
per instruction (CPI).

3. CISC focuses on hardware, such as RISC focuses more on software

transistors, to execute instructions. such as codes or compilers to
execute instructions.

4. Implementation of complex RISC lacks special memory and

instructions is enabled through thus utilizes specialized hardware
memory units. to execute instructions.

Sno CISC RISC

4. Implementation of complex RISC lacks special memory

instructions is enabled through and thus utilizes specialized
memory units. hardware to execute
instructions.

5. CISC devices are installed RISC devices are embedded

with a microprogramming unit. with a hardwired
programming unit.

6. CISC uses a variety of RISC is provided with a

instructions to accomplish reduced instruction set,
complex tasks. which is typically primitive
in nature.

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Sno CISC RISC

7. CISC processors are generally RISC processors use hardwired

micro-coded, thereby allowing units to control CPUs.
ROM-based CPU control. However,
modern CISC processors also use
hardwired units for easy CPU
control.

8. A CISC processor works with 16 A RISC processor utilizes 32 bits

bits to 64 bits to execute each to execute each instruction.
instruction.

9. A CISC architecture uses one cache The RISC architecture relies on

to store data as well as instructions. split caches, one for data and the
However, recent CISC designs other for instructions.
employ split caches to divide data
and instructions.

Sno CISC RISC

10. CISC processors use a RISC processors rely on a

memory-to-memory register-to-register
framework to execute mechanism to execute ADD,
instructions such as ADD, STORE, and independent
LOAD, and even STORE. LOAD instructions.

11. The CISC architecture uses The RISC architecture

only one register set. utilizes multiple registers
sets.

12. Since CISC devices operate in Since RISC machines

a multi-clock environment, it operate on single clock
supports addressing modes in cycles, it has limited
the range of 12 to 24. addressing modes.

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Sno CISC RISC

13. CISC processors are capable Since RISC processors

of processing high-level support a limited set of
programming language addressing modes, complex
statements more efficiently, instructions are synthesized
thanks to the support of through software codes.
complex addressing modes.

14. CISC does not support RISC processors support

parallelism and pipelining. As instruction pipelining.
such, CISC instructions are
less pipelined.

15. CISC complexity is embedded RISC complexity is pinned

in microprograms. with compilers that execute
the software program.

Sno CISC RISC

16. CISC instructions require high RISC instructions require

execution time. less time for execution.

17. CISC supports code expansion, RISC does not support code
which is similar to macro expansion.
expansion, wherein a copy of
inline functions is added in
each place wherever it is
called. Such inline functions
run faster than normal
functions.

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Sno CISC RISC

18. In the CISC architecture, the In RISC processors,

task of decoding instructions instruction decoding is
is quite complex. simpler than in CISC.

19. Some examples of CISC Examples of RISC

processors include Intel x86 processors include Alpha,
CPUs, System/360, VAX, ARC, ARM, AVR, MIPS,
PDP-11, Motorola 68000 PA-RISC, PIC, Power
family, and AMD. Architecture, and SPARC.

20. CISC processors are used for RISC processors are suitable
low-end applications such as for high-end applications,
home automation devices, including image and video
security systems, etc. processing,
telecommunications, etc.