FET DC Analysis
PREPARED BY: JEFFERSON B. REMUDARO, ECE
Review for the DC analysis for FET
FET – Field Effect Transistor
• Is a type of transistor which uses
electric field to control the flow of
current.
• FETs are devices with three
terminal: source, gate & drain.
FET – Field Effect Transistor
• Is also known as a unipolar device
transistor since they only involve
single charge carrier in it
operation.
• FET display a very high input
impedance at low frequencies.
FET – Field Effect Transistor
• The drain current will flow from
drain (D) terminal to source (S)
terminal, by applying a source
voltage across the gate (G)
terminal and source (S)
terminal, you can control the
drain current.
FET vs BJT
• Voltage Controlled Device • Current Controlled Device
• Unipolar Devices • Bipolar Devices
• Either free electrons or holes • Both electrons or holes
• Application • Application
• Amplifier • Amplifier
• Analog switch • Analog switch
• Integrated circuit • Integrated circuit
• Buffer amplifier • Buffer amplifier
• oscillators • oscillators
Types of FET
Fixed Bias Configuration
• Is the simplest basing arrangement for the DD
JFET device.
• Is one of the few FET that can be solve just as
D
directly using either a mathematical or
graphical approach.
• The RG is present to ensure Vi appears at the
input of FET amplifier. G
• For DC analysis:
GG
IG ≈ 0A
Therefore: VRG = IGRG = 0V
Fixed Bias Configuration
Re-draw the circuit for DC analysis: • Note: the zero voltage drop across RG
permits replacing RG by short circuit
DD IG ≈ 0A equivalent.
• Applying KVL @ Loop
D
-VGG - VGS = 0
+ VGS = -VGG VGG is fixed dc supply
VDS
+
VGS - • For drain current
-
ID = IDSS (1 – VGS / VP)²
GG
Fixed Bias Configuration
For Graphical solution: • The transfer curve can be plot using four
points define at the table below:
Table 1.0
• For any given values of VGS & ID the transfer
curve can be plotted.
Fixed Bias Configuration
• The fixed level of VGS has been superimposed as
a vertical line at VGS = - VGG. At any point on the
line, the level VGS is - VGG and the level of ID must
simply be determined on this vertical line. The
point where the curve and line intersect is the
common solution to the configuration and
referred to as the quiescent or operating point.
• For mathematical approach use the Shockley’s
equation by substituting the equation of VGS in
equation below that derive from the circuit.
ID = IDSS (1 – VGS / VP)²
Fixed Bias Configuration
Example: Det. the VGSQ, IDQ, VDS, VD, VG, & VS, • Graphical Solution:
from the circuit.
IDSS = 10mA
VP = - 8V
by KVL @ loop:
+
VGSQ = - VGG = - 2V
+
VDS
VGS -
-
Fixed Bias Configuration
• Graphical Solution: • The result of the intersection of the curve and load-line
provide the solution for IDQ = 5.6mA.
• For Mathematical approach:
ID = IDSS (1 – VGS / VP)²
ID = 10mA (1 – (-2 / -8))²
ID = 5.625mA
VDS = VDD - RDID = 16 – (2kΩ)(5.625mA)
VDS = 4.75V = VD
VG = VGS = -2V ; since VS = 0V
• The results between Graphical and Mathematical
approach generate the same solutions.
Voltage Divider Configuration
Example: Det. the VGSQ, IDQ, VDS, VD, VG, & VS,
from the circuit.
VG = VDDR2 = 16 (270kΩ)
R1+R2 2.1M+270k
VG = 1.823V
IDSS = 8mA
VP = - 4V by KVL @ loop:
G +
VGS
-
VGS = VG – IDRS eq. 1 ; IS = ID
Note: Eq. 1 is used to graph the load line at
transfer curve to determine the Q pt. at
intersection.
Voltage Divider Configuration
Graphical Method: • Set condition using eq. 1 to plot the load-line.
Graph the load-line using
VGS = VG – IDRS eq. 1
this condition. Then
if VGS = 0V ; ID = 1.215mA connect both point until
it intersect at the curve
if ID = 0A ; VGS = 1.823V which commonly
referred to as the Q-pt.
From the Q pt. at the transfer curve:
VGSQ = -1.8V & IDQ = 2.4mA
VD = VDD - IDRD = 16 – (2.4mA )(2.4kΩ)
VD = 10.24V
VDS = VDD –ID (RD + RS) = 16 – (2.4mA )(2.4kΩ+ 1.5kΩ)
VDS = 6.64V
VS = ISRS = IDRS = 2.4mA(1.5kΩ) = 3.6V
Voltage Divider Configuration
Mathematical Method: using Shockley’s Equation. • Note: Using the Quadratic formula we arrive in two different
values of ID, this condition should meet in choosing ID:
ID = IDSS (1 – VGS / VP)² ; Subst. eq 1 in this eq.
2 2
• IDQ ≤ IDSS or VGSQ ≤ VP.
VG – IDRS 1.823 - 1500ID
-3
ID = IDSS 1 – = 8x10 1–
VP -4 From the Q pt. at the transfer curve:
-3
2 VGSQ = 1.823V – 2.413mA (1.5kΩ)
16ID = 8x10 5.823 - 1500ID
VGSQ = -1.797V & IDQ = 2.413mA
16ID = 0.271 – 139.752ID + 18000ID2 VD = VDD - IDRD = 16 – (2.413mA )(2.4kΩ)
18000ID2 - 155.752ID + 0.271 = 0 Quadratic equation. VD = 10.21V
Using the Quadratic formula we can solve IDQ.
VDS = VDD –ID (RD + RS) = 16 – (2.413mA )(2.4kΩ+ 1.5kΩ)
ID1 = 6.24mA & ID2 = 2.413mA
VDS = 6.589V
IDQ = ID2 = 2.413mA
VS = ISRS = IDRS = 2.413mA(1.5kΩ) = 3.62V
Voltage Divider Configuration
• Note:
• Mathematical approach or Graphical approach can be used to solve for the operating point of
JFET or D-MOSFET and arrive on almost the same values as shown in the example.
• A graphical analysis require to plot the Shockley’s equation using values of IDSS and VP that
identifies in the circuit and the table 1.0
• A mathematical analysis require to determine the equation of VGS from the given circuit and
substitute it in Shockley’s equation to solve for the value of ID.
• Using both approach that arrive in almost the same answer will confirm that you have a
correct solution.
