Huge Amount of Self-Contained

Devices
Communication • Sensors
• A-to-D converters
Protocols • D-to-A
• Memory
Notes and/or Reference • Microcontrollers
• Etc…

• We need ability/fluency to extract info from and

work with them

10/22/19 6.111 Fall 2019 1 10/22/19 6.111 Fall 2019 2

Board: $5.00 from Ebay

How to get Access to the signals MPU-9250 Chip: $3.00 in bulk

in first place? • Use in Lab 5B

• 3-axis Accelerometer (16-bit readings)
• Some accelerometers are analog out (can therefore • 3-axis Gyroscope (16-bit readings)
read them with an A-to-D converter) (ADXL335, for • 3-axis Magnetic Hall Effect Sensor (Compass) (16 bit readings)
example) • SPI or I2C communication (!)…no analog out
• On-chip Filters (programmable)
• These have limited functionality…and also it is • On-chip programmable offsets
analog so there’s the whole noise issue....which is • On-chip programmable scale!
not nice • On-chip sensor fusion possible (with quaternion output)!
• Interrupt-out (for low-power applications!)
• Most flavors of sensors are digital • On-chip sensor fusion and other calculations (can do orientation math on-chip
or pedometry even)
• So cheap they usually aren’t even counterfeited! J
• Communicates using either I2C or SPI

10/22/19 6.111 Fall 2019 3 10/22/19 6.111 Fall 2019 4

Common Chip-to-Chip Communication
Protocols Parallel and Series at High Level
• Parallel (not so much anymore)…mostly memory and things
that need to send data at very high rates such as a camera

• Serial (UART) (still common in random devices, reliable and Parallel Link: Serial Link:
easy to implement)

• SPI (Serial Peripheral Interface) very common

• I2C (Inter-Integrated Circuit Communication) very common

• I2S (Inter-Integrated Circuit Sound Bus) very common in

audio-specific applications Currently pushing 10-30Gb/s …

10/22/19 6.111 Fall 2019 5 10/22/19 6.111 Fall 2019 6

Serial Communications Common Chip-Chip Communication

• Sending information one bit at a time vs. many bits in parallel Protocols
• Serial: good for long distance (save on cable, pin and connector cost,
easy synchronization). Requires “serializer” at sender, “deserializer” at
receiver • Parallel (not so much anymore).
• Parallel: issues with clock skew, crosstalk, interconnect density, pin
count. Used to dominate for short-distances (eg, between chips).
• BUT modern preference is for parallel, but independent serial links (eg,
PCI-Express x1,x2,x4,x8,x16) as a hedge against link failures. • Serial (UART) (still common in some classes of devices)
• A zillion standards
• Asynchronous (no explicit clock) vs. Synchronous (CLK line in addition • SPI (Serial Peripheral Interface) very common
to DATA line).
• Recent trend to reduce signaling voltages: save power, reduce
transition times
• I2C (Inter-Integrated Circuit Communication) very
• Control/low-bandwidth Interfaces: SPI, I2C, 1-Wire, PS/2, AC97
• Networking: RS232, Ethernet, T1, Sonet
common
• Computer Peripherals: USB, FireWire, Fiber Channel, Infiniband, SATA,
Serial Attached SCSI
• I2S (Inter-Integrated Circuit Sound Bus) very common
10/22/19 6.111 Fall 2019 7 10/22/19 6.111 Fall 2019 8
 Serial (UART)
Serial (UART)
TX/RX
Device 1 Device 2

RX/TX • Line Hi at rest

• Drops Low to indicate start
• Stands for Universal Asynchronous Receiver Transmitter
• 8 (or 9 bits follows) sent least significant bit first
• Requires agreement ahead-of-time between devices
regarding things like clock rate (BAUD), etc… • Goes high (stop bit)
• Two wire communication • Can have optional parity bit for simple error correction
• Cannot really share
• (every pair of devices needs own pair of lines so wires scales
as 2" where " is the number of devices)
• Data rate really < 115.2Kbps
• Data sent LSB first

10/22/19 6.111 Fall 2019 9 10/22/19 6.111 Fall 2019 10

Note on Terminology SPI

MOSI
Master MISO Slave
Device Device
SCK
CE/CS
• In device-to-device communication, it is common to have
one device labeled the ”Master” and one labeled the • Stands for Serial-Peripheral Interface
“Slave”…the Master controls the Slave(s) in these settings. • Four Wires:
• Trace history of this naming terminology back to 1940s and • MOSI: Master-Out-Slave-In
before • MISO: Master-In-Slave-Out
• I’ve seen some alternatives suggested: Leader/Follower, • SCK: Serial Clock
Primary/Secondary (other ideas?), but this naming scheme • CE/CS (Chip Enable or Chip Select)
persists in the field and on data sheets • SCK removes need to agree ahead of time on data
• Movement from this terminology has occurred more rate (from UART)…makes data interpretation
readily in software than hardware…Django has transitioned easier!
• Los Angeles actually requested manufacturers to use • High Data Rates: (1MHz up to ~70 MHz clock (bits))
alternative naming scheme as far back as 2003
• Data MSB or LSB first…up to devices
10/22/19 6.111 Fall 2019 11 10/22/19 6.111 Fall 2019 12
 MOSI
SPI Example From MCP3008 Datasheet

SPI
Master MISO Slave
Device Device 1
SCK MCP3008 is a 8-channel 10 bit ADC from
CE0/CS0 Microchip Semi that communicates over
SPI
• Can share MOSI/MISO Bus so the wire
requirement scales as 3 + # where # is Slave CMOD-A7-35T
MCP3008

the number of devices Device 2

CE1/CS1
• Addition of multiple slaves requires Here I am talking to a MCP3008 10 bit ADC

additional select wires CS

• Hardware/firmware for SPI is pretty MOSI Sends its data MSB first
easy to implement: X X 1 1 0 0 1 X X X X X X X X X X X X X

• Wires are uni-directional MISO …

X X X X X X X X 0 0 0 0 1 0 1 1 0 1 1
• Classic “duh” sort of approach to digital
communication, but very robust. SCK

10/22/19 6.111 Fall 2019 13 10/22/19 6.111 Fall 2019 14

SPI Example SPI In Real Life

“Give me a
single-ended
reading…” “From your “0001011011” ”We’re done
“Hey MCP3008” channel 1” here. ”
• Here I am talking to the same CS
chip I was daydreaming about
CS
talking to on the previous
MOSI
slide. SCK
X X 1 1 0 0 1 X X X X X X X X X X X X X • Dreams do come true
MISO … • I’m saying, “give me your MOSI 11001000001011011
X X X X X X X X 0 0 0 0 1 0 1 1 0 1 1 measurement on Channel 1,”
and it is responding with MISO
SCK
“10’b0001011011” mapped to
3.3V or 0.293 V
Artix-7 (Master Device) Dialog
MCP3008 (Slave Device) Dialog X means don’t care

10/22/19 6.111 Fall 2019 15 10/22/19 6.111 Fall 2019 16

 I2C
MOSI

SPI* Master
Device
MISO
SCK
Slave
Device

• Six Wires: CE0/CS0 • Stands for Inter-Integrated Circuit communication

D/C
• MOSI: Master-Out-Slave-In
RES
• Invented in 1980s
• MISO: Master-In-Slave-Out
• SCK: Clock • Two Wire, One for Clock, one for data (bi-
• CE/CS (Chip Enable or Chip Select) directional)
• RES: Reset Device
• D/C: Data/Command (often seen in devices
• Usually 100kHz or 400 kHz clock (newer versions go
where you need to write tons of data (i.e. a to 3.4 MHz)
display)
• Three/Two Wires: Master SDA Slave
Device Device
• If a device has nothing to say, drop MISO:
• If you assume only one device on bus drop SCL
CE/CS, so only have SCK and MOSI, sometimes
just called “DO” (for data out) in this situation

10/22/19 6.111 Fall 2019 17 10/22/19 6.111 Fall 2019 18

On i2C Multiple Devices Require More to story (need pull-up resistors)

Same # of Wires • i2C uses an open drain
• Devices come with their own ID
Master
Device
SDA
Slave
• Meaning both Master and Slave Device
numbers (originally a 7 bit value
Device 1
are either:
SCL
but more modern ones have 10 • LOW
bits)…allows potentially up to • High-Impedance
2^7 devices or 2^10 on a bus • Need external pull-up resistors
(theoretically anyways) Slave
Device 2
These resistors
are large reaso
n
3.3V 3.3V why data rate
is so low!

• ID’s are specified at the factory, 4.7kΩ 4.7kΩ

usually several to choose from

when you implement and you Master
Device
SDA Slave
Device
select them by pulling external
pins HI or LOW SCL

10/22/19 6.111 Fall 2019 19 10/22/19 6.111 Fall 2019 20

 As a result:
Tri-State 3.3V

4.7kΩ
• inout is an “input-output”…needs some special inout sda;
logic sda_val;

handling...you can both write to them (only using assign sda = sda_val? 1’bz: 1’b0; SDA

combinational logic) and read from them...the Wanna write to SDA? SDA in

usual way to work with them is the following: sda_val <= 0; //or 1 if desired

Wanna read to SDA?

In verilog… VGS
sda_val <= 1;
inout sda;
//wait clock cycle…
some_reg <= sda; //read from input
logic sda_val;

assign sda = sda_val? 1’bz: 1’b0; Mode Master Slave

Master Transmit HiZ (HI) or LOW HiZ (listening)

//if desired:
always_ff @(posedge clk)begin Slave ACK/NACK HiZ (listening) HiZ (HI) or LOW
sda_val <= 1; //do a non-blocking assign to sda_val if desired Slave Transmit HiZ (listening) HiZ (HI) or LOW
//this indirectly affects sda then
Master ACK/NACK HiZ (HI) or LOW HiZ (listening)
end

10/22/19 6.111 Fall 2019 21 10/22/19 6.111 Fall 2019 22

i2C Operation Meanings I: (Start, Stop, Sampling)

• Data is conveyed on SDA (Either from Master or
Slave depending on point during communication) Master Claims Bus (START)
Master Releases Bus (STOP)
By pulling SDA HI while SCL is HI
Idle State
• SCL is a 50% duty cycle clock SDA and SCL sit HI
By pulling SDA LOW while SCL is HI

• SDA generally changes on falling edge of SCL (isn’t SDA: HI

required, but is a convenient marker for LO

• SDA sampled at rising edge of SCL

Data/State on SDA transitions
• Master is in charge of setting SCL frequency and SCL: HI @ negedge of SCL*

driving it LO

• Data is sent MSB first Data from SDA sampled @ posedge of SCL

*not specified but probably easiest spot to do

10/22/19 6.111 Fall 2019 23 10/22/19 6.111 Fall 2019 24

Meanings II Address Meanings III (Read/Write Bit)
• First thing sent by Master is 7 bit address (10 bit in • After sending address, a Read/Write Bit is specified
more modern i2C…don’t worry about that) by Master on SDA:
• If Write (0) is specified, the next byte will be a register to
write to, and following bytes will be information to write
• If a device on the bus possesses that address, it into that register
acknowledges (ACK/NACK=0) and it becomes the • If Read (1) is specified, the Slave will start sending data out,
slave for the time being. with the Master acknowledging after every byte (until it
wants data to not be sent anymore)
• All other devices (other than Master/Slave Devices)
will ignore until STOP signal appears later on.

10/22/19 6.111 Fall 2019 25 10/22/19 6.111 Fall 2019 26

Meanings IV (ACK/NACK) Meanings V

• After every 8 bits, it is the listener’s job to • For Master Device to write to Slave Device:
• START
acknowledge or not acknowledge the data just • Send Device Address (with Write bit)

sent (called an ACK/NACK) • Send register you want to write to

• Send data…until you’re satisfied, doing ACK/NACKs along the way

• Transmitter pulls SDA HI and listens for next • STOP

• For Master Device to read from Slave Device a common (though not universal procedure) is:
reading (@posedge of SCL): • START
• Send Device Address (with Write bit)
• If LOW, then receiver acknowledges data
• Send register you want to read from (think of this like setting a cursor in the register map)
• If remains HI, no acknowledgement • ReSTART communication
• Send Device Address (With Read bit)
• Transmitter/Receiver act accordingly • Read the bits (it’ll start from where the cursor was left pointing at)
• After every 8 bits, it is Master’s job to acknowledge Slave…continued acknowledgement
leads to continued data out by Slave.
• Not-Acknowledge says “no more data from Slave”
• STOP leads to Master ceasing all communication

10/22/19 6.111 Fall 2019 27 10/22/19 6.111 Fall 2019 28

Implementing i2C on FPGA with State-Machine
MPU9250: Implementation of
• Made master i2C controller in Verilog i2C Master
• Continuously reads 2 bytes
• Used MPU9250 Data sheet: 42 pages (basic starting at the 0x3B register
(X accelerometer data)
functionality, timing requirements, etc…)
• Print out value in hex in LEDs
• MPU9250 Register Map: 55 pages • 34 States
• Clocked at 200kHz, and
creates 100 kHz SCL
• Change SDA on falling edge of
SCL
• Sample SDA on rising edge of
SCL

10/22/19 6.111 Fall 2019 29 10/22/19 6.111 Fall 2019 30

State-Machine
Implementation of i2C START1
Master
ACKNACK1A
STOP IDLE IDLE
ADDRESS1 READWRITE1

ACKNACK1C
NACK
7x
• Redundant states (repeated
READ/WRITE, ADDRESS, ACK/NACK, NACK ACK
READ3
etc…) ADDRESS2
ADDRESS3
8x
REGISTER1
ACK4
• ARM manual describes ~20 state READ4 7x
FSM for full I2C…this is just a toy 8x
implementation of specific I2C START2
operation
ADDRESS4
READ2 ACKNACK3A REGISTER2

• Included code on site for ACK

reference/starting point 8x
ACKNACK3C
READWRITE2 ACKNACK2C
READ1 ACKNACK2A
• Diagram: on next page for reference ACK
IDLE
…200 more lines NACK NACK
IDLE

10/22/19 6.111 Fall 2019 31 10/22/19 6.111 Fall 2019 32

 Communication Part Communication Part
VCC VCC

GND GND
SCL SCL

SDA MPU9250 SDA MPU9250

Nexys4 Nexys4

MA
ST E
Nexys4 Acknowledge=0 ReStart MPU9250

R AC
Write=0 Read=1 Acknowledge=0

K
Device Address (0x68) Device Address (0x68) Data Read In
Start Device Register (0x3B)
1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0
SDA
SDA
01010101010101010101010101010101010101110101010101010101010101010101010101010 … 01010101010101010101010101010101010101110101010101010101010101010101010101010 …
SCL
SCL

10/22/19 6.111 Fall 2019 33 10/22/19 6.111 Fall 2019 34

Communication Part Communication in Real-Life:

VCC Data being sent to MPU9250 Data being sent from MPU9250

GND
SCL

SDA MPU9250
Nexys4

SDA = Yellow

“I’m here. Sounds good” “OK” “Hey, 0x68…”

“Hey, 0x68…” “For sure”
”More, please”
“Different thought” “Read to me
“Look at your
“I wanna tell from where
0x6B register” “0x6D”
“I claim this bus” you something” you’re looking”

1 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 1 1 1 0 0 SCL = Purple
SDA

SCL
01010101010101010101010101010101010101110101010101010101010101010101010101010 …
Nexys4 (Master Device) Dialog MPU9250 (Slave Device) Dialog
Triggered on leaving IDLE state

10/22/19 6.111 Fall 2019 35 10/22/19 6.111 Fall 2019 36

Running and reading X acceleration: Clock-Stretching (Cool part of i2C!!!)
!
• Normally Master drives SCL, but since Master drives
SCL high by going hiZ, it leaves the option open for
Slave to step in and prevent SCL from going high by
pulling SCL LOW
Master wanted to pull SCL HI but slave
prevents by pull LOW
(red never happens)
HOOKUP

SCL:
Horizontal: Vertical:
16’hFD88 = 16’b1111_1101_1000_1000 (2’s complement) 16’h4088 = 16’b0100_0000_1000_1000 (2’s complement) Once Slave goes HiZ again, Master
Flip bits to get magnitude: 16’b0000_0010_0111_0111 Leave bits to get magnitude: 16’b0100_0000_1000_1000 picks back up on SCL
=-315 =+16520
Full-scale (default +/- 2g) Full-scale (default +/- 2g) • Allows Slave a way to buy time/slow down things (if it requires
-315/(2**15)*2g = -0.02g J makes sense -16520/(2**15)*2 = +1.01g J makes sense! multiple clock cycles to process incoming data and/or generate
output)

10/22/19 6.111 Fall 2019 37 10/22/19 6.111 Fall 2019 38

I2C Can Also Be a “Multi-Master” Bus I2s (Inter-IC Sound Bus)

Master Slave
SDA
• In SPI, there is a pre-determined device in charge WS
of the system. I2C is potentially much more • Not related to i2C at all SCL

democratic Master Releases Bus (STOP) • Intended for Digitized Stereo Data
By pulling SDA HI while SCL is HI
Master Claims Bus (START)
Idle State By pulling SDA LOW while SCL is HI • Three Wires:
SDA and SCL sit HI
• SDA: Serial Data (The actual music)
SDA: HI • WS: Word Select (Left/Right Channel)
• SCL: Serial Clock (For Synchronization)
LO
• Push-Pull Driving (like SPI…no need for pull-up resistors)
• Devices can be design to yield based on who claims a bus first…but • Data sent MSB first
you have to be careful…what if two devices claim a bus at the same
time…potential problems? Can get bus contention so need to be • Clock-rate dictated by sample rate (44.1kHz @16 bits per
careful channel /w 2 channels = ~1.4 MHz for example
10/22/19 6.111 Fall 2019 39 10/22/19 6.111 Fall 2019 40
i2S Implementation
• You’ve built a UART/serial module already…it was
pretty short/easy
• Vivado has IP cores for i2C Master and i2S Masters
• SPI is much more open to interpretation and loose
on its specs so no default core that I can find:
• I put some generic skeleton code on github/site with a
FIFO buffer that can get folks started if they need it.

10/22/19 6.111 Fall 2019 41 10/22/19 6.111 Fall 2019 42

Compare and Contrast? Which to Choose?

• Generally the fewer the wires the more rigid the • SPI is generally easier and more flexible to implement,
protocol but only certain devices use it since it takes up a lot of
pins (and pins are expensive/limited)
• SPI can be very flexible and high speed (have only • ”Slow” and “Fast” data rates are relative too…i2C is
10 bits to send? No problem…send 10!...can’t do not as much of a compromise now as it was fifteen
that do that with i2C…need to zero-pad up to the years ago, particularly with high-speed i2C (or even
next full byte (16 bits) now that 400 kHz rates are common)
• In terms of implementation, generally with • Remember, these are all meant for chip-to-chip
communication protocols, the more wires, the communications!
easier the protocol/less overhead • Check out the example i2C code from this lecture for
the IMU, and a generic SPI master I wrote up as
well…see if you can add clock-stretching! (not
required)
10/22/19 6.111 Fall 2019 43 10/22/19 6.111 Fall 2019 44
 • There’s lot of neat IP we can work
AXI Everywhere with….if you wanted to implement a
hardware accelerated Fast Fourier
Transform you totally can…

AXI

Module to Module AXI

Communication AXI

AXI
Talking Between Modules on the same Chip (Systems on a
Chip)

10/22/19 6.111 Fall 2019 45 10/22/19 6.111 Fall 2019 46

Advanced Microcontroller Bus Three General Flavors of AXI4

• AXI4 (Full AXI): For memory-mapped links.
Architecture (AMBA) Provides highest performance.
1. Address is supplied
• Version 1 released in 1996 by ARM 2. Then a data burst transfer of up to 256 data words
• 2003 saw release of Advanced eXtensible Interface • AXI4 Lite: A memory-mapped simplified link
(AXI3) supporting only one data transfer per connection
• 2011 saw release of AXI4 (no bursts). (also restricted to 32 bit addr/data)
1. Address is supplied
• There are no royalties affiliated with AMBA/AXI so 2. One data transfer
they’re used a lot. • AXI4 Stream: Meant for high-speed streaming data
• It is a general, flexible, and relatively free* • Can do burst transfers of unrestricted size
communication protocol for development • No addressing
• Meant to stream data from one device to another
quickly on its own direct connection
https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture
From the Zynq Book
10/22/19 6.111 Fall 2019 47 10/22/19 6.111 Fall 2019 48
Memory Map? AXI Idea
• Communication between two devices (Master and
• Memory mapped means an address is specified Slave) is carried out over multiple assigned
within the transaction by the master (read or “channels”
write). This corresponds to an address in the • Each channel has its own collection of wires which
system memory space. convey data, signals, etc.
• For AXI4-Lite, which supports a single data transfer • The channels can work somewhat independently,
per transaction, data is then written to, or read however in practice what one channel does is often
from, the specified address the result of what a different one did previously
• For Full-AXI4 sending a burst, the address specified • Five Types of Channels (may have all or a subset):
is for the first data word to be transferred, and the
• Read Address: ”AR” channel
slave must then calculate the addresses for the
data words that follow. • Read Data: “R” channel
• Write Address: “AW” channel
• AXI-Stream has no addressing so no memory • Write Data: “W” channel
mapping • Write Response: “B” channel
10/22/19 6.111 Fall 2019 49 10/22/19 6.111 Fall 2019 50

Read Wiring Write Wiring

Generalized collection of wires
“Channel”. Will contain numerous wires
depending on situation

Master initiates communication, Slave responds

10/22/19 6.111 Fall 2019 51 10/22/19 6.111 Fall 2019 52

 Within Each Channel are wires: AXI Clock
M S
• These wires serve specific purposes.
ACLK
• Some are universal to all channels, and others are From clock source
specific • Everything in system will run off of AXI clock usually
called ACLK in documentation
• No combinatorial paths between inputs and
outputs. Everything must be registered.
• All signals are sampled on rising edge
• AXI modules should also have Reset pins. AXI work
ACTIVE LOW so the Reset pin is usually called
ARSTn or ARESETn (meaning it is normally high)
10/22/19 6.111 Fall 2019 53 10/22/19 6.111 Fall 2019 54

Valid and Ready

<-STUFF->
Everything Else… VALID
M READY
S
VALID
M READY
S ACLK
From clock source
ACLK
From clock source • Everything else is information and depends on what is
needed in situation. Could be:
• All of AXI uses the same handshake procedure:
• Address
• The source of a data generates a VALID signal • Data
• The destination generates a READY signal • Other specialized wires like:
• STRB (used to specify which bytes in current data step are valid, sent
• Transfer of data only occurs when both are high by Master along with data payload to Slave)
• Both Master and Slave Devices can therefore • RESP (sort of like a status)
• LAST (sent to indicate the final data clock cycle of data in a burst)
control the flow of their data as needed
10/22/19 6.111 Fall 2019 55 10/22/19 6.111 Fall 2019 56
Each channel has its own subset of
“stuff” that goes along with those The Read Data Channel:
core signals shared by all
For example, the Write Data Channel (”W” channel)

Payload
Payload
Supplemental
Supplemental
Stuff
Stuff

CORE CORE

10/22/19 6.111 Fall 2019 57 10/22/19 6.111 Fall 2019 58

Read Address Chanel

Payload
Write Response

Payload

CORE

CORE

10/22/19 6.111 Fall 2019 59 10/22/19 6.111 Fall 2019 60

Write Address Channel

Generalized Transaction
Payload

• All Channel Interactions

follow same high-level
structure

Sending One ”beat” of data (one clock-cycle of data)

Keep in mind this could

be 64 parallel wires of
1’s and 0’s of info or 8
bytes for example…
Or it could be
something else

CORE
10/22/19 6.111 Fall 2019 61 10/22/19 6.111 Fall 2019 62

Generalized Transaction Generalized Transaction

• All Channel Interactions • All Channel Interactions
follow same high-level follow same high-level
structure structure
Sending One ”beat” of data (one clock-cycle of data) Sending One ”beat” of data (one clock-cycle of data)

Keep in mind this could Keep in mind this could

be 64 parallel wires of be 64 parallel wires of
1’s and 0’s of info or 8 1’s and 0’s of info or 8
bytes for example… bytes for example…
Or it could be Or it could be
something else something else

10/22/19 6.111 Fall 2019 63 10/22/19 6.111 Fall 2019 64

 And Up to All Five AXI channels
Other Things to Keep in Mind
can come from one device
• the VALID signal of the AXI interface sending • While operating independently at their individual
information must not be dependent on the READY transaction level, they can then report to the larger
signal of the AXI interface receiving that module to provide overall interfaces
information • Example:
• an AXI interface that is receiving information can • The slave device receives address on write channel
wait until it detects a VALID signal before it asserts address
its corresponding READY signal. • The write data channel then becomes active and knows
where to point incoming data
• Fail to Follow these rules and could have devices
• The response channel then opens and does its thing
wait infinitely.
• And so on
• Like when two people keep going “no, after you at a
door” • Hierarchy of Control/Design

10/22/19 6.111 Fall 2019 65 10/22/19 6.111 Fall 2019 66

And you Can Use AXI to Interface And you Can Use AXI to Interface
with Tons of things! with Tons of things!
Connecting a FIR (from a Xilinx IP) to the FFT module Creating a AXI-controlled joe6 module that I can then call from Python

10/22/19 6.111 Fall 2019 67 10/22/19 6.111 Fall 2019 68

And you Can Use AXI to Interface
with Tons of things! Complexity
A running-average hardware
accelerator Using AXI Stream for • In terms of wires and options, Full- Full-AXI4
DMA (Direct Memory Access)
AXI is the most complex

• AXI-LITE has a lot less options

(single data beat so all the AXI-LITE
supplemental stuff that specifies
burst characteristics gets skipped)

• AXI-STREAM has even AXI-STREAM

less…basically a high-speed write
channel (Few options), but often
needs that extra TLAST signal

10/22/19 6.111 Fall 2019 69 10/22/19 6.111 Fall 2019 70

Thi
s
s p e is th e
s u r c s h e e th in g
Others than AXI? Sources
p ri s t
ing /man right h
ly g u a l
o o d i s e re … t
!! he

• There are other generalized bus protocols out

• “AMBA® AXITM and ACETM Protocol Specification”, ARM 2011
there:
• “The Zynq Book”, L.H. Crockett, R.A. Elliot, M.A. Enderwitz, and R.W.
• Wishbone, some Open cores use this Stewart, University of Glasgow
• Avalon: used in some Altera sets (proprietary) • “Building Zynq Accelerators with Vivado High Level Synthesis” Xilinx
• AXI is a good one to be familiar with, not just Technical Note
because it is used in Xilinx stuff a lot • Some material from ECE699 Spring 2016
https://ece.gmu.edu/coursewebpages/ECE/ECE699_SW_HW/S16/

Crack open the AXI spec sheet with a few data

sheets for some Xilinx IP cores (like the CORDIC,
FFT, etc…) and you should be able to start making
sense of it.

10/22/19 6.111 Fall 2019 71 10/22/19 6.111 Fall 2019 72