Transistors and Logic

1) The “Digital” contract

A
2) Encoding bits
with voltages
3) Processing bits
with transistors
B 4) Gates
5) Large fanout gates
6) Truth-table SOP
Realizations
7) Multiplexer Logic

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 1

 Where Are We?
Things we know so far -
1) Computers process information
2) Information is measured in bits
3) Data can be represented as groups of bits
4) Computer instructions are encoded as bits
5) Computer instructions are just data

6) But, we don’t want to deal with bits…

So we invent ASSEMBLY Language
7) Even that is too low-level…
So we invent COMPILERs to generate
assembly code and assemblers to
generate the final bits …
But, how are all these bits PROCESSED?
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 2
 A Substrate for Computation
We can build devices for processing and representing bits
using almost any physical phenomenon
Wait! Those last ones
might have potential... neutrino flux
trained elephants
engraved stone tablets
orbits of planets
sequences of amino acids
polarization of a photon

1 1 0 1 0
0 1

1 0 1 0 0

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 3

 Using Electromagnetic Phenomena

Some EM things we could encode bits with:

voltages phase
currents frequency
With today’s technologies voltages are most often used.
Voltage pros:
easy generation, detection
voltage changes can be very fast
lots of engineering knowledge
Voltage cons:
easily affected by environment
DC connectivity required?
R & C effects slow things down

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 4

 Representing Information with Voltage

Representation of each point (x, y) on a B&W Picture:

0 volts: BLACK
1 volt: WHITE
0.37 volts: 37% Gray
etc.

Representation of a picture:
Scan points in some prescribed
raster order… generate voltage
waveform
How much information
at each point?

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 5

 Information Processing = Computation
First, let’s introduce some processing blocks:

v Copy v

v INV 1-v

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 6

 Let’s build a system!

Copy INV

input Copy INV

(In(Reality)
Theory)
Copy INV

Copy INV
?
output

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 7

 Why Did Our System Fail?
Why doesn’t reality match theory?
1. COPY Operator doesn’t work right
2. INVERSION Operator doesn’t work right
3. Theory is imperfect
4. Reality is imperfect
5. Our system architecture stinks

ANSWER: all of the above!

Noise and inaccuracy are inevitable; we can’t reliably
reproduce infinite information-- we must design our
system to tolerate some amount of error if it is to
process information reliably.
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 8
 The Key to System Design
A SYSTEM is a structure that is “guaranteed” to exhibit a
specified behavior, assuming all of its components obey
their specified behaviors.

How is this achieved? Through Contracts

Every system component will have clear obligations and
responsibilities. If these are maintained we have every
right to expect the system to behave as planned. If
contracts are violated all bets are off.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 9

 The Digital Panacea ...
Why DIGITAL?
… because it keeps the contracts SIMPLE!

It’s the price we pay for this robustness?

0 or 1

All the information that we transfer

between components is only 1 crummy bit!

But, in exchange, we get reliable, modular, and

reproducible systems.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 10

 The Digital Abstraction

“Ideal”
Abstract World
Real World
0/1
Manufacturing
Variations
Noise Bits

Volts or
Electrons or
Ergs or Gallons

Keep in mind, the world is not digital, we engineer it to behave that way.
We must use real physical phenomena to implement digital designs!

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 11

 A Digital Processing Element
• A combinational device is a circuit element that has
– one or more digital inputs
– one or more digital outputs
– a functional specification that details the value of each
Static output for every possible combination of valid input
Discipline values
– a timing specification consisting (at minimum) of an
upper bound propagation delay, tpd, on the required
time for the device to compute the specified valid
output values from an arbitrary set of stable, valid
input values
Output a “1” if at
input A least 2 out of 3 of
my inputs are a “1”.
input B Otherwise, output “0”.
output Y

input C I will generate a valid

output in no more than
2 minutes after
seeing valid inputs

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 12

 A Combinational Digital System
• A system of interconnected elements is
combinational if
– each circuit element is combinational
– every input is connected to exactly one output
or directly to some source of 0’s or 1’s
– the circuit contains no directed cycles

No feedback (yet!)

• But, in order to realize digital processing

elements we have one more requirement!

A definition for a VALID input

and a VALID output!`

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 13

 Valid = Noise Margins
! Key idea:
Don’t allow “0” to be mistaken for a “1” or vice versa
! Use the same “uniform bit-representation convention”,
for every component in our digital system
! To implement devices with high reliability, we outlaw
“close calls” via a representation convention which
forbids a range of voltages between “0” and “1”.
! Ensure the valid input range is more tolerant (larger)
than the valid output range
Our definition of valid does not preclude inputs and outputs from
passing through invalid values. In fact, they must, but only during
transitions. Our specifications allow for this (i.e. outputs are
specified sometime (Tpd) after after inputs become valid).

Invalid
Invalid Output
Input
Valid Valid
“0” Forbidden Zone “1”
Min Voltage volts
Max Voltage

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 14

 Digital Processing Elements
Some digital processing elements occur so frequently
that we give them special names and symbols

I will copy and I will output the

A restore my input Y A complement of Y
tobuffer
my output my input
inverter

A I will output a A I will output a

‘1’AND
if all my Y OR of my
‘1’ if any Y
B inputs are ‘1’ B inputs are ‘1’

A I will only output a

Q: What is the point of a buffer?

Y
Doesn’t a wire do the same thing?
‘1’ if an XOR
odd number A: A buffer restores marginal digital
B of my inputs are ‘1’ signals, because the output is as
good or “better” than the input (i.e.
it solves that bad image problem
from slide 7).

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 15

 Digital Processing Elements
Some digital processing elements occur so frequently
that we give them special names and symbols

A Y A Y
buffer inverter

A A
AND Y OR Y
B B

A In honor of the richest

XOR Y man in the world we will

B henceforth refer to
digital processing
elements as “GATES”

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 16

 From What Do We Make Digital Devices?
• A controllable switch is the
This symbol
common link of all computing indicates a “high”
technologies potential, or the
voltage of the
• How do you control voltages power supply

Load
with a switch?
• By creating and opening
paths between higher and
lower potentials

This symbol
indicates a
“low” or
ground
potential

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 17

 N-Channel Field-Effect Transistors (NFETs)

D D + When the gate

voltage is high,
the switch
G G VDS ≥ 0 closes. Good
+
at pulling
S - S - things “low”.
Operating regions: VGS
0.8V
cut-off: IDS
VGS < VTH S D
linear saturation
linear:
VGS ≥ VTH S “ “ D VGS
VDS < VDsat
VGS - VTH

saturation:
VGS ≥ VTH VDS
VDS ≥ VDsat S D

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 18

 P-Channel Field-Effect Transistors (PFETs)

D D - When the gate

voltage is low,
the switch
G G VDS ≤ 0 closes. Good
+
at pulling
S - S + things “high”.
Operating regions: VGS
–0.8V
cut-off:
VGS > VTH S D -VDS

linear:
VGS ≤ VTH -VGS
VDS > VDsat
S “ “ D
VGS - VTH

saturation: saturation linear

VGS ≤ VTH
VDS ≤ VDsat S D
-IDS

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 19

 Finally… Using Transistors to
Build Logic Gates!
We’ll use
VDD Logic Gate recipe: PFETs here

pullup: make this connection

when VIN is near 0 so that VOUT = VDD

VIN VOUT

pulldown: make this connection

when VIN is near VDD so that VOUT = 0
and, NFETs
here

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 20

 CMOS Inverter
“0” “1”
Vout
Valid “1”

Vin Vout Invalid

“1” “0”
Valid “0”
Vin
Valid “0” Valid “1”

Only a narrow range

of input voltages result in
“invalid” output values.

A Y
This diagram is greatly
exaggerated (The invalid
inverter input region is actually
MUCH smaller)!

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 21

 “Digital” Transistor Abstraction
• Transistors are extremely flexible, but fickled analog devices.
• If we limit how we use them, (i.e. adopt conventions), they
can act as robust digital devices.
• Which we can treat as a simple switch abstraction.
N-channel FET,
P-channel FET,
a 3-input device
a 3-input device
D Convention: The D terminal of a P-FET
*will* be connected to either the supply D
(the voltage representing “1”) or the S
terminal of another P-FET

G Convention: The S terminal of an N-FET

*will* be connected to either ground or
G
the D terminal of another N-FET
S
S

“1” G D “0” G D
“0” G D “1” G D
P-FET S P-FET S
N-FET S N-FET S

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 22

 Complementary Pullups and Pulldowns
This is what the “C”
in CMOS stands for!
We design components with complementary pullup and
pulldown logic (i.e., the pulldown should be “on” when the
pullup is “off” and vice versa).
pullup pulldown F(A1,…,An)
on off driven “1”
off on driven “0”
on on driven “X”
off off no connection

Since there’s plenty of capacitance on output nodes, so when the

output becomes disconnected it tends to “remember” its previous
voltage– at least for a while. The “memory” is the load capacitor’s
charge. Leakage currents will cause eventual decay of the charge
(that’s why DRAMs need to be refreshed!).
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 23
 CMOS Complements
What a nice
VOH you have...

Thanks. It runs A A
in the family...

conducts when A is high conducts when A is low

A
Series N connections: A B
B Parallel P connections:

conducts when A is high conducts when A is low

and B is high: A.B or B is low: A+B = A.B

A
A B
B
Parallel N connections: Series P connections:

conducts when A is high conducts when A is low

or B is high: A+B and B is low: A.B = A+B
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 24
 A Two Input Logic Gate

What function does

this gate compute?

A B C
A 0 0
0 1
B 1 0
1 1

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 25

 Here’s Another…

B
What function does
this gate compute?

A B C
0 0
0 1
A
1 0
1 1

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 26

 General CMOS Gate Recipe

Step 1. Figure out pulldown network that A

does what you want (i.e the set of
conditions where the output is ‘0’) B C
e.g., F = A*(B+C)

Step 2. Walk the hierarchy replacing nfets

with pfets, series subnets with parallel B
A
subnets, and parallel subnets with series C
subnets
But isn’t it
hard to wire
B it all up?
Step 3. Combine pfet pullup network A
C
from Step 2 with nfet pulldown
network from Step 1 to form fully A
-complementary CMOS gate.
B C

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 27

 One Last Exercise
Lets construct a gate to compute:
F = A+BC = NOT(OR(A,AND(B,C))) Vdd
A

Step 1: The pull-down network B C

Step 2: The complementary pull-up
F
network
A B

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 28

 One Last Exercise
Lets construct a gate to compute:
F = A+BC = NOT(OR(A,AND(B,C)))
Vdd
A
A B C F Step 1: The pull-down network
0 0 0 1 Step 2: The complementary pull-up B C
0 0 1 1 F
network
A B
0 1 0 1 Step 3: Combine and Verify
0 1 1 0 C
1 0 0 0 OBSERVATION: CMOS gates tend
1 0 1 0 to be inverting! Precisely, one or
more “0” inputs are necessary to
1 1 0 0 generate a “1” output, and one or
1 1 1 0 more “1” inputs are necessary to
generate a “0” output. Why?

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 29

 Now We’re Ready to Design Stuff!
We need to start somewhere –
usually with a functional specification
Argh… I’m tired of word games
A
If C is 1 then
Y
B copy B to Y,
otherwise copy
Truth Table
C A to Y

If you are like most pragmatists you’d rather be given a

table or formula than solve a puzzle to understand a
function. The fact is, any combinational function can
be expressed as a table.

“Truth tables” are a concise description of the

combinational system’s function, where an output is
specified for *every* input combination.

Conversely, any computation performed by a

combinational system can expressed as a truth table.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 30

 Where Do We Start?
We want to build a computer!

A
What do we do?
Thus far, we
B
have a few gates?
(AND, OR, which we haven’t made yet.
An Inverter, and those funky CMOS
things that we have made.)
Logic
Gates

We need
… a systematic approach for designing logic

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 31

 A Slight Diversion
Are we sure we have all the gates we need?
How many two-input gates are there?
AND OR NAND NOR

SURGE
Hum… all of these have 2-inputs (no surprise)
… 2 inputs have 4 permutations, giving 22 output cases
24
How many permutations of 4 outputs are there? ___
2N
Generalizing, there are 2 , N-input gates!
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 32
 Show me the Gates!
How many of
these gates
can be
There are only 16 possible 2-input gates implemented
using a single
… some we know already, others are just silly CMOS gate?

Do we need all of these gates?

Nope. We can describe them all using only AND, OR, and NOT.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 33

 But, we can compose gates using others

B>A XOR
A
B
Y

The TRICK is to OR
A y A
the ANDs of all
Y input combinations
B B that generate an
output of “1”. You
don’t need the OR
gate if only one input
combination results
How many different gates do we really need? in a “1”.

We can always do it with 3 different You need Inverters to

handle input
types of gates, and sometimes with 2, combinations
involving “0”s, ANDs,
but, can we use fewer? and ORs.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 34

 One Will Do!
A UNIVERSAL gate is one that can be used to implement
*ANY* COMBINATIONAL FUNCTION. There are many

NANDs and NORs are UNIVERSAL UNIVERSAL gates, but not all gates are UNIVERSAL.
Q: What is a COMBINATIONAL FUNCTION?
A: Any function that can be written as a
truth table.

= =
= =
= =
Ah!, but what if we want more than 2-inputs

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 35

 Stupid Gate Tricks

Suppose we have some 2-input XOR gates: A B C

0 0 0
tpd = 1 nS 0 1 1
1 0 1
1 1 0
And we want an N-input XOR: output = 1
iff number of 1s
input is ODD
(“PARITY”)

tpd = N nS -- WORST CASE.

Can we compute N-input XOR faster?

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 36

 I Think That I Shall Never See
a Gate Lovely as a ...

log2N 22 21
2
log N ) levels...
N-input TREE has O( ______
log N ) gate delays.
Signal propagation takes O( _______

EVERY N-Input Combinational function be implemented

using only 2-input gates? But, its handy to have
gates with more than 2-inputs if needed.

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 37

 Our first Design Approach
1) Write out our functional spec as a
Truth Table
truth table
2) Write down a Boolean expression for
every ‘1’ in the output
An “ideal”
gate might

Y = C B A + C BA + CBA + CBA have any

number of
inputs, and
might not
be directly
realizable as
3) Wire up the ideal gates, replace them a single
CMOS gate.
with equivalent realizable gates, call
€ it a day, and go home!
-it’s systematic!
-it works!
This approach will always give us logic
-it’s easy!
-we get to go home!
expressions in a particular form:
SUM-OF-PRODUCTS
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 38
 Straightforward Synthesis
We can implement
SUM-OF-PRODUCTS A
B
with just three levels of C

logic. A
B
C
Y

INVERTERS/AND/OR A
B
C

A
B
C

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 39

 Other Useful Gate Structures
AB=A+B “Pushing Bubbles”
NAND-NAND
C C

A A

B
Y
≡ B
Y

DeMorgan’s Laws
xyz = x + y + z
AB=A+B
NOR-NOR
C C
A € A

B
Y
≡ B
Y

x + y = xy
Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 40
 More Useful Gate Structures
Vdd

AOI (AND-OR-INVERT)
A
A AOI and OAI
C
B
C
D
Y
≡ D
Y structures can
be realized as a
single CMOS
B gate. However,
their function is
OAI (OR-AND-INVERT) equivalent to 3
Vdd levels of logic.

A A
B
Y
C B
An OAI’s DeMorgan
equivalent is usually
easier to think about.
D

A
≡ C
Y

B
Y D
C
D

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 41

 An Interesting 3-Input Gate
Based on C, select the A or B input to be
copied to the output Y. Truth Table

A
If C is 1 then
Y
B copy B to Y,
otherwise copy
C A to Y

2-input Multiplexer
B
A 0

C Y B 1
Gate
A
symbol
C
schematic

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 42

 MUX Compositions and Shortcuts

A 4-bit wide
2-input Mux
A 4-input Mux
A0 0
(implemented as 0 Y0
B0 11
a tree) S

I0 A1
0
0 0
0 Y1
I1 11S B1 11S
0 Y
A 0
0 A0-3
I2 11S B 1 Y A2 0 Y0-3
0
0 C 2 0 B0-3
I3 B2 11 Y2
11S 3
D S

S S
A3
0
0 Y3
S0 S1 B3 1
1S

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 43

 Mux Function Synthesis

Mux Logic:
Consider implementation of some arbitrary
Combinational function, F(A,B,C) An example of
“structured” logic
... using a MULTIPLEXER synthesis
as the only circuit element:
0 0
0 1
0 2
1 3 Y
0 4
1 5
1 6
1 7
A,B,C

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 44

 Small Improvements
We can apply certain optimizations to MUX Function synthesis

There’s
Desired Logic - Largely by something
Function interesting
inspection or going on
in those
exhaustive search MUXes

0 0
C 1 Y
C 2
1 3

A,B - N-input gate

with N-1
input MUX &
one inverter

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 45

 Next Time
Binary Arithmetic
Circuits that:
ADD
SUBTRACT
SHIFT

Comp 411 – Fall 2015 9/22/15 L10 – Transistors and Logic 46