Data Representation Boolean Algebra and Logic Circuit Minimisation Sequential Circuits & Flip-Flops Circuits with Feedback

Sequential Circuits & Flip-Flops Circuits with Feedback Registers Connecting up the 4 Function Shift Register
Sign & Magnitude : 𝐴 + (𝐴 ⋅ 𝐵) = 𝐴 Karnaugh Map RS Flip-Flop (One-bit memory of Q) State Register – n FF stores unsigned int ≤ 2^n
- Leftmost bit: sign of the integer Distributive: 𝐴 + (𝐵 ⋅ 𝐶) = (𝐴 + 𝐵) ⋅ (𝐴 + 𝐶) 3-input, 2 bits on top header Parallel Data
- −(2^{𝑛 − 1} − 1)\le(2^{𝑛 − 1} − 1) (A·B·C..·X)’ = A’ + B’ + C’ + ..+ X’ (pb Induction) - Data reg. with say 32 FF has a common clock, and
- Simple for humans to understand Dual form: replace AND/OR 00->11, 01->10, 10->01, 11-> Hold/Oscillate all 32 bits set at the same time
- 2 representations for 0 NAND is complete (universal gate) - Comms, serial data used in which the bits of a 32
- Costly to implement (cmp & sub) bit word are sent one after the other
One’s Complement Serial to Parallel Conversion (4 bit eg)
- -ve are complement of +ve
- Less intuitive, Less costly, fiddly Circles have power of 2
- Carry out adjustment Horizontal & vertical edge circles
Two’s Complement Add A’ at end of A+B for NOR If inputs never occur, use Don’t Care
- -ve: invert bit and add 1 X can either be 1 or 0
- −2^{𝑛 − 1}\le2^{𝑛 − 1} − 1 (+): smaller & faster than PGA & orig.
- 1 bit pattern for zero If control, it goes on LHS column Parallel to Serial Conversion
- Asymmetric – extra negative val Programmable Gate Arrays 1. Load parallel data on to D-type FF Computer Arithmetic
- Sorting is difficult Synthesize using Minterm/Maxterms 2. Shift data out in serial form Single Bit Addition:
Excess-n (Bias n) 2 Function Shift Register: 𝑆𝑈𝑀 = 𝐴′ ⋅ 𝐵 + 𝐴 ⋅ 𝐵′ = 𝐴 ⊕ 𝐵, 𝐶𝐴𝑅𝑅𝑌 = 𝐴 ⋅ 𝐵
2-Bit counter Example XNOR = A’ . B’ + A . B
- 0..0 smallest and move up 00 avoided, 11: output cant change 4 states: 0 (00), 1 (01), 2 (10), 3(11) Half Adder
Binary-Coded Decimal (BCD) XOR 10: Q=1, 01: Q=0 Registers: Ordered G of 1b DQ FF
- Each decimal digit = fixed # bits For n input, 2^n in. values, 4^n n in. gates Types of Circuits Reg. Transfer Op: 𝑅𝑑𝑒𝑠𝑡𝑖𝑛𝑎𝑡𝑖𝑜𝑛 ← 𝑅𝑠𝑜𝑢𝑟𝑐𝑒
- Easy for humans, more space Combinatorial: Combination of inputs
Unicode Sequential: Combination of inputs and
- defined chars like ASCII (127 first) previous outputs
Binary Arithmetic MPX: (+): Prototype des. quickly & efficient - Asynchronous: Output has correct value
Minuend – Subtrahend = result (-): specific patterns, no optimisation of speed or after an undefined amount of T, i.e. no clock
Full Adder:
Dividend=quot x divisor + rem circuit size - Synchronous: Output has correct value 4 Function Shift Register Add binary numbers longer than 1 bit
2C (+/-): Disregard Carry-Out Optimisation and Testing after defined time, i.e. clock signal 00 Hold, 01 Shift R, 10 Shift L, 11 Parallel Load 𝑆 = 𝐴 ⊕ 𝐵 ⊕ 𝐶, 𝐶𝑜𝑢𝑡 = 𝐶 ⋅ (𝐴 ⊕ 𝐵) + 𝐴 ⋅ 𝐵
2C(*): SIZE: INVERTER: 3, NAND/NOR: 4, AND/OR: 6, D-Type Latch
2 bit binary to unary converter (decoder)
−𝑌 = 2𝑛 − 𝑌, 𝑋 ∗ 𝑌 = 22𝑛 − 𝑋𝑌 XOR/XNOR: 8 D=0-> S=0,R=1; 1-> 10 -> Q=1
Systematic Testing: 3-Bit Controlled Counter
Floating Point Numbers - Large range of inputs & observe behaviour. Sim.
Binary fractions: 0.01=2^{-2} Combinatorial Circuit Design before manufacture, real tests after.
1.375 1 0.75 1 1 1 Combinational: v on RHS not on LHS (!cycle) (-) too many combinations Selecting Source Register
0.6875 = = + = + + Canonical form:
2 2 4 2 8 16 Formal Techniques To deal with X, make smallest circuit then check that Done by MPX – one for each bit of register n-bit Adder w C (ripple thru carry adder)
𝑁1 ∗ 𝑁2 = (𝑀1 ∗ 10𝐸1 ) ∗ (𝑀2 ∗ 10𝐸2 ) - used in automated design & analysis of circuit - Abstraction, simulation equivalence, bounded the final circuit works in all cases
= (𝑀1 ∗ 𝑀2 ) ∗ (10𝐸1+𝐸2 ) - obtained from TT, Boolean eq. and circuits model checking
𝑁1 + 𝑁2 = (𝑀1 ∗ 10 ) + (𝑀2 ∗ 10𝐸2 )
𝐸1
Minterm: conj. of each RHS v or its negation 10:0100,11:0001
(-) hard to reason abt all poss. behave.
= (𝑀1 + 𝑀2 ∗ 10𝐸2−𝐸1 ) ∗ (10𝐸1 ) Can. MinT form: unsimplified DNF 4 way MPX with Decoder
5.29 x 10² = 5.2 x 10² trunc, biased - 1 in TT, conjunct of variables Time-Dependent Behaviour
= 5.3 x 10² rounding, unbiased err Can. MaxT form: unsimplified CNF Switch and Delay (LHS)
Overflow: infinity or exception - 0 in TT, disjunct of negation of variables
Underflow: zero or exception Augmentation: 𝑩 ⋅ 𝑪 = (𝑨 + 𝑨′) ⋅ 𝑩 ⋅ 𝑪
Cmp: a = b : (b – e) < a < (b + e)
Conversion from IEEE
IEEE Floating Point Standard 8 Registers: 8-to-1 multiplexers
IEEE: institute of electrical & electronic Limitations:
engineers R-C (RHS) - Value on Q = D at instant at which latch ->
(+): Widely adopted -> predictable results Resistance-Capacitance (analogue) goes from 1 to 0
independent of arch Noise Margin: Thresholds (1.7V-0.5V) - When latch is 1, any change on D causes
Defines: Format, Semantics, Error Fan-out: Decreases noise tolerance & speed change of Q
Clock Dividers:
Single Precision Format (32-b): of response Edge Triggering
Serial Adder
Adapt: val D -> Q @ falling edge of C
Add binary numbers in serial form
Bits arrive with LSB first
Addition
E.g. +1. 𝐹 ∗ 2𝐸−127 - Exponents must be the same – shift smaller
Normal bit (1.) omitted from significant exponent by shifting significant accordingly (must
field -> hidden bit restore hidden bit) Crystal produces waveform 1MHz, 10^6 falling edges
24 bits, ~ 7 decimal digit precision i.e. Shift smaller sig. right by E_l – E_s Dividing by 10^6 requires 20 D-Q flip flops
Special values Master-slave (falling edge)
±10 38
≤ ±10 −38
,0 Divide by 256 Loading to Destination Register
SPR:
Stored as Excess numbers Rload = combined R of all gates - Clock pulse must be applied to dest. Reg. 1-Bit Full Subtractor
e.g. 8-bit E-127, 128 = 1111 1111 For fan-out n, 𝑅𝑙𝑜𝑎𝑑 = 𝑅𝑙𝑜𝑎𝑑
1
/𝑛 - No pulse applied to any other register
Double Precision Format (64-b): Where R^1_load is load of single gate - Demultiplexer used to switch a clock pulse on
𝐶𝑙𝑜𝑎𝑑 = 𝑛 ∗ 𝐶𝑙 Spike Definition: one out of eight lines
Time to switch is 𝑛 ∗ 𝑡𝑑 Momentary Ripple Through Counter 2-to-4 Demultiplexer (decoder)
Analysis using Variable Resistance Model wrong state if D
Rising Edge-Trig. FF with Preset & Clear
E.g. +1. 𝐹 ∗ 2𝐸−1023 to be stored
53 bits ~ 16 decimal digits prec. arrives a little
- All 0 exp. Used for zero & denormalised
±10308 ≤ ±10−308 , 0 - All 1 exp. For infinites and NaN later than clock
SP when memory scare or debugging - Therefore range for normalised numbers educed pulse & if prev.
calculations since rounding errors show from -127..128 to -126..127 value of Q = new !synchronous, correct state only present for short T
up quickly - Denormalised = values between underflow limit and Use with care, only when no time critical functionality
Conversion to IEEE zero, i.e. for SP ±0. 𝐹 ∗ 2−126 Divide by any number
Two’s Complement Subtractor
Convert to binary, then normalise - Allows for more gradual shift to zero - Design counter to the next higher power of 2
e.g. 42.6875 = 1.010101011 ∗ 25 - Add clear when cnt is divisor
Significant field: Synchronous Digital Systems Count to 5
State changes occur at exact Times by clock. Sequential Circuit Design Methodology Comlete Register Transfer Circuit
- 0101 0101 1000 0000 0000 0000
Exponent Field: General form of Synchronous digital circuit 1. Determine # of states required
- 5 + 127 = 132: 1000 0100 Invalid digital value 1.2V 2. Determine State Transitions
+ve: Sign = 0 3. Choose way to represent states
Infinites and NaNs FSM 4. State Sequencing Logic to Boolean equations and
- Infinites: > overflow limits and div by 0 (+) specifying exactly what a circuit does minimise using Karnaugh
- Nan: no real mathematical interpretation (+) apply des. methods on FSM, create circuit 5. Output logic as Boolean Eq & minimise
All Synchronous can be modelled by FSM
- NaN result: quiet, exception signalling Transition Diag.: Multiplication
Moore: state/output 𝑎1 𝑎0 × 𝑏1 𝑏0 = (𝑎1 ⋅ 𝑏1 ) ⇐ 2 + (𝑎0 ⋅ 𝑏1 ) ⇐
FSM General Form: Isomorphic Assignments 1 + (𝑎1 ⋅ 𝑏0 ) ⇐ 1 + 𝑎0 ⋅ 𝑏0
Mealy Machine: This demultiplexer is a minterm generator 2 bit multiplier circuit (unsigned)
D-Type

T-Type f – state sequencing/input logic | g – output logic State Allocation

Moore: more robust (I spikes blocked) - States that have the same next state for the same
input -> adjacent state assignments
- Next states of state produced by applying adjacent
J-K FF input conditions -> adjacent state assignments
Comparators RAM Fetch Cycle Architecture & Instructions E.g. exchange R0 & R1 Output Logic: determines c0-c14, f0-f4, s0-s8
1 bit comparator: One-Bit Static RAM (D-type FF) Get next program instr. & load to IR Speed things up:
′
𝐴 > 𝐵: 𝐴 ⋅ 𝐵 ′ , 𝐴 < 𝐵: 𝐴′ ⋅ 𝐵, 𝐴 = 𝐵: ((𝐴 > 𝐵) + (𝐴 < 𝐵)) , no A<B Unique address (binary number) MAR ← PC - 32 bit buses instead of 8 (4x per cycle)
2 AND gates determine read/written MDR ← RAM[MAR] , PC ← PC+1 - local registers for partial results
Read=1, clock supressed, Q->Output IR ← MDR - Controller with minimum exec. Cycles
Read=0, FF receives clock pulse and is Incrementer for PC made of Half Adders - Remove carry by doing arithm. on big ints
CMAR=F1+E1+E2 (simplified)
loaded in from the data in line Register Transfers: - Replace bi-directional data bus with
1. MPX set to connection paths “data in” & “data out” buses for memory
4 bit comparator (1 bit scaled up) 2. Regs to be loaded must be given a signal on Simplify as we only load MDR on the cycle before we use it
their clock inputs, by interrupting system clock, , CIR = F2
using NAND 𝑪𝑴𝒆𝒎𝒐𝒓𝒚 = 𝑬𝟐 ⋅ 𝑺𝑻𝑶𝑹𝑬 + 𝑬𝟑 ⋅ 𝑺𝑻𝑶𝑹𝑬𝑰𝑵𝑫𝑰𝑹𝑬𝑪𝑻
Carried out by controller (synchronous
sequential circuit)

4 bit multiplier circuit (unsigned) 4-function Shifter Manual Processor Controller 𝑪𝑩 = 𝑬𝟐; 𝑪𝑪 = 𝑬𝟑 ⋅ (𝑶𝑵𝑬 + 𝑻𝑾𝑶)
Instruction Format for IR

S/A: reg A MPX Asymmetric Circuit: (Static RAM)

S/C: 0 – logic 1, 1 – Cout - For reading: combinatorial circuit
00 Hold, 01 SL w/ C, 10 ASR, 11 Rotate right S/R: result: 0 – shifter, 1 – ALU - Writing: sequential circuit (address & data
1 MPX per bit F/ALU-SHIFT – determines func present & correct when clock pulse sets FF)
E.g. A+B in ALUout, when data is next to be RAM is 2D
L Shift + Carry:
Add-subtract circuit loaded into reg A, IR0=0, IR2=1, so path R0…R6 can be manipulated by programmer, rest belongs to hardware designers.
from ALUout to reg A input established Program Instructions: Bit Mask
Arithm R Shift: software: Few & powerful Turns 20-bit Address
Instruction takes 5 steps: hardware: simple and few clock pulses to 32-but number by
Rotate Right: 1. Load “Data in” to IR register (opcode 1) Controller Circuit for Fetch Cycle masking top bits Ind. Reg sel:
Manually place bits using MPX 2. Load A register
8-function Shifter 3. Load B and C registers
4. Load “Data in” to IR register (opcode 2)
5. Load RES and C registers
To ensure start at Step 1: <-31, 24,23,20,19,0
Manual Processor
Processor: instr. + operand = res
Types: CPU, GPU, Array, Manual Indirect: L/S/J/C-INDIRECT Reg1, Reg2: 31-24,23-20,19-16, 15-0 unused (=2R)
8-bit Processor Architecture von Neumann 45 8 bit ALU 2R intrnl: Move,add,subtract,and,or,xor,compare Rdest,Rscr,31-24,23-20,19-16
1R: Clear,INC,DEC,COMP,ASL,ASR,ROR Rdest, RETURN: 31-24,23-20
0R: SKIPPOSITIVE,SKIPNEGATIVE,SKIP,NOP: 31-24
Input/Output using LOAD/STORE, Truth table for sequencing logic: Arithmetic Function Selectors
peripherals can be read/written to as if memory, & connected to M
-1-bit memory cell only enabled when both
row & col lines = 1 Clock Control to Regs
I/O Ports: busses - For 256 bit RAM, decoder: 4bit binary to 16
E.g. R = (A+B)/2, A+B < 256 Dynamic RAM (DRAM)
bit unary so max 1 cell Large RAMs (>1Mbit chips), no DQ
1. first # set up on input lines and stored in reg A n bit address bus: 2^n addresses F4=ASR+ROR; F3=ASL+ROR
2. second # … stored in reg B 1 transistor & capacitor for each bit
decoders: n/2 – to – 2^(n/2)
3. Circuits to add A to B Capacitor charged = 1
Connecting RAM to Processor
4. sum back to reg A Capacitor uncharged = 0
Memory Address Register (MAR)
5. Shifting circuit for 1 bit right - Stores add. In M to be stored/read
6. Result loaded onto reg Res Store is not permanent and all the cells
Memory Data Register (MDR)
ALU (two 4-bit operations) Carry: storing 1s drift to 0 in a fraction of a second
- a.k.a. Memory Buffer Reg (MBR)
This is a standard sequential circuit Restore capacitor charge regularly
- stores data read from M, and sometimes
TT and then K-map Map Refreshing capacitor charges done when
data to be written in M
Output Logic: computer is not accessing the memory
+ fast RAM is low powered & cannot be After using K-maps
Memory controller myst tell the DRAM to
connected to large number of processor regs
refresh itself periodically
Program Counter (PC)
- the address of next program instr. Controller Specification ALU C: as that is the only
Using NAND gate ensures no race hazard Final circuit for State Sequencing logic
Instruction Register (IR) place that a 1 carry is required
F/alu=011 & F/cy=1: A+B+1 Data input: falling, load reg: rising
ALU adders + subtractors - program inst. being executed
Why not have 0,1 as MPX inputs To find mean of A,B: 2 execution cycles
TSB can be enabled when writing, blocking
e.g. 16 bit, use the carry from the lSByte 0: OPERATE (OP) input to 0
when reading. For 256x1b RAM, 8 TSB (2^8)
result when computing the MSByte result 1: Data In lines to x000xxx1 & OP to 1
Bi-directional Data Buses - instr -> IR, ALUout & Cout=0, MPXA=1
2: Data In lines to number A

input to controller
after COMPARE executed, then used as
Compare used by SKIP: carry reg updated
SKIP in COMPARE
Tri-State Buffer:
If C =0, output follows input 3: Data In lines to number B (0 into C) F: Fetch, E: exec.
If C=1, output neither 0 nor 1 but disconnected 4: Data In lines to x011x11x F: Get a 32bit instruction from memory
-ins->IR,ALUo=A+B, MPXres=1,MPXC=1,C=0 E: processor carry out that instr.
5: - (A+B) -> RES, C indicates overflow) Fetch Register Transfers:
2nd Execution Cycle MDR only reg connected to memory out bus
1: Data In lines to x011x110 F1: MAR <- PC; PC <- PC+1
- ins->IR,ALUo=A+B,MPXres=1,MPXA=0 F2: MDR <- Memory
2: - (ALUout loaded into reg A) F3: IR <- MDR
3: - (ALU/Cout -> C, B irrelevant) After F3, instruction in both IR and MDR
4: Data In lines to x110x0xx F1,F2,F3,E4 unconditional
Only 1 has C=0 - ins->IR,SFTR=ARS,MPXres=0 8-bit opcode to Instruction
Use demultiplexer for that. 5: - (A+B/2 -> RES). Then OP=0

Improvement: for INC,DEC,CMP, B loaded from main bus, A from

programmer’s reg. Another MPX could allow both at the same time
Decoder to determine which state we are in

into A first, shift in 1 cycle

Data path through shifter without loading
parallel
Fast addition hardware, more bits in
Optimise combination logic, less delay
Other Improvements:
Function MPX X check: C=0, unused -> F(0) (000), and C=1, E2 (110)

Register Selector
Cout MPX: Ri() <- Cout(), rest 0 MPX selection bits:
Instruction Improvement Some instructions have exactly the same sequence of reg transfers
Bottom 16 bits mostly empty, pack up
instructions on byte boundaries + MPX
hardware to load IR correctly
E.g. RETURN,SHIFTS,MOVE & JUMPINDIRECT require 2 execute
Additional Arithmetic Hardware
cycles. So the condition for returning from state E2 to F1:
Incrementer, decrementer, 16b mult.
Data Paths Internal Bus Selector
More MPX to reduce instruction cycles,
MPX to select input to B indep. of A: 3-2 Bus selection bits S6,S5,S4
Path from reg. to internal bus -1 cycle Processor part 1 PC to Bus