Combinational Logic Circuits

➢ It is a logic circuits that contain no

memory

Sequential Logic Circuits

➢ It is a logic circuits that contain

memory (ability to store information)
including flip-flops.

Adders

➢ A combinational circuit that performs

addition of binary numbers.

Half-Adder

➢ It is a combinational circuit that Subtractors

performs the addition of two bits.
➢ A combinational circuit that performs
➢ The input variables designate the
subtraction of binary numbers.
augend and addend bits.
➢ The output variables produce the sum Half-Subtractor
and carry.
➢ A combinational circuit that performs
the subtraction of two bits.
➢ The input variables designate the
subtrahend and minuend bits.

Full-Adder

➢ It is a combinational circuit that

performs the addition of three bits.
➢ The input variables designate the
Full-Subtractor
augend, addend and the other (usually a
carry from previous bits addition) bits. ➢ A combinational circuit that performs
a subtraction between two bits, considering
that a 1 may have been borrowed by a lower
significant stage.
 ➢ This circuit has 3 inputs and 2 outputs. ➢ Binary adder may also be
implemented using full adders with initial
carry C0 set to 0 and with its output carry
connected to the input carry of the next full
adder in chain.

Ripple Carry Adder

➢ The carry output of each full-adder is

connected to the carry input of the next
Binary Parallel-Adder
higher-order stage (a stage is one full
➢ It is a digital circuit that produces the adder).
arithmetic sum of binary numbers in parallel. ➢ The sum and the output carry of any
➢ It consists of half-adder that adds the stage cannot be produced until the input
least significant bit of augend and addend carry occurs; this causes a time delay in the
and its output carry is connected to the input addition process.
carry of the next full adder.
➢ Consider two binary numbers: A=1101
and B=1001.
➢ When a pair of bits are added through
a full adder, the circuit produces a carry to be
used with the pair of bits, one significant
position higher.
Look-Ahead Carry Adder

➢ The speed of the addition operation

depends on the time required for the carries
to propagate.
➢ The principle of carry look ahead
solves this problem by calculating the carry
in advance based on the inputs.
➢ It anticipates the output carry of each
stage.
➢ This method is based on two functions
of the full-adder: Carry Generate (Gi) and
Carry Propagate (Pi).
Binary Parallel-Subtractor

➢ It is a digital circuit that produces the

arithmetic difference of the binary numbers
in parallel.
➢ It is consisting of half-subtractor that
subtracts the least significant bit of minuend
and subtrahend, and its output borrow (BN) is 2-Bit Magnitude Comparator
connected to the input borrow (BP) of the next
full-subtractor.

➢ Binary subtractor may also be

implemented using full subtractor with initial
borrow (BP0) set to 0 and with its output
borrow (BN) connected to the input borrow
(BP) of the next full adder in chain.

3-Bit Magnitude Comparator

Magnitude Comparator

➢ A combinational circuit that compares

two numbers A and B, determines their
relative magnitude.

It has 3 outputs:
 ➢ If the n-bit decoded information has
unused or don’t care combinations, the
decoder output will have less than 2n outputs.
➢ The decoders are often referred to as n
to m line decoders where m ≤ 2n. Their
purpose is to generate the 2n (or less)
minterms of n-input variables.

2 x 4 Decoder (Active High)

Combinational Logic Implementation

➢ Any Boolean function can be

expressed in sum-of-minterms.
➢ Use a decoder to generate the
minterms and an external OR gate to form
the sum.

Decoder

➢ Converts binary information from n

input lines to a maximum of 2n unique output
lines
2 x 4 Decoder with Enable Input

➢ Enable inputs are used to control the

circuit operation. It would act like a switch
that dictates when a decoder would function
and when not to.

Two problems encountered with the previous

implementation:

1. An output with all 0’s is generated when

all the inputs are 0’s, which is also the output
when D0 is equal to 1.

2. If two inputs are active simultaneously,

the output produces an undefined
combination.

Priority Encoder

2 x 4 Decoder with Enable Input (Active-Low)

➢ It solves the problem encountered in

the previous implementation.
➢ It includes the priority function.
➢ The input having the highest priority
will take precedence.
➢ This can be done by including a valid
output indicator in the implementation. This is
set to 0 if all inputs are 0.

Multiplexer

➢ Multiplexing means transmitting a

Encoder large number of information units over a

➢ An encoder is a digital function that smaller number of channels or lines.

produces a reverse operation from that of a ➢ Multiplexer is a combinational circuit

decoder. An encoder has 2n (or less) m-input that selects binary information from one of

lines and an n output line. many input lines and directs it to a single

➢ Has 2n input lines and n output lines. output line.

➢ The selection of particular input lines is
controlled by a set of select lines. Normally,
there are 2n input lines, n selection lines
whose bit combinations determine which
input is selected.
 ➢ Also known as “data selector”. ➢ Create an implementation table based
on the variable not used as select line.
➢ Inspect each column of the
implementation table

❑ If the minterms in a column are not circled,

apply 0 to the corresponding MUX input.

❑ If the minterms are circled, apply 1 to the

corresponding MUX input.

❑ If the top minterm is circled and the

bottom minterm is not circled, apply A’ to
the corresponding MUX input.

4 x 1 Multiplexer Circuit ❑ If the top minterm is not circled and the

bottom minterm is circled, apply A to the
corresponding MUX input.

Demultiplexer

➢ It is a circuit that receives information

on a single line and transmits this information
to one of 2n possible output lines.
➢ The selection of a specific output is
controlled by the bit values of n selection
lines.
➢ It is also known as “data distributor”.

Boolean Implementation using Multiplexer

➢ Choose your select lines (n-1) from

your input variables. Any of the input
variables.
➢ Determine the size of the multiplexer
Depends on the number of select lines.
Sequential Logic Circuits ➢ Storage elements that operate with
signal levels rather than signal transitions are
➢ Consists of a combinational circuit to
referred to as latches while those controlled
which memory elements are connected to
by a clock transition are flip-flops.
form a feedback path.
➢ Latches are said to be level sensitive
➢ Receives binary information from
devices while flip-flops are edge-sensitive
external inputs together with the present
devices.
state of the memory elements to determine
➢ The two types of storage elements are
the binary value at the output terminals.
related because latches are the basic circuits
from which all flip-flops are constructed.

SR Latch NOR Version

Types of Sequential Logic Circuits

Synchronous Sequential Logic Circuit

➢ A system whose behavior can be
defined from the knowledge of its signals at
discrete instants of time.
➢ Synchronization is achieved by a
timing device called a clock generator, which
provides a clock signal having the form of a
periodic train of clock pulses.

Asynchronous Sequential Logic Circuit

➢ Depends upon the input signals at any

instant of time and the order in which the
inputs change. SR Latch NAND Version

Latches and Flip-Flops

Latches

➢ It is a sequential device that watches

all of its inputs continuously and changes its
outputs at any time, independent of a
clocking signal.

Flip-Flops

➢ It is a sequential device that normally

samples its input and changes its outputs
only at times determined by a clocking
signal.
Flip-Flops

➢ A device with two stable states.

➢ It can maintain a binary state
indefinitely until directed by an input signal to
switch states.
➢ It remains in one of these states until
triggered into the other.

SR FLIP FLOP
T Flip-flop

➢ It is a single-input version of the JK

Flip-Flop.

D Flip-flop
Preset and Clear
➢ One way to eliminate the undesirable
indeterminate state in the RS flip flop is to ➢ In a flip-flop, "preset" and "clear" are

ensure that inputs S and R are never 1 asynchronous inputs that allow you to set or

simultaneously. reset the flip-flop's output state regardless of

➢ This is done in the D latch. the clock signal.

➢ Two external inputs that initiate the
condition or state of the flip-flop.
➢ Priority inputs.
➢ Preset: When active, the preset input
forces the flip-flop to its set state, where Q=1
and Q'=0, regardless of the clock or other
inputs.
➢ Clear: When active, the clear input
JK Flip-flop forces the flip-flop to its reset state, where
Q=0 and Q'=1, regardless of the clock or other
A JK Flip-Flop is a refinement of the RS Flip-
inputs.
flop in that the indeterminate state of the RS
➢ These asynchronous inputs are useful
type is defined in the JK type.
for initializing flip-flops or resetting them to a
Inputs J and K behave like inputs S and R to known state when needed, and they are often
set and clear the flip-flop, respectively. used when multiple flip-flops are ganged
together to form a larger circuit.
The input marked J is for set and the input
marked K is for reset.
 ❑ Slave Flip-flop:

• This flip-flop is triggered by the inverted

clock signal and captures the data output
from the master flipflop when the clock signal
transitions from high to low (falling edge).

Propagation Delay Time (tP)

• This represents the amount of time it takes

for the output of a gate or flip-flop to change
states

Setup Time (tSETUP)

• It is the minimum length of time the data bit

must be present before the CLK edge hits

Hold Time (tHOLD)

• It is the minimum length of time the data bit

must be present after the CLK edge has
struck

Master-Slave Flip-Flop

In flip-flops, "master" and "slave" refer to a

configuration using two flip-flops to improve
performance and reliability.

❑ The master flip-flop captures the input

data on the rising edge of the clock signal,
while the slave flip-flop captures the output
of the master on the falling edge of the clock
signal.

❑ This arrangement helps to avoid race

conditions and allows for stable data transfer,
ensuring the output is reliable.

❑ Master Flip-flop:

• This flip-flop is triggered by the external

clock pulse and stores the input data when
the clock signal transitions from low to high
(rising edge).