The digital circuits are divided into two broad categories:

1. Combinational Circuits
2. Sequential Circuits
The logic circuits in which the outputs at any time instant depends upon
the inputs present at that time instant are said to be combinational.
These circuits does not have any memory(ability to store information).In
these circuits there will be no feedback from output to input.

In sequential circuits, the outputs at any time instant depends upon the
input at that time instant as well as previous inputs/outputs.
These logic circuits have feedback from output to input. These circuits
have storing elements called flip-flops to store the past information.
Therefore these circuits are said to have memory.
Combinational Logic Circuits

• When Logic Gates are connected together to produce a specified output for certain
specified combination of input variables, with no storage involved , the resulting circuit is
called combinational logic circuit.
• In Combinational Logic Circuits, the output variables are all time depends on combination
of input variables.
• A Combinational Circuit consist of Input variables, Logic Gates & Output Variables.
• The Logic Gates accepts signal from the input variable and generate output signals.
Block Diagram of Combinational Logic Circuit
TYPES OF COMBINATIONAL
CIRCUITS
Design a combinational Logic Circuit with three input variables
that will produce a logic 1 output when more than one input
variable are logic 1
DESIGN OF ADDERS (HALF ADDER AND FULL ADDER)

• Design of Adders

0+0 =0 • The Simple addition consist of four possible elementary operations.

0+1 =1
1+0=1
• The First 3 Operations Produces Sum.
1+1= 10 • Last Operation Performed sum in two digits. Higher Significant result is Called Carry & Lower
Significant bit is Called Sum.
(1+1=
Sum 0,
Carry 1)
HALF ADDER
• Half adder is a combinational logic circuit with two inputs and two outputs.

• The half adder circuit is designed to add two single bit binary number A and B.

• It is the basic building block for addition of two single bit numbers. This circuit has two
outputs carry and sum.
HALF ADDER
FULL ADDER
•The full adder is a three input and two output
combinational circuit.
FULL ADDER
Full Adder
Implementation of Full Adder
Circuit using two Half Adders
Subtractor
Implementation of Full Subtractor Circuit using two Half Subtractors
MAGNITUDE COMPARATORS

Single Bit Magnitude Comparator

•comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit
comparator. It consists of two inputs for allowing two single bit numbers and three outputs to generate
less than, equal and greater than comparison outputs.
•The figure below shows the block diagram of a single bit magnitude comparator. This comparator
compares the two bits and produces one of the 3 outputs as L (A<B), E (A=B) and G (A>B).
Truth Table
Two Bit Magnitude
Comparator
• A 2-bit comparator compares two binary numbers, each of two bits and produces their
relation such as one number is equal or greater than or less than the other. The figure below
shows the block diagram of a two-bit comparator which has four inputs and three outputs.

• The first number A is designated as A = A1A0 and the second number is designated as B =
B1B0. This comparator produces three outputs as G (G = 1 if A>B), E (E = 1, if A = B)
and L (L = 1 if A<B).
Application of Comparators

•These are used in the address decoding circuitry in computers and microprocessor based devices to select

a specific input/output device for the storage of data.

•These are used in control applications in which the binary numbers representing physical variables such

as temperature, position, etc. are compared with a reference value. Then the outputs from the comparator

are used to drive the actuators so as to make the physical variables closest to the set or reference value.

•Process controllers

•Servo-motor control
MULTIPLEXER (MUX)
• Multiplexer is a digital circuit that has multiple inputs and a single
output.
• It is also known as Data Selector.

• The Section of particular input line is controlled by set of Selection

lines.

• Normally there are 2𝑛 Input lines and n Selection Lines Whose bit
combination determines which input is selected.
• Therefore Multiplexer is ‘Many to One’ and it provide digital
equivalent of an analog selector switch.
 2𝑛 Input Lines
n Selection Lines
TYPES OF MULIPLEXERS

2 :1 1 Output
Mux Line

4 :1
Mux
8:1
Mux
DEMULTIPLEXER (DEMUX)

• Demultiplexer is a digital circuit that has multiple Outputs and a single

Input.
• It is also known as Data Distributor.
• The Section of particular Output line is controlled by set of
Selection lines.

• Normally there are 2𝑛 Output lines and n Selection Lines whose bit
combination determines which input is selected.
• Therefore demultiplexer is ‘One to Many’.
TYPES OF DEMULIPLEXER
S
1 :2 Mux
n Selection Lines
1 :4 Mux
1 : 8 Mux 2𝑛 Output Lines

1 Input Line
 DECODER AND ENCODER
DECODER
• Decoder is a Multiple Input , Multiple Output logic circuit which
converts coded inputs to coded outputs, where the input and
output are different
• Decoder consist of n input and 2𝑛 Maximum Possible Outputs
• Decoders also have enable inputs to activate decoded outputs based
on data inputs.
 Binary Decoder ( 2 to 4 Decoder)
Examples

Inputs Outputs
ENABLE A B Y3 Y2 Y1 Y0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0
 3 to 8 Decoder

Inputs Outputs
ENABLE A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
ENCODER
• Encoder is a digital circuit which perform inverse operation of Decoder.
• Decoder is a Multiple Input , Multiple Output logic circuit which converts coded inputs to coded outputs, where
the input and output are different.
• Decoder consist of n Outputs and 2𝑛 Maximum Possible Inputs.
8 TO 3 ENCODER ( OCTAL TO BINARY)

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
 PRIORITY ENCODER

In the normal encoder circuits, there are certain drawbacks. They are when the output is zero, there is the
ambiguity that whether it corresponds to one input as zero or all inputs as zeroes.
The encoder may produce incorrect output when the two inputs are high.
To overcome the above drawbacks, priority encoders are used, in which the output will be based on the priority
of the inputs.
A Priority encoder is one of the type of encoders in which an ordering is imposed to the inputs that means
compared with the standard encoder, it includes the priority function.

• However, this priority is based on the relative magnitudes of the inputs. Hence, the input with larger
magnitude is the one that is encoded first.

• Priority encoders can select the inputs with highest priority in many practical applications.
This Priority encoder consists of 4 inputs and three outputs.
Although an encoder has 2n inputs and n outputs, it has a third output ‘V’ which is a valid bit indicator and is
set to one when one or more inputs are active or equal to 1.
The output of a priority encoder is
always the index of the highest-priority
active input.
If multiple inputs are active at the same
priority level, the encoder typically
outputs the index of the highest-
numbered active input.
Priority encoders are commonly used in
applications like multiplexing, data
selection, and priority interrupt systems.
 BCD ADDER

• BCD adder must be able to operate in accordance with above steps

• 1) Add two bit BCD Code Groups , using straight binary addition
• 2) Determine if the sum of addition is greater than 1001 (Decimal 9); If it is , add 0110
(Decimal 6) to this sum and generate a carry to the next decimal position
• The first requirement is easily met by using a 4 bit binary parallel adder

• The sum output S4 S3 S2 S1 S0 can range anywhere from 00000 to 10010

The Circuitry for a BCD adder must include the logic needed to detect whenever the sum is greater
than 01001, so that correction can be added in
 PARALLEL
ADDER
• A single full adder performs the addition of two one bit numbers and an input carry.
• But a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary
numbers that is greater than one bit in length by operating on corresponding pairs of bits in
parallel.
• It consists of full adders connected in a chain where the output carry from each full adder
is connected to the carry input of the next higher order full adder in the chain.
• A n bit parallel adder requires n full adders to perform the operation.
• So for the two-bit number, two adders are needed while for four bit number, four adders are
needed and so on. Parallel adders normally incorporate carry lookahead logic to ensure that
carry propagation between subsequent stages of addition does not limit addition speed.
PARALLEL ADDER
 CARRY LOOK AHEAD
ADDER
•A carry-Lookahead adder is a fast parallel adder as it reduces
the propagation delay by more complex hardware, hence it
is costlier. In this design, the carry logic over fixed groups of
bits of the adder is reduced to two-level logic.

•This method makes use of logic gates so as to look at the

lower order bits of the augend and addend to see whether a
higher order carry is to be generated or not.

•Carry-Lookahead Adder Ics A typical carry-Lookahead

generator IC is 74182 which accept four pairs of active low
carry propagate (as P0, P1, P2 and P3) and carry generate
(Go, G1, G2 and G3) signals and an active high input (Cn).
 CARRY LOOK AHEAD
ADDER
Consider the full adder circuit with corresponding truth table. If we define two variables
as carry generate Gi and carry propagate Pi then,
Pi = Ai ⊕ Bi Gi = Ai Bi
The sum output and carry output can be expressed as
Si = Pi ⊕ Ci
C i +1 = Gi + Pi Ci
•A and B: The two input bits to be added.
•Ci: The carry-in bit from the previous stage of the adder.
•Ci+1: The carry-out bit to be propagated to the next stage.
•Condition: The condition under which a carry is generated or
propagated.
The truth table shows the following conditions:
•No carry generate: When neither A nor B is 1, or when A and B
are both 1 but Ci is 0, no carry is generated (Ci+1 = 0).
•No carry propagate: When A and B are both 0 and Ci is 1, the
carry is propagated to the next stage (Ci+1 = 1) without
generating a new carry.
•Carry generate: When A and B are both 1, a carry is generated
regardless of the value of Ci (Ci+1 = 1).