BTECH (SEM III) THEORY EXAMINATION 2024-25 COMPUTER

ORGANIZATION AND ARCHITECTURE BCS302

SECTION A

a. Basic Functional Units of a Digital System:

1. Input Unit
2. Output Unit
3. Memory Unit
4. Arithmetic and Logic Unit (ALU)
5. Control Unit
6. Registers
7. System Bus

b. General-Purpose Registers: These are registers within the CPU used to temporarily store data and addresses during
execution. Examples include AX, BX, CX, DX in x86 architecture.

c. Floating Point Representation: It represents real numbers using scientific notation in binary. A floating-point number
has three parts:

Sign bit (1 bit)

Exponent (biased)
Mantissa (normalized fraction)

d. Role of ALU: The Arithmetic and Logic Unit performs arithmetic operations (add, subtract) and logic operations (AND,
OR, NOT, XOR). It's the core computational unit of the CPU.

e. Micro-operations: These are low-level operations executed on data stored in registers such as:
Transfer operations (MOV)
Arithmetic operations (ADD, SUB) Logic
operations (AND, OR)
Shift operations (SHL, SHR)

f. Purpose of ROM Memories: ROM stores firmware or permanent data essential for booting up and hardware
initialization. Data in ROM is non-volatile and cannot be modified during normal operation.

g. Peripheral Devices: Examples include:

Keyboard
Mouse Printer Scanner
Hard Disk Monitor
USB Devices

Section B
2a. Data Transfer Process: Data transfers in a digital system occur through:

Registers: Temporary storage

Bus: Pathways (data, control, address)
Memory: Stores data and programs

Read Operation: Address is placed on address bus, control line set to read, data fetched into the CPU.

Write Operation: Data placed on data bus, address on address bus, control line set to write.
positive and negative numbers efficiently by encoding sequences of 1s and minimizing the number of
additions/subtractions. Advantages:

Reduces the number of operations

2c. Horizontal vs Vertical Microprogramming:

Horizontal Microprogramming: Wide control word; each bit controls one micro- operation.
o Fast execution
o Complex control unit
Vertical Microprogramming: Compact control word; encoded micro-operations.
o Slower
o Simpler, more memory-efficient

2d. Auxiliary Memories:

Magnetic Disk: Random access, used in HDDs
Magnetic Tape: Sequential access, used for backups
Optical Disk: CDs, DVDs; read via lasers Used for long-term data storage, cost- effective, and slower
than main memory.

2e. I/O Ports: I/O ports allow data transfer between CPU and external devices.

Functions: Data buffering, signal conversion, and communication.

Types: Parallel, serial
Enable data exchange and device control.

Q3a. Detailed Overview of Processor Organization

A processor (CPU) performs various operations in a systematic manner. Its organization includes:

1. Instruction Fetch (IF):

o The processor fetches the instruction from memory using the Program Counter (PC) which holds the
address of the next instruction.
o Fetched instruction is placed in the Instruction Register (IR).
2. Instruction Decode (ID):
o The control unit decodes the instruction to understand the operation and operands.
o It determines whether the instruction is arithmetic, logical, data transfer, or control.
3. Execute Cycle (EX):
o ALU or other execution units perform the required task.
o If the operation is arithmetic or logical, ALU is engaged.
o If it is memory access, address calculation is done, followed by a memory read/write.
4. Pipelining:
o Technique to improve CPU throughput by overlapping instruction phases.
o E.g., while one instruction is being decoded, another is fetched.
o Common pipeline stages: IF, ID, EX, MEM, WB
o Increases instruction throughput without increasing clock speed.
5. Parallel Processing:
o Uses multiple processors or cores to execute instructions simultaneously.
o Types:
SISD Single Instruction, Single Data
SIMD Single Instruction, Multiple Data (e.g., GPUs)
MISD Rarely used
MIMD Multiple Instruction, Multiple Data (e.g., multicore CPUs)
 o Enhances performance for multitasking and large computations.
3B. Instruction Cycle
The instruction cycle is the sequence of steps a CPU follows to fetch, decode, and execute an instruction. Every program is
a sequence of instructions, and the CPU repeatedly performs the instruction cycle to process them.

The four main phases of the instruction cycle are:

1. Fetch
Purpose: To get the next instruction from memory.
Process:
o The Program Counter (PC) holds the memory address of the instruction to be executed.
o This address is sent to memory through the Address Bus.
o The instruction is fetched into the Instruction Register (IR).
o PC is incremented to point to the next instruction.

2. Decode
Purpose: To interpret the fetched instruction.
Process:
o The Control Unit decodes the binary instruction stored in the IR.
o It identifies the opcode (operation to perform) and operand (data or address).
o It activates the necessary circuits or control signals.

3. Execute
Purpose: To perform the actual operation specified by the instruction.
Process:
o If it's an arithmetic instruction, the ALU performs the operation.
o If it's a data transfer, the data is moved between CPU and memory or I/O.
o If it's a control instruction, the PC may be modified.

4. Memory or Write-back (if needed)

Some instructions may require storing the result back in memory or in a register. Control signals
ensure the result is written to the correct location.

Instruction Format

An instruction format defines the layout of bits in an instruction. It typically includes:

1. Opcode: Specifies the operation (e.g., ADD, SUB)

2. Operand(s): Address or data to be processed
3. Mode Bits: (Optional) Specifies the addressing mode
Opcode: Operation code (e.g., 00001010 for ADD)
Source Register: Register holding operand
Destination Register: Where the result is stored
Address/Immediate: Memory address or immediate value

Types of Instruction Formats:

1. Zero-address: Uses stack (e.g., PUSH, POP)

2. One-address: Accumulator-based
3. Two-address: Uses two operands
4. Three-address: Most flexible, three operand fields

Q4a. Look-Ahead Carry Adders vs Ripple Carry Adders Look-Ahead Carry

Adder (LCA):
 Speeds up binary addition by precomputing carry signals using generate (G) and propagate (P) logic.
Carry for each bit is calculated in parallel.

Key Terms:
Generate (G): G = A·B
Propagate (P): P = A B

Formula:

C1 = G0 + P0·C0
C2 = G1 + P1·C1 = G1 + P1·(G0 + P0·C0)
Comparison with Ripple Carry Adder (RCA): Feature RCA
LCA
Carry Propagation Sequential Parallel Speed Slow
Fast Circuit Complexity Simple
Complex Gate Count Fewer
More Advantages of LCA:

Faster for large bit adders

Reduces delay due to carry propagation

Disadvantages:

More hardware
Costlier and power-consuming

4B. A stack is a special type of memory data structure that follows the Last In, First Out (LIFO) principle. The most
recently added (pushed) data is the first to be removed (popped).

In computer organization, stack organization refers to a system where a set of operations is performed using stack-based
memory. Instead of using general-purpose registers or memory addresses for temporary storage, computations are done on a
stack.

Characteristics of Stack Organization:

LIFO principle: Last element inserted is the first to be accessed. Used for:
o Arithmetic expression evaluation
o Subroutine call handling (return address, parameters)
o Interrupt handling
Operates using:
o PUSH: Add data to the top of the stack
o POP: Remove data from the top
Stack in Expression Evaluation

One of the most powerful uses of a stack is in evaluating arithmetic expressions, especially when written in postfix
(Reverse Polish Notation).
Types of Arithmetic Expressions:

1. Infix Notation (common): A + B

Operators are between operands. Requires parentheses and operator precedence rules.
2. Postfix Notation: A B +
Operator follows operands. No need for parentheses or precedence rules.

Steps for Evaluating Postfix Expression Using Stack:

n example postfix expression:

532*+
Which is equivalent to: 5 + (3 × 2) = 11

Step-by-step:

Step Symbol Action Stack

1 5 Push 5

2 3 Push 53

3 2 Push 532

4 * 56

5 + 11

Final Result: 11

Stack Organization in Processor

Some processors use stack-based architecture, especially older or simpler CPUs (e.g., HP 3000, Java Virtual Machine).
Features include:

Implicit use of the top of the stack for operations. Instructions like:
o PUSH operand
o POP operand
o ADD, SUB, MUL act on top two stack elements

Advantages of Stack-Based Evaluation:

Eliminates the need for parentheses in expressions Easier
parsing and evaluation logic
Simplifies code generation in compilers
Natural fit for recursive function call handling

5a. A basic computer is a simple model of a stored-program computer architecture used for teaching purposes. It includes
the core elements required for executing instructions: memory, CPU, input/output, and control units.

This design demonstrates how a computer executes instructions and manages data flow.

Components of a Basic Computer

The basic computer consists of the following main units:

1. Memory Unit

Stores both data and instructions.

Memory words are typically 16 bits wide.
Addressed using a Memory Address Register (AR). Data is
transferred using the Data Register (DR).

2. Processor Unit (CPU)

Includes several registers and an Arithmetic Logic Unit (ALU): Register Purpose
AR (Address Register) Holds address for memory access

PC (Program Counter) Points to next instruction

DR (Data Register) Holds data from or to memory

Register Purpose

AC (Accumulator) Main register for ALU operations

IR (Instruction Register) Holds the current instruction

TR (Temporary Register) Holds temporary intermediate data

INPR/OUTR Input and output registers

The ALU performs arithmetic and logic operations, primarily using the AC.

3. Control Unit

Decodes the opcode of an instruction in the IR.

Generates control signals to coordinate all CPU and memory operations. Manages the fetch-
decode-execute cycle.

4. Input/Output System

INPR receives 8-bit input from external devices.

OUTR holds data to be sent to an output device.
Controlled by Input Flag (FGI) and Output Flag (FGO).

Block Diagram of a Basic Computer

Working of the Basic Computer

1. Fetch: PC sends address to memory; instruction loaded into IR.
2. Decode: Control unit decodes opcode and addressing mode.
3. Execute: Operation performed using AC, DR, and memory.
4. Store: Results may be stored in AC or written to memory.

Q5b. Microprogram Sequencing

Definition: Microprogram sequencing involves executing complex instructions by breaking them into a series of simpler
microinstructions stored in control memory.

Components:

1. Control Memory: Stores microinstructions

2. Control Address Register (CAR): Holds address of the next microinstruction
3. Control Data Register (CDR): Holds the microinstruction being executed
 4. Sequencer: Determines the address of the next instruction based on current conditions
Microinstruction Fields:

Control signals for ALU, memory, I/O Next address

field (for sequencing)

Types of Sequencing:

Fixed sequencing: Next address is incremented by 1

Conditional branching: Based on flags or opcode
Mapping: Opcode maps directly to microinstruction address

Benefits:
Easier to modify control logic
Simpler design and debugging
Allows complex instructions with simpler hardware

Q6a. Memory Hierarchy Design

Concept: A layered structure of memory with trade-offs in speed, cost, and size.
Levels:

1. Registers: Fastest, smallest, located in CPU.

2. Cache Memory:
o L1: Closest to CPU, fastest cache
o L2/L3: Larger, slightly slower
3. Main Memory (RAM): DRAM used for currently executing programs.
4. Secondary Storage: HDDs, SSDs large, slower, persistent
5. Tertiary Storage: Optical Disks, Tapes archival

Characteristics:

Level Speed Cost/bit Capacity Registers

Fastest High Low Cache Very
Fast High Medium Main Memory Fast Moderate High
HDD/SSD Slow Low Very High Tape/CD
Very Slow Very Low Massive

Principle of Locality:

Temporal: Recently accessed data is likely to be used again

Spatial: Nearby data is likely to be used soon

This hierarchy ensures performance and efficiency while managing cost.

6B. Associative Memory, also called Content Addressable Memory (CAM), is a type of memory where data is accessed
based on content rather than specific addresses. Unlike conventional RAM (where data is retrieved by address), in
associative memory, you provide a part of the data, and the memory returns the full word (or indicates a match).

Key Features of Associative Memory:

Content-based access: Search is based on data content, not address.
Parallel searching: All memory words are compared simultaneously, offering fast retrieval.
Commonly used in:
o Caches
o TLBs (Translation Lookaside Buffers)
o Networking (MAC address tables)
 Structure of Associative Memory
Associative memory consists of the following major components:

1. Memory Array: Stores data words.

2. Key Register: Holds the data (or part of it) that is to be searched.
3. Mask Register: Determines which bits in the key are relevant (used in partial matches).
4. Match Logic: Compares key with stored words.
5. Match Register: Indicates which memory locations matched the search.

Advantages of Associative Memory:

Extremely fast lookup and retrieval
Supports partial matches (with mask bits)
Ideal for high-speed searching applications (e.g., CPU cache, TLB)

Disadvantages:

Complex and expensive hardware

More power consumption due to parallel search logic Less scalable
for large memory sizes

Q7a. Role of Peripheral Devices and I/O Interaction

Peripheral Devices: External hardware used for input, output, and storage. Examples:

Input: Keyboard, Mouse, Scanner Output: Monitor,

Printer
Storage: USB, Hard Drives

Role in System:
Enable interaction between user and computer Provide data
to CPU and receive output

I/O Interfaces:

1. Ports:
o Serial (e.g., USB)
o Parallel
2. I/O Controllers:
o Handle communication between CPU and device
Communication Techniques:

1. Programmed I/O: CPU actively checks device status

2. Interrupt-driven I/O: Device sends interrupt to CPU
3. DMA (Direct Memory Access): Device transfers data directly to/from memory, bypassing CPU
Importance:

Facilitates efficient data exchange Offloads CPU from direct

I/O handling Enhances overall system throughput

7B.

An interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. It
temporarily halts the current execution, saves the processor state, and transfers control to a predefined service routine
(Interrupt Service Routine or ISR).

Interrupts enable efficient and real-time handling of asynchronous events without polling.
 Types of Interrupts
Interrupts are mainly classified into two broad categories:

1. Hardware Interrupts

These are generated by external devices to notify the CPU of an event.

a. Maskable Interrupt
Can be ignored or disabled by the CPU using a mask bit. Used for
routine tasks like I/O operations.
Example: Keyboard input interrupt.

b. Non-Maskable Interrupt (NMI)

Cannot be disabled.
Used for critical events like hardware failure or power loss. Example: Memory parity
error, power failure.
2. Software Interrupts

These are triggered by executing specific instructions in the program.

Used to switch to supervisor mode for system calls. Also helpful

in debugging or exception handling.

Example:
In x86 assembly, INT 21h is used for DOS function calls.

3. Internal or Trap Interrupts (Exception)

Caused by internal conditions during instruction execution. Generated

automatically by the processor.

Common types:

Divide by zero
Invalid opcode
Overflow or underflow

These are also sometimes called traps or exceptions.

4. Vectored vs Non-Vectored Interrupts Vectored

Interrupt
The address of the ISR is predefined or provided by the interrupting device. Faster and more
organized.
Example: ARM processors.
Non-Vectored Interrupt

CPU must determine the ISR address manually or by polling. More flexible but slower.
5. Priority Interrupts

When multiple interrupts occur, priority mechanisms are used to decide which to serve first.

a. Daisy-Chaining
Devices connected in a chain; priority is determined by position.

b. Polling
CPU asks each device in sequence to find which raised the interrupt.

Comparison Table

Type Source Maskable Examples

Hardware External device Yes/No Keyboard, Disk, Power Failure Software

Program code N/A System calls, INT in x86 Internal/Trap CPU
execution No Divide by zero, Overflow Vectored Device-defined Yes Interrupt
table based
Non-Vectored CPU-decided Yes Older microprocessors