ALVA’S INSTITUTE OF ENGINEERING &

TECHNOLOGY
A Unit of Alva’s Education Foundation (R)
(Affiliated to Visvesvaraya Technological University, Belagavi.
Approved by AICTE, New Delhi & Recognized by Government of Karnataka)
Shobhavana Campus, Mijar, Moodbidri- 574 225, Mangalore, D.K., Karnataka State.
Phone: 08258-262724 (O), 262725(P), Telefax: 08258-262726
Email: [email protected], web: www.aiet.org.in
(Accredited by NBA and NAAC with A+) (ECE & CSE)

Department of Electronics & Communication Engineering

Integrated Circuits Laboratory

BECL305

B.E – III Semester

LaB Manual 2025-26

NAME:………………………………………………………….

USN:………………………………………………………….…

SEM / SECTION:……………………..BATCH NO.:………....

Prepared by

Department of Electronics & Communication

Engineering
 Alva’s Institute of Engineering & Technology

Vision of the Institute

“Transformative education by pursuing excellence in engineering and Management through

enhancing skills to meet the evolving needs of the community”

Mission of the Institute

 To bestow quality technical education to imbibe knowledge, creativity and ethos to

students’ community.
 To include the best engineering practices through transformative education.
 To develop a knowledgeable individual for a dynamic industrial scenario.
 To include research, entrepreneurial skills and human values in order to cater the
needs of the society.

Vision of the Department

Centre of Excellence to empower young minds in the field of Electronics and

Communication Engineering with research focus and skill development through
Transformative Education catering to the needs of Society.

Mission of the Department

 To create a unique learning environment to enable the students for their excellence.
 To empower the students with necessary skills for solving the Technological
Problems.
 To promote R&D activities among teaching learning group to meet the requirements
of industry and academia.
 By Imbibing the Students with Human Values and Ethics through Transformative
Education and make them Socially Responsible Professionals.
 PROGRAMME OUTCOMES

Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering

1.
specialization to the solution of complex engineering problems.

Identify, formulate, review research literature, and analyze complex engineering problems
2. reaching substantiated conclusions using first principles of mathematics, natural sciences, and
engineering sciences.

Design solutions for complex engineering problems and design system components or
3. processes that meet the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.

Use research-based knowledge and research methods including design of experiments, analysis
4.
and interpretation of data, and synthesis of the information to provide valid conclusions.

Create, select, and apply appropriate techniques, resources, and modern engineering and IT
5. tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.

Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal
6. and cultural issues and the consequent responsibilities relevant to the professional engineering
practice.

Understand the impact of the professional engineering solutions in societal and environmental
7.
contexts, and demonstrate the knowledge of, and need for sustainable development.

Apply ethical principles and commit to professional ethics and responsibilities and norms of the
8.
engineering practice.

Function effectively as an individual, and as a member or leader in diverse teams, and in

9.
multidisciplinary settings.

Communicate effectively on complex engineering activities with the engineering community

10 and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.

Demonstrate knowledge and understanding of the engineering and management principles and
11. apply these to one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.

Recognize the need for, and have the preparation and ability to engage in independent and life-
12.
long learning in the broadest context of technological change.
 PROGRAM EDUCATIONAL OBJECTIVES

The graduates of Electronics & Communication Engineering will be able to

PEO1: Apply Mathematical, Scientific and Engineering skills for solving problems in
the areas of Electronics and Communication Engineering.

PEO2: Expose to Emerging Technologies and excel in Industries/higher studies/

research.

PEO3: Apply analytical skills in the areas of Electronics and Communication

Engineering to become competent and Employable.

PEO4: Inculcate Professional ethics, human values, team work for solving
Engineering problems and contribute to societal needs.

PROGRAM SPECIFIC OUTCOMES

PSO 1: Understand and apply the principles of Electronics and Communication

Engineering in various domains of Analog and Digital systems.

PSO 2: Design and implement systems using the concepts of Electronics, Signal
Processing, Embedded Systems and Semiconductor technology.

PSO 3: Apply modern Hardware & Software tools to analyze and solve engineering
problems.
 COURSE OUTCOMES

Students will be able to:

1. Design and test Op-amp circuits for Adder, Integrator, Differentiator, Comparator and
ADC.
2. Design and test multivibrator circuits using 555
3. Design and test the combinational logic circuits for the given specifications.
4. Test the sequential logic circuits for the given functionality
5. Demonstrate the performance of active filters

CO’s – PO’s – PSO’s Mapping

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

BECL305.1 3 2 3 2 3 2 2 2 3 3

BECL305.2 3 2 3 2 3 2 2 3 3

BECL305.3 3 2 3 2 3 2 2 2 2 3 3

BECL305.4 3 2 2 3 2 2 2 2 3

BECL305.5 2 2 2 3 2 2 2 3

SUM 14 12 13 6 15 4 10 4 10 10 15
AVG
2.75 2 2.6 2 3 2 2 2 2 2 3
Attainment
 Integrated Circuits Laboratory
Course Code BECL305 Semester 3
Teaching Hours/Week (L:T:P) 0:0:3 CIE Marks 50
Credits 04 SEE Marks 50
Examination type (SEE) Practical Exam Hours 100
Course objectives:
This laboratory course enables students to
 Understand the electronic circuit construction and its working
 Design and test multivibrator circuits for the given requirement.
 Develop the op-amp circuits for Digital to analog conversion and waveform generation.
 Realize Code converters and verify their performance
 Design and test the combinational and sequential logic circuits for their functionalities.
 Use the suitable ICs based on the specifications and function.
Sl. Experiments
No. (All the experiments have to be conducted using discrete components)
1 Design and set up the circuits using op-amp 741: i) Adder, ii) Comparator
2 Design and set up the circuits using op-amp 741: i) Integrator, ii) Differentiator
3 Design and test astable multivibrator using IC 555.
4 Design and test monostable multivibrator using IC 555
Design 4-bit R – 2R Op-Amp Digital to Analog Converter for a 4-bit binary input using
5 toggle switches
Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates, (b)
6 Half subtractor& Full subtractor using NAND gates
7 Implementation of 4-variable function using IC74151(8:1MUX)
8 Realize Binary to Gray code conversion & vice-versa using IC74139

9 Realize BCD to Excess-3 code conversion vice versa using IC74139

10 Realize using NAND Gates: i) D Flip-Flop, ii) Master-Slave JK Flip-Flop iii) T Flip-Flop
Realize the shift registers using IC7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring
11 counter and (vi) Johnson counter
12 Realize (a) Mod-N Counter using IC7490 (b) Synchronous counter using IC74192

Demonstration Experiments (For CIE)

1 Design and Test the second order Low pass Filter and plot the frequency response
2 Design and Test the second order High pass Filter and plot the frequency response
 About Integrated Circuits Laboratory
Rules & Guidelines for conducting Lab-Work

 Conduct yourself in a responsible manner at all times in the laboratory. Don’t talk aloud or
crack jokes in lab.
 A lab coat should be worn during laboratory experiments. Dress properly during a
laboratory activity. Long hair, dangling jewellery and loose or baggy clothing are a hazard
in the laboratory.
 Observe good housekeeping practices. Replace the materials improper place after work to
keep the lab area tidy.
 Do not wander around the room, distract other students, or interfere with the laboratory
experiments of others.
 Do not eat food, drink beverages or chew gum in the laboratory and do not use laboratory
glassware as containers for food or beverages.
 Students are not allowed to touch any equipment or other materials in the laboratory area
until you are instructed by Faculty or Instructor.
 Before starting Laboratory work follow all written and verbal instructions carefully. If you
do not understand a direction or part of a procedure, ASK YOUR CONCERN FACULTY
BEFORE PROCEEDING WITH THE ACTIVITY.
 Before using any equipment, it is must to read carefully all Labels and instructions. Set up
and use the equipment as directed by your Faculty & Instructor.
 If you do not understand how to use a piece of equipment, ASK THE FACULTY &
INSTRUCTOR FOR HELP!
 Perform only those experiments authorized by your faculty. Carefully follow all
instructions, both written and oral.
 Students are not allowed to work in Laboratory alone or without presence of the Faculty or
Instructor.
 Any failure / breakdown of equipment must be reported to the instructor.
 Protect yourself from getting electric shock.
 Ensure that safety devices are adequate, appropriate and in good working order.
 Without Fail bring the observation book, record and Manual for each Lab session.
 Compulsory fill the lab test form before coming to lab.
 Ensure that safety devices are adequate, appropriate and in good working order.

 Instructions before Starting the Experiment

1. Students are expected to study the circuit, theory and procedures, expected output
before doing the experiment.
2. Using of Digital trainer: Before constructing the circuit connect Digital trainer to the
supply mains and ensure That Digital trainer is working with glowing of LED
3. Checking patch cords: Check all probes for continuity by connecting output LED to
+5V and observing ON State of LED.
4. Checking of ICs: Before constructing circuit check the IC by verifying its truth table.
5. After constructing circuit, check the circuit connections before turning the power on.
6. Ensure that the circuit has +Vcc and ground connections.
7. Don’t pull out the connections with the power supply on.
8. Adjustment of signal generator: - Before connecting the signal generator to the circuit
check the followings.
a. Set the shape of the waveform (sinusoidal),
b. Set the frequency using coarse and fine adjustments.
c. Set the offset adjustments. Set the CRO in DC mode and ensure the waveform is
symmetry in both positive and negative cycle. If not, adjust it using the DC
offsetting potentiometer
d. Set the voltage magnitude using Vcourse settings and Vfine adjustments.
9. Adjustment of CRO
a. Select the right voltage and time scale to get the proper waveform
b. For clipper and clamper circuits, observe the waveform in DC mode only
c. Set the input waveform mainly for offset setting in DC mode only.
d. Before measurement, ensure X & Y are in calibrated mode (if provided
externally)
e. Ensure that Channel selection and trigger mode are properly set.
f. In case of two channels do not mix the signal and ground terminals.
10. Multi-meter adjustments:
a. Set the right mode before taking the readings.
b. For current reading, connect the multi-meter in mA (or A) mode to the circuit
before switching on the supply. Do not remove the current meter when the supply
is on. Check for ac and dc modes as required.
c. For voltage reading ensure that proper ac or dc setting.
d. Use the proper leads for the measurement. Wrong cables damage the instrument.
11. After adjusting the input voltage, check the circuit connections before turning the
power on.
12. Ensure that the circuit has one ground.
13. Don’t pull out the connections with the power supply on.

Think critically about what you are doing!!!!

 Cycle of experiments

CYCLE – I

1. Design and set up the circuits using op-amp 741: i) Adder, ii) Comparator

2. Design and set up the circuits using op-amp 741: i) Integrator, ii) Differentiator

Design and implement

3. (a) Half Adder & Full Adder using basic gates and NAND gates.
(b) Half subtractor& Full subtractor using NAND gates.
4 Implementation of 4-variable function using IC74151 (8:1MUX)

CYCLE – II

5. Design and test astable multivibrator using IC 555

6. Design and test monostable multivibrator using IC 555

7. Realize Binary to Gray code conversion & vice-versa using IC74139

8. Realize BCD to Excess-3 code conversion vice versa using IC74139

9. Realize using NAND Gates: i) D Flip-Flop, ii) Master-Slave JK Flip-Flop iii) T Flip-Flop

CYCLE – III

Design 4-bit R – 2R Op-Amp Digital to Analog Converter for a 4-bit binary input using
10.
toggle switches

Realize the shift registers using IC7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring
11.
counter and (vi) Johnson counter

12. Realize, (a) Mod-N Counter using IC7490 b) Synchronous counter using IC74192
Integrated Circuits Laboratory 2024-25

AND GATE

Symbol Pin Diagram

NAND GATE

Symbol Pin Diagram

NOT GATE

Symbol Pin Diagram

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STUDY OF LOGIC GATES

Aim: To study and verify the truth table of logic gates.

Objective: Identify various ICs and their specification

a. AND gate
b. NAND gate
c. NOT gate
d. OR gate
e. NOR gate
f. XOR
g. XNOR

Components Required:

Sl. No. Particulars Quantity

IC 7400, IC 7408, IC 7432, IC 7406,
1. 01 each
IC 7402, IC 7404, IC 7486
2. Logic gates (IC) trainer kit 01
3. Connecting patch chords. -

Procedure:

1. Fix the I.C on the I.C trainer kit.

2. Connections are made as shown, using the pin details of the gates. Toggle switches
and LED‟s in the trainer is used as inputs and outputs respectively.
3. Switch on the supply on the trainer and verify the truth table of the gates

Result:

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OR GATE

Symbol Pin Diagram

NOR GATE

Symbol Pin Diagram

XOR GATE

Symbol Pin Diagram

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EX-OR GATE

Symbol

Pin Diagram

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Circuit Diagram: Adder

Design:

Given Av=1 V1/R1 + V2/R2 + V0/Rf = 0

V0 = [(Rf/R1) V1 + (Rf/R2) V2]
Let R1=R2=R=1kΩ
R1 = R2 = Rf = 1KΩ
V0 = - (V1 + V2)

RF=1kΩ

Waveforms:

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Integrated Circuits Laboratory 2024-25

Experiment No: 01

Design and set up the circuits using Op-amp 741

i) Adder, ii) Comparator

1. Adder
Aim:
To study the output and design of inverting adder using op-amp.
Component Required:

Sl. No. Particulars Specification Quantity

4. Op-amp IC741 01
5. Resistors As per design
6. Multimeter 01
7. Spring Board + Connecting wires 01 Set

Procedure:

1. Check the components/Equipments for their working condition.

2. Connections are made as shown in the circuit diagram.
3. Apply input from RPS-1 (say V1=2V) and RPS-2 (Say V2=3V).
4. Observe the output from multi-meter at op-amp output pin-6.

Result:

V1 (volts) V2 (volts) Theoretical values of Vo Practical values of Vo

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Circuit Diagram: Comparator

Waveforms:

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2. Comparator
Aim:
To study the output and design of inverting adder using op-amp.
Component Required:

Sl. No. Particulars Specification Quantity

1. Op-amp IC741 01
2. Resistors As per design
3. Multimeter 01
4. Spring Board + Connecting wires 01 Set

Procedure:

1. Check the components/Equipments for their working condition.

2. Connections are made as shown in the circuit diagram.
3. Apply input from RPS-1 (say V1=2V) and RPS-2 (Say V2=3V).
4. Observe the output from multi-meter at op-amp output pin-6.

Result:

Input Voltage (p-p) Vref (volts) Output Amplitude

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Circuit Diagram: Integrator

Let the input frequency be 1 kHz. The frequency at which the integrator gives unity gain
output is given by,

Assume C = 0.1µf, R = 1.5KΩ

Waveform:

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Integrated Circuits Laboratory 2024-25

Experiment No: 02

Design and set up the circuits using Op-Amp 741

i) Integrator, ii) Differentiator
1. Integrator
Aim:
To study the output and design of integrator using op-amp.
This circuit performs the integration of the input waveform. The output voltage Vo can
−1
be expressed as V o =
RC
∫ V i dt+ K where K is the constant of integration which depends
upon the value of Vo at t = 0. The peak of the output waveform Vt is given by the expression
VT
V t= , where T is the time period of the input square wave. Integrators are commonly
4 RC
used in analog computers and wave shaping networks.

Component Required:

Sl. No. Particulars Specification Quantity

1. Op-amp IC741 01
2. Resistors and Capacitors As per design
3. CRO and Signal Generator 01
4. Spring Board + Connecting wires 01 Set

Procedure:

1. Check the components/Equipments for their working condition.

2. Connections are made as shown in the circuit diagram.
3. Apply square wave input using ASG (say amplitude=2V(P-P) and Frequency=
1kHz).
4. Observe the output from multi-meter at op-amp output pin-6.

Result:

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Circuit Diagram: Differentiation

Let the input frequency be 1 kHz. The frequency at which the integrator gives unity gain
output is given by,

Assume C = 0.1µf, R = 1.5KΩ

Waveform:

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2. Differentiator
Aim: To study and design of differentiator using op-amp.
If the input resistor of the inverting amplifier is replaced by a capacitor, it forms an
inverting differentiator. The output of the circuit is the derivative of the input. Gain of the
differentiator increases with increase in frequency, which makes the circuit unstable. This is a
d Vi
drawback of the circuit. The output voltage can be expressed as V o =−RF C i
dt
Differentiator functions as high pass filter. At high frequency it becomes unstable and breaks
into oscillations. Input impedance decreases with increase in frequency which makes the
circuit very susceptible to high frequency noise. Both stability and high frequency noise
problems can be reduced significantly by additional circuit elements.

Component Required:

Sl. No. Particulars Specification Quantity

1. Op-amp IC741 01
2. Resistors and Capacitors As per design
3. CRO and Signal Generator 01
4. Spring Board + Connecting wires 01 Set

Procedure:

5. Check the components/Equipments for their working condition.

6. Connections are made as shown in the circuit diagram.
7. Apply square wave input using ASG (say amplitude=2V(P-P) and Frequency=
1kHz).
8. Observe the output from multi-meter at op-amp output pin-6.

Result:

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Circuit Diagram:

Waveform:

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Experiment No: 03

Design and test Astable multivibrator using IC 555

Aim: To rig up a Astable Multivibrator using IC 555 timer to generate a pulse of given width.

This charging and discharging of capacitor continue and a rectangular oscillating output
wave for is generated. While capacitor is getting charge the output of 555 is HIGH, and while
capacitor is getting discharge output will be LOW. So, this is called Astable mode because
none of the state is stable and 555 automatically interchange its state from HIGH to LOW and
LOW to HIGH, so it is called Free running Multivibrator.

Now, the OUTPUT HIGH and OUTPUT LOW duration, is determined by the Resistors
R1 & R2 and capacitor C1.

This can be calculated using below formulas:

Time High (Seconds) T1 = 0.693 * (R1+R2) * C1

Time Low (Seconds) T2 = 0.693 * R2 * C1

Time Period T = Time High + Time Low = 0.693 * (R1+2*R2) * C1

Frequency f = 1/Time Period = 1/ 0.693 * (R1+2*R2) * C1 = 1.44 / (R1+2*R2) * C1

Duty Cycle: Duty cycle is the ratio of time for which the output is HIGH to the total time.

Duty cycle %: (Time HIGH/ Total time) * 100 = (T1/T) * 100 = (R1+R2)/ (R1+2*R2) *100

Component Required:

Sl. No. Particulars Range Quantity

1. IC 555 01
2. Capacitor 0.1μF, 0.01μF 02
3. Resistors 5.7kΩ, 3KΩ leach
4. Resistor 7.2KΩ 02
5. Diode BY 127 02
6. Trainer Kit
7. Connecting wires

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Design:
For Duty cycle 60%
Charging time T1=0.693*(Ra+Rb)*C Discharging time T2=0.693*Rb*C
Let f=1 kHz and choose duty cycle = 60% Duty cycle D = T1/T where T = 1/f = 1mSec
T1 = D x T = 60% x 1x10-3 = 0.6x10-3Sec
T = T1 + T2
T2 = T - T1 = 1x10-3 – 0.6x10-3 = 0.4x10-3 Sec T2 = 0.693 x Rb x C
Assume C = 0.1μF Rb = T2/(0.693xC)
= 0.4x10-3/(0.693x0.1x10-6) = 5.7KΩ
T1=0.693x(Ra+Rb)xC
(Ra + Rb) = T1/(0.693xC)
Ra = [0.6x10-3/ (0.693x0.1x10-6)] – 5.7x103
Ra = 2.95KΩ, choose Ra = 3K Ω
Note: T1 = Ton and T2 = Toff
For Duty cycle 50%
Charging time T1=0.693*Ra*C Discharging time T2=0.693*Rb*C
Let f=1 kHz and choose duty cycle = 50%
Duty cycle D = T1/T
where T = 1/f = 1mSec
T1 = D x T = 50% x 1x10-3 = 0.5x10-3Sec T = T1 + T2
T2 = T - T1 = 1x10-3 – 0.5x10-3
Therefore, T2 = 0.5x10-3 Sec T2 = 0.693 x Rb x C
Assume C = 0.1μF Rb = T2/(0.693xC)
= 0.5x10-3/(0.693x0.1x10-6) = 7.2KΩ
T1=0.693 x Ra x C Ra = T1/(0.693xC)
Ra = 0.5x10-3/ (0.693x0.1x10-6) Ra = 7.2KΩ

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Integrated Circuits Laboratory 2024-25

Procedure:
1. Configure the circuit as per the circuit diagram.
2. Use RA = 3 kΩ, RB = 5.7 kΩ, RL = 1 kΩ and CT = 0.1 μF, C = 0.01 μF. Using the
power supply set VCC = 10 V.
3. Compute the expected values of fosc and duty cycle (%).
4. Connect the output terminal (pin 3) to channel 1 of the oscilloscope. Also feed the
voltage across capacitor to channel 2.
5. Power on your circuit and observe and save the output. Determine the values of fosc
and duty cycle (%) from your observations and compare with the theoretical values.
6. When you are done, turn off the power to your experimental circuit.
Result:
Ton = _________, Toff = ________, f = _________ Hz

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Design:
O/p pulse width = Td = 0.5msec
For Monostable multivibrator,
Td= 1.1RaC, Let C=0.01µF 0.5x10-3 = 1.1xRa x 0.01x10-6
Ra = 45.45KΩ, choose Ra = 47KΩ Vut, upper threshold Vg = 2/3 Vcc.
Let f = 1KHz, then T = 1mSec, RTCT << T
RTCT = 0.1T, Assume CT = 0.01μF RT = 0.1x1x10-3/0.01x10-6 = 1KΩ
Duty cycle: D = (Td/T) x 100%
D = (0.5x10-3/1x10-3) x 100% = 50%

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Integrated Circuits Laboratory 2024-25

Experiment No: 04

Design and test monostable multivibrator using IC 555

Aim: To rig up a Monostable Multivibrator using IC 555 timer to generate a pulse of given
width.

The output of the monostable multivibrator using 555 timer remains in its stable state
until it gets a trigger. In monostable 555 multivibrator, when both the transistor and capacitor
are shorted then this state is called as a stable state. When the voltage goes below at the
second pin of the 555 IC, the o/p becomes high. This high state is called quasi stable state.
When the circuit activates then the transition from a stable state to quasi stable state. Then the
discharge transistor is cut off and capacitor starts charging to VCC. Charging of the capacitor
is done via the resistor R1 with a time constant R1C1. Hence, the voltage of the capacitor
increases and finally exceeds 2/3 Vcc, it will change the internal control flip flop, thereby
turning off the 555 timer IC. Thus, the o/p goes back to its stable state from an unstable state.

The Time duration of the pulse is given by

T = 1.1RC

Where, R is in Ω and C in Farads.

Finally, we can conclude that, in the monostable multivibrator using 555 timers, the
o/p stays in a low state until it gets a trigger i/p. This type of operation is used in push to
operate systems. When the input is triggered, then the o/p will go to high state & comes back
to its original state.

Component Required:

Sl. No. Particulars Range Quantity

1. IC 555 01
2. Capacitor 0.1μF, 0.01μF leach
3. Resistors 10kΩ, 1KΩ leach

Procedure:
1. Configure the circuit as per the circuit diagram.
2. Use R1 = 1 kΩ, RA = 2.7 kΩ, RL = 1 kΩ and CT = 1 μF, CD = 0.047 μF, C = 0.01
μF. Using the power supply set VCC = 10 V.
3. Compute the expected value of pulse duration.
4. Apply a square wave input of frequency 1 kHz at terminal N of the circuit diagram.
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Integrated Circuits Laboratory 2024-25

5. Connect the output terminal (pin 3) to the oscilloscope. Also feed the voltage across
capacitor to channel 2.
6. Power on your circuit and observe the output. Determine the value of pulse duration
from your observations and compare with the theoretical values. Save the data.
7. When you are done, turn off the power to your experimental circuit.

Result:
RA = ______________ KΩ, CT = ______________ µF
Output waveform and capacitor voltage as observed in oscilloscope: (paste data here)

Parameter Calculated Value (ms) Observed Value (ms) Error

Pulse Duration

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Circuit Diagram:

Design Specification:
Design 4-bit R-2R DAC for an output voltage, V0 = 5V,
when the input is (10)d [i.e., (1010)b].
D3 D2 D1 D0
(10)10 = ( 1 0 1 0 )2

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Experiment No: 05

Design 4-bit R – 2R Op-Amp Digital to Analog Converter for a

4-bit binary input using toggle switches

Aim: To design the four-bit DAC using op-amp from toggle switch to get the output voltage
for various values of binary data.

Component Required:

Sl. No. Particulars Range Quantity

1. IC μA741 01
2. Resistors As per design
3. Multimeter - 01
4. Base board + connecting wires - 01

Procedure:
1. Check the components/Equipments for their working condition.
2. Connections are made as shown in the circuit diagram-6.
3. Digital input data is given at D3, D2, D1, D0 and corresponding analog output voltage
V0 is measured using voltmeter.
4. Tabulate the readings & plot the graph of Vin v/s Vo.
Note:
1. Do. D1. D2 & D3 are binary input.
2. Vo is the analog output.
3. Binary input Di (i = 0 to 3) can be made ‘0’ by connecting the i/p to ground. It can be
made ‘1’ by connecting to –5 V.

Result:

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Observation:

Binary Inputs Analog O/P Analog O/P

Decimal
Vo (volts) Vo (volts)
Value D3 D2 D1 D0 Theoretical values Practical values
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

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Half Adder using basic gates:

A B Sum Carry
0 0 0 0 S  AB  AB
0 1 1 0 S  AB
C  AB
1 0 1 0
1 1 0 1

Full Adder using basic gates:

Realization of full adder using Basic and EXOR gates

Half Adder using NAND gates only:

Realization of half adder using NAND gates

Full Adder using NAND gates only:

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Experiment No: 06

Design and implement

(a) Half Adder & Full Adder using basic gates and NAND gates,

(b) Half subtractor & Full subtractor using NAND gates

(a) Half Adder & Full Adder using basic gates and NAND gates,

Aim: To design and implement Half Adder & Full Adder using,

i. EXOR & Basic gates

ii. NAND gates

Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. AND Gate IC 7408 - 01
3. OR Gate IC 7432 - 01
4. NOT Gate IC 7404 - 01
5. NAND Gate (2 Input) IC 7400 - 01
5. XOR Gate IC 7486 - 01
6. Patch chords / connecting wires - -

Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth table.
4. Note down the output readings for half/full adder of the sum/difference and the
carry/borrow bit for different combinations of inputs.

Result: Thus, the Logic circuit of Full Adder Circuit was constructed and the truth table is
verified.

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Half Adder using basic gates:

A B Diff Borrow
0 0 0 0 Difference  A 
B
0 1 1 1 Borrow =A•B
1 0 1 0
1 1 0 0

Full Adder using basic gates:

Half Adder using NAND gates only:

Realization of half adder using NAND gates

Full Adder using NAND gates only:

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(b) Half subtractor & Full subtractor using NAND gates

Aim: To design and implement Half subtractor & Full subtractor using,

iii. EXOR & Basic gates

iv. NAND gates

Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. AND Gate IC 7408 - 01
3. OR Gate IC 7432 - 01
4. NOT Gate IC 7404 - 01
5. NAND Gate (2 Input) IC 7400 - 01
5. XOR Gate IC 7486 - 01
6. Patch chords / connecting wires -

Procedure:
1. Verify the gates.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to the truth table.
4. Note down the output readings for half/full subtractor of the sum/difference and the
carry/borrow bit for different combinations of inputs.

Result: Thus, the Logic circuit of Full Adder Circuit was constructed and the truth table is
verified.

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Pin diagram of 74151 IC

Block diagram of n: 1 MUX and Truth Table of 8:1 MUX

8:1 MUX using gates

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Experiment No: 07

Implementation of 4-variable function using IC74151(8:1MUX)

Aim: To realize the 4 variable functions using 8 to1 multiplexer.

Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. 81 MUX IC 74151 - 01
3. Patch chords / connecting wires - -
Theory:
 Multiplexer is a combinational circuit that is one of the most widely used in digital
design.
 The multiplexer is a data selector which gates one out of several inputs to a single o/p.
It has n data inputs & one o/p line & m select lines where 2m= n shown in fig a.
 Depending upon the digital code applied at the select inputs one out of n data input is
selected & transmitted to a single o/p channel.
 Normally strobe (G) input is incorporated which is generally active low which enables
the multiplexer when it is LOW. Strobe i/p helps in cascading.
 IC 74151A is an 8: 1 multiplexer which provides two complementary outputs Y & Y.
The o/p Y is same as the selected i/p & Y is its complement. The n: 1 multiplexer can
be used to realize a m variable function. (2m= n, m is no. of select inputs)

Procedure:
1. The IC 74151 is fixed on the IC base board and Vcc & Gnd connections are given
from 5V supply.
2. Working of 74151 as 8:1 MUX is verified using Truth table.
3. Connections are made as shown in the circuit diagram to realize 4 variable functions.
4. All the inputs are connected to the switches and outputs to the LEDs of LED box.
5. The truth table is verified for different combinations of input.
(LED ON = 1, LED OFF = 0)

Result: Given 4-variable function using IC74151 (8:1MUX) is verified.

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Ex: Implement the following Boolean function using 8:1 multiplexer.

F (A, B, C, D) = ∑m (2, 4, 5, 7, 10, 14)
Design Table Using MSB Bit A:

Logic Diagram:

Truth Table:
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

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Truth table: Binary to Gray code Circuit diagram: Binary to Gray code

Binary code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1

G2 = B3 ⨁ B2
G3 = B3
0 1 1 0 0 1 0 1
G1 = B1 ⨁ B2
G0 = B1 ⨁B0
0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
Binary to Gray code using Nand gates

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Experiment No: 08

Realize Binary to Gray code conversion & vice-versa using

IC74139
Aim: To realize Binary to Gray code converter and vice versa using IC74139.
Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. IC 74139 - 01
3. IC 7420 01
4. IC 7404 01
5. Patch chords / connecting wires - -

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

Result: Binary to Gray and Gray to binary code Converters using IC74139 have been
verified.

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Truth table: Gray to Binary code Circuit diagram: Gray to Binary code

Gray code Binary code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

B2 = G3 ⨁ G2
0 1 0 0 0 1 1 1 B3 = G3

B1 = G3 ⨁ G2 ⨁ G1
B0 = G3 ⨁ G2 ⨁ G1 ⨁ G0
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
Gray to Binary code using Nand gates:

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Truth table: BCD to Excess- 3 Code

Bcd BCD (input) Excess -3 code

code
(output)
word
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Bcd to excess-3 codeNand gate:

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Experiment No: 09

Realize BCD to Excess-3 code conversion vice versa using

IC74139
Aim: To design and realize the following using IC 7483.

I) BCD to Excess- 3 Code

II) II) Excess-3 to BCD Code.

Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. IC 7483,7486 - 01
3. Patch chords / connecting wires - -

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.

RESULT:
Working of BCD to Excess-3 code converter and Excess 3 code to BCD converter
have been verified.

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Truth table: Excess -3 to BCD code

Excess -3 (input) Bcd Bcd code (output)

code
E3 E2 E1 E0 word B3 B2 B1 B0
0 0 1 1 0 0 0 0 0
0 1 0 0 1 0 0 0 1
0 1 0 1 2 0 0 1 0
0 1 1 0 3 0 0 1 1
0 1 1 1 4 0 1 0 0
1 0 0 0 5 0 1 0 1
1 0 0 1 6 0 1 1 0
1 0 1 0 7 0 1 1 1
1 0 1 1 8 1 0 0 0
1 1 0 0 9 1 0 0 1

Excess -3 to BCD Code using Nand gate:

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Truth table: D-Flip flop using NAND gates

Clock D Qn+1 Operation

0 X Qn No Change

0 0 Reset
1 1 Set

Logic symbol: D-Flip flop

Logic Diagram: D-Flip flop

Waveform: D-Flip flop

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Experiment No: 10

Realize using NAND Gates: i) D Flip-Flop, ii Master-Slave JK

Flip-Flop iii) T Flip-Flop
Aim: To verify the Truth Table of clocked D Flip-flop, Mater-Slave JK Flip-flop and T Flip-
flop

Component Required:

Sl. No. Particulars Range Quantity

1. Digital Trainer Kit - 01
2. IC 7400, 7404 - 01
3. Patch chords / connecting wires - -

Procedure:

1. Connections are made as shown in Logic diagram, using the pin details of different
IC’s used.
2. Switch on the power supply of the Trainer Kit.
3. The Truth Tables of flip flops are verified for various combinations of inputs.

Result: Thus, the truth table for clocked D, Mater-Slave JK and T Flip-Flops are verified
using NAND gate.

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Truth table: JK-Flip flop using NAND gates

Clock J K Qn+1 Operation

0 X X Qn No Change

0 0 Qn No Change

0 1 0 Reset

1 0 1 Set

1 1 Qn Toggle

Logic symbol: JK-Flip flop

Logic Diagram: Master-Slave JK Flip-Flop

Waveform: JK-Flip flop

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Truth table: T-Flip flop using NAND gates

Clock T Qn+1 Operation

0 X Qn No Change

0 Qn No Change
1 Qn Toggle

Logic symbol: T-Flip flop

Logic Diagram: T-Flip flop

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Pin Diagram: SISO

Circuit Diagram: Serial In Serial Out [SISO] register

Tabular Column: SISO

Q
Clock Serial Data QA QB QD
C
1 DO = 0 0 X X X
2 D1 = 1 1 0 X X
3 D2 = 1 1 1 0 X
4 D3 = 1 1 1 1 0 = DO
5 X X 1 1 1 = D1
6 X X X 1 1 = D2
7 X X X X 1 = D3

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Experiment No: 11

Realize the shift registers using IC7495: (i) SISO (ii) SIPO (iii)
PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter
Aim: To implement different types of shift registers like Serial In Serial Out [SISO], Serial In
Parallel Out [SIPO], Parallel In Parallel Out [PIPO] and Parallel In Serial Out [PISO]
using D-flip flops and to verify their observation table.

i. SISO
Procedure: Serial In Serial Out: (SISO)
1. Connections are made as shown in the circuit diagram.
2. The shift register is loaded with 4 bits of data one by one serially.
3. At the end of the 4th clock pulse the first data ‘do’ appears at QD.
4. Another clock pulse is applied; the second data ‘d1’ appears at QD.
5. Another clock pulse is applied; the third data ‘d2’ appears at QD.
6. Application of next clock pulse will enable the fourth data ‘d3’ to appear at QD.
7. The data applied serially at the i/p comes out serially at QD.

Result:

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Pin Diagram: Serial In Parallel Out [SIPO]

Circuit Diagram: SIPO

Tabular Column: SIPO

Clock Serial Data QA QB QC QD

1 0 0 X X X
2 1 1 0 X X
3 1 1 1 0 X
4 1 1 1 1 0

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ii. SIPO

Procedure: Serial In Parallel Out [SIPO]

1. Connections are made as shown in the circuit diagram.

2. The data is applied at the serial i/p
3. One clock pulse is applied at clock 1 (Right shift) and this data is observed at QA.
4. The next data is applied at serial i/p.
5. One more clock pulse is applied at clock 1and it is observed that the data on QA will
shift to QB and the new data applied will appear at QA.
6. Steps 2 and 3 are repeated till all the 4 bits of data are entered one by one into the shift
register.

Result:

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Pin Diagram: Parallel In Parallel Out [PIPO]

Circuit Diagram: PIPO

Tabular Column: PIPO

Parallel Data Inputs Parallel Data Outputs

Clock
A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1

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iii. PIPO

Procedure: Parallel In Parallel Out [PIPO]

1. Connections are made as shown in the circuit diagram.
2. Apply the 4-bit data is applied at A, B, C & D.
3. Apply one clock pulse is applied at clock 2 (note: Mode control M = 1).
4. The 4-bit data at A, B, C & D appears at QA, QB, QC& QD respectively.

Result:

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Pin Diagram: Parallel In Serial Out [PISO]

Circuit Diagram: PISO

Tabular Column: PISO

Cloc Parallel Data Inputs Parallel Data Outputs

Mode
k A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
0 2 x x x x x 1 0 1
0 3 x x x x x x 1 0
0 4 x x x x x x x 1

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iv. PISO

Procedure: Parallel In Serial Out [PISO]

1. Connections are made as shown in the circuit diagram.
2. Apply the desired 4-bit data at A, B, C and D.
3. Keeping the mode control M=1, apply one clock pulse. The data applied at A, B, C &
D will appear at QA, QB, QC& QD respectively.
4. Now mode control M=0, clock pulses are applied one by one and the data arriving out
serially at QD is observed.

Result:

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Pin Diagram: Ring Counter

Circuit Diagram: Ring Counter

Tabular Column: Ring Counter

Q
Clock Mode QA QB QD
C
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 0
4 0 0 0 0 1
5 0 0 0 0 0
6 0 repeats

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v. RING COUNTER

Procedure:
1. Make the connection as show in the ring counter circuit diagram.
2. connect the inputs A, B, C, D to input switch present on trainer kit.
3. connect the outputs QA, QB, QC, QD.
4. connect the serial input to pin 10of the 7495 IC i.e., QD.
5. connect 8th & 9th pins of the IC 7495 to clock, which is present on the trainer kit.
6. connect mode(M) 6th pin of IC 7495 to input switch.
7. Verify the truth table of ring counter.

Result: Verified the truth table of Ring Counter using 4-Bit shift register.

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Pin Diagram: Johnson Counter

Circuit Diagram: Johnson Counter

Tabular Column: Johnson Counter

Q
Clock Mode QA QB QD
C
1 1 1 0 0 0
2 0 1 1 0 0
3 0 1 1 1 0
4 0 1 1 1 1
5 0 0 1 1 1
6 0 0 0 1 1
7 0 0 0 0 1
8 0 0 0 0 0
9 0 1 0 0 0
10 0 repeats

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vi. JOHNSON COUNTER

Procedure:
1. Make the connection as show in the twisted ring counter circuit diagram.
2. connect the inputs A, B, C, D to input switch present on trainer kit.
3. connect the outputs QA, QB, QC, QD.
4. connect the serial input to NOT gate, clock, which is present on the trainer kit.
5. connect the terminal of the NOT Gate pin 10 of the IC 7495 i.e., QD.
6. connect the 8th & 9th pins of the IC 7495 to clock, which is present on the trainer kit.
7. connect mode(M) 6th pin of IC 7495 to input switch.
8. Verify the truth table of Johnson counter.

Wave forms: Johnson counter:

Result: Verified the truth table of Johnson Counter using 4-Bit shift register.

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Pin Diagram: Mod-N Counter using IC7490

Circuit Diagram:

Tabular Column:

Clock QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 repeats

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Experiment No: 12

Realize, (a) Mod-N Counter using IC7490 (b) Synchronous

counter using IC74192
A. Mod-N Counter using IC7490

Aim: To realize a Modulo N-counter using 7490 and verify the expected truth table and
display the output waveform for a square wave input of given frequency. (N–to be
specified, N  9).

Procedure:

Result: Verified the truth table of Mod-N Counter using IC7490

B. Synchronous counter using IC74192

Procedure:

Result: Verified the truth table of Synchronous counter using IC74192

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To use it as a divide by N counter [N<=10, say N=7, N=5]

Truth Table:

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 0 0 0

Truth Table:

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0

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Pin Diagram: Synchronous counter using IC74192

1. Count from 3 to 8:

Truth Table: Circuit Diagram:

Clk QD QC QB QA
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 0 0 1 1

2. Count from 12 to 5:

Truth Table: Circuit Diagram:

Clk QD QC QB QA
0 1 1 0 0
1 1 0 1 1
2 1 0 1 0
3 1 0 0 1
4 1 0 0 0
5 0 0 1 1
6 0 1 1 0
7 0 1 0 1
8 1 1 0 0

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Circuit Diagram: II-Order Active Low Pass Filter

Design: LPF
Assume Pass band gain AV = 2, Cutoff frequency fC = 5KHz
1. Amplifier: then Rf = R, choose Rf = R = 10KΩ
1
2. Filter Circuit: Cut off frequency f c = = 5KHz
2 π R1 C 1

Choose C1 = 0.01 π f, then R1 = 3.183 KΩ ⁓ 3.3 KΩ

Rf = 10KΩ, R1 = 3.3KΩ, C1 = 0.01µf, Op-amp = µA741
Frequency Response: Low Pass Filter

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Experiment No: 01

Design and Test the second order Low pass Filter and plot the
frequency response
Aim: To conduct an experiment to study the frequency response of an II order butterworth
active low pass filter for the given design specification.

Component Required:

Sl. No. Particulars Range Quantity

1. Op-amp μA 741 01
2. Resistors & Capacitors As per design 01
3. CRO + Probes - 01 set
4. Signal Generator - 01
5. Spring board + connecting wires - 01 set

Procedure:

1. Connections are made as shown in the circuit diagram.

2. Apply sine wave i/p signal of peak amplitude 5 volts.
3. Check the gain of non-inverting amplifier by keeping the frequency of the input signal
in the pass band of the filter. Note down the output voltage VO max.
4. Keeping the input signal amplitude constant, vary the frequency until the output
voltage reduces to 0.707 Vo max, the corresponding frequency is the cut-off frequency
(fC) of the filter.

To find Roll off:

Maintaining the input signal amplitude constant, note down the output amplitude at the
cut off frequency fH and 10fH. The difference in the gain in dB at f H and 10fH will give
the roll off.

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Tabular Column: Vi (p - p) = __________Volts (Constant)

Gain magnitude
Sl. O/P Voltage Voltage Gain
I/P frequency in Hz in DB
No. VO (P - P) (volts) Av = Vo/Vi
20log(Vo/Vi)
1
2
3
4
5
6
7
8
9
10

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Result:

Cut off frequency, fH Theoretical = ______________

Cut off frequency, fH Practical = ______________

Pass band gain Av Theoretical = ______________

Pass band gain Av Practical = ______________

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Circuit Diagram: II-Order Active High Pass Filter

Design: HPF
Assume Pass band gain AV = 2, Cutoff frequency fC = 5KHz
1. Amplifier: then Rf = R, choose Rf = R = 10KΩ
1
2. Filter Circuit: Cut off frequency f c = = 5KHz
2 π R1 C 1

Choose C1 = 0.01 π f, then R1 = 3.183 KΩ ⁓ 3.3 KΩ

Rf = 10KΩ, R1 = 3.3KΩ, C1 = 0.01µf, Op-amp = µA741
Frequency Response: High Pass Filter

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Experiment No: 02

Design and Test the second order High pass Filter and plot the
frequency response
Aim: To conduct an experiment to study the frequency response of an II order butterworth
active high pass filter for the given design specification.

Component Required:

Sl. No. Particulars Range Quantity

1. Op-amp μA 741 01
2. Resistors & Capacitors As per design 01
3. CRO + Probes - 01 set
4. Signal Generator - 01
5. Spring board + connecting wires - 01 set

Procedure:

1. Connections are made as shown in the circuit diagram.

2. Apply sine wave i/p signal of peak amplitude 5 volts.
3. Check the gain of non-inverting amplifier by keeping the frequency of the input signal
in the pass band of the filter. Note down the output voltage VO max.
4. Keeping the input signal amplitude constant, vary the frequency until the output
voltage reduces to 0.707 Vo max, the corresponding frequency is the cut-off frequency
(fC) of the filter.

To find Roll off:

Maintaining the input signal amplitude constant, note down the output amplitude at the
cut off frequency fL and 0.1fL. The difference in the gain in dB at f L and 0.1fL will give
the roll off.

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Integrated Circuits Laboratory 2024-25

Tabulation: Vi (p - p) = __________Volts (Constant)

Gain magnitude
Sl. O/P Voltage Voltage Gain
I/P frequency in Hz in DB
No. VO (P - P) (volts) Av = Vo/Vi
20log(Vo/Vi)
1
2
3
4
5
6
7
8
9
10

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Integrated Circuits Laboratory 2024-25

Result:

Cut off frequency, fL Theoretical = ______________

Cut off frequency, fL Practical = ______________

Pass band gain Av Theoretical = ______________

Pass band gain Av Practical = ______________

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Integrated Circuits Laboratory 2024-25

VIVA QUESTIONS
1. What do you mean by Logic Gates?
2. What are the applications of Logic Gates?
3. What is Truth Table?
4. Why we use basic logic gates?
5. Write down the truth table of all logic gates?
6. What do you mean by universal gate?
7. Write truth table for 2 I/P OR, NOR, AND and NAND gate?
8. Implement all logic gate by using Universal gate?
9. Why is they called Universal Gates?
10. Give the name of universal gate?
11. Why NAND & NOR gates are called universal gates?
12. Realize the EX – OR gates using minimum number of NAND gates.
13. Give the truth table for EX-NOR and realize using NAND gates?
14. What is the logic low and High levels of TTL IC’s and CMOS ICs?
15. Compare TTL logic family with CMOS family?
16. Which logic family is fastest and which has low power dissipation?
17. Draw the circuit diagram of 2 input adder.
18. What is the other name for adder?
19. Draw the circuit diagram of a Subtractor.
20. Which amplifier acts as a Subtractor?
21. How many basic input parameters are required for a comparator?
22. Draw the circuit diagram of a non-inverting comparator and inverting comparator.
23. What is the output of a non-inverting comparator and inverting comparator if the input
is sinusoidal?
24. What are the differences between the Inverting and Non–Inverting comparator?
25. What is the name of the comparator if the reference voltage is 0V?
26. Draw the circuit diagram and the output waveform of a Zero Crossing Detector if the
input is sinusoidal?
27. What is the name of a regenerative comparator? Draw an op- amp circuit whose
output Vo is V1+ V2 – V3 –V4.
28. What is an Integrator?
29. Draw the circuit of the Integrator using op-amp IC741.
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Integrated Circuits Laboratory 2024-25

30. Write down the expression for Vo of an Integrator.

31. Draw the frequency response of the Integrator and explain.
32. Draw the output waveform of the Integrator when the input is a square wave.
33. What is the purpose behind the connection of Rf in the feedback path of Integrator?
34. What are the applications of Integrator?
35. Why R and C are used in both Integrator and Differentiator circuits?
36. What is a Differentiator?
37. Draw circuit diagram of Half Adder circuit?
38. Draw circuit diagram of Full Adder circuit?
39. Draw Full Adder circuit by using Half Adder circuit and minimum no. of logic gate?
40. Write Boolean function for half adder? Q.5 Write Boolean function for Full adder?
41. Design the half Adder & Full Adder using NAND-NAND Logic.
42. Draw circuit diagram of Half Subtractor circuit?
43. Draw circuit diagram of Full Subtractor circuit?
44. Draw Full Subtractor circuit by using Half Subtractor circuit and minimum no. of
logic gate?
45. Write Boolean function for half Subtractor?
46. Write Boolean function for Full Subtractor?
47. What is Excess-3 code? Why it is called Excess-3 code?
48. What is the application of Excess-3 Code?
49. What is 2s compliment subtraction
50. Why XOR gates are used in parallel adder/subtractor
51. What is ASCII code?
52. Excess-3 code is Weighted or Unweighted?
53. Out of the possible 16 code combination? How many numbers used in Excess-3 code?
54. What is Hybrid function?
55. What is Flip-Flop?
56. What is Latch circuit?
57. Draw a truth table of Master Slave JK, D and T?
58. What are the disadvantages of Master Slave JK, D and T Flip-Flop?
59. How can you remove the problem of Master Slave JK Flip –Flop?
60. Make circuit diagram of Master Slave JK, D and T Flip-Flop?
61. What is the advantage of Edge triggering over level triggering?
62. What is the relation between propagation delay & clock frequency of flip-flop?
63. What is the necessity for sequence generation?

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Integrated Circuits Laboratory 2024-25

64. What is PIPO, PISO, SIPO, and SISO with respect to shift register?
65. Differentiate between serial data & parallel data
66. What is the significance of Mode control bit?
67. What is a ring counter?
68. What is a Johnson counter?
69. How many Flip-flops are present in IC 7495?
70. What is a decade counter?
71. What do you mean by a ripple counter?
72. Explain the design of Modulo-N counter (N ≤ 9) using IC 7490
73. What is a preset table counter?
74. What are the applications of preset table counters?
75. Explain the working of IC 74192
76. Write the circuit for preset value of 0100 and N=5 (up counter)

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