EM 4/1, SALT LAKE, SECTOR-V, KOLKATA-700091

LABORATORY MANUAL

For
DIGITAL SYSTEM DESIGN LABORATORY (EC-392)

Department of
ELECTRONICS & COMMUNICATION ENGINEERING

Last Modified: March 2024

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Institute Vision:

Emerge as a Centre of excellence for engineering and management studies encouraging

research and building leaders contributing towards individual and social empowerment.

Institute Mission:

1. To identify individual potential, capabilities and skills to achieve confidence and

competence.
2. To practice innovative and modern methods of pedagogy encouraging holistic
education and research.
3. To enhance employability skills through collaborative ventures with the industry.
4. To build leaders and entrepreneurs with integrity and ethics fostering growth and
sustainability.

Departmental Vision:

To be recognized as Centre of excellence in Electronics and Communication Engineering

education, higher studies and research as per the needs of industry, deeply inculcating
professional ethics and duly nurturing all-round personality development.

Departmental Mission:

M1. To offer the state-of-art infrastructure for teaching, learning, research activities and
innovative hands on engineering project.
M2. To deliver curricula to meet ever changing industry requirement and cope up with
the present trends in higher studies and research, through student centric learning
methodologies.
M3. To promote all round personality development of the students through interaction
with alumni and experts from academia and industry.
M4. To motivate and upgrade faculty members for departmental success, growth and
quality enhancement.

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Department Program Educational Objectives (PEOs): Our Graduate will

PEO1 Utilize their domain knowledge to analyze data and technical concept for
application to higher studies, research and innovation in Electronics and
Communication engineering.
PEO2 Excel in multidisciplinary areas with modern engineering tools, techniques and
relevant software.
PEO3 Develop expressive confidence and presentation skills to bring forth celebrated
industry leaders, entrepreneurs, academicians and researchers.
PEO4 Inculcate lifelong learning, professional and ethical values for the development of
the society.

Program Outcomes (POs):

PO1. Engineering Knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and engineering specialization to the solution of complex
engineering problems.

PO2. Problem analysis: Identify, formulate, research literature, and analyse

engineering problems to arrive at substantiated conclusions using first principles of
mathematics, natural and engineering sciences.

PO3. Design/Development of solutions: Design solutions for complex engineering

problems and design system components, processes to meet the specifications with
consideration for the public health and safety and the cultural societal and environmental
considerations.

PO4. Conduct investigations of complex problems: Use research based knowledge

including design of experiments, analysis and interpretation of data and synthesis of the
information to provide valid conclusions.

PO5. Modern tool usage: Create, select and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modelling to complex
engineering activities with an understanding of the limitations.

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 PO6. The engineer and society: Apply reasoning informed by the contextual
knowledge to access societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.

PO7. Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of and need for sustainable development.

PO8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.

PO9. Individual and team work: Function effectively as an individual, and as a

member or leader in teams, and in multidisciplinary settings.

PO10. Communications: Communicate effectively with the engineering community

and with the society at large. Be able to comprehend and write effective reports
documentation. Make effective presentations and give and receive clear instructions.

PO11. Project management and finance: Demonstrate knowledge and understanding

of engineering and management principles and apply these to one’s own work, as a
member and leader in a team. Manage projects in multidisciplinary environments.

PO12. Life-long learning: Recognize the need for, and have the preparation and ability
to engage in independent and lifelong learning in the broadest context of technological
change.

Program Specific Outcomes (PSOs):

PSO-1. Solve real life industrial problems relevant to electronic circuits, VLSI and
nanotechnology, control system, microwave, embedded system, IoT and
communication engineering by applying current techniques, equipment, modern
engineering tools, hardware and software.

PSO-2. Pursue research and entrepreneurship activities in the field of computer,

electronics and communication engineering as per the needs of industry and society.

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 Course Outcome:
After this course student will be able to

CO1 Understand different types of Digital logic IC.

Design Combinational circuits (Adder, Subtractor, parity decoder, multiplexer,
CO2 Comparator) using logic gates.
Design of different type of sequential circuits (RS-JK & D flip-flop and Up/Down
CO3 synchronous and asynchronous counter

CO4 Design of MOS inverter by using different types of simulator.

CO5 Design of Multiplexer , Decoder and various logic Gates by using VHDL/Verilog

Prerequisites:

1. How to operate Power supply.

2. Student should aware internal connection of bread board.

3. How to work pulse generator for Sequential circuit.

Reference Book & Special Resources:

.

1. Morries Mano- Digital Logic Design- PHI

2. R.P.Jain—Modern Digital Electronics, 2/e , Mc Graw Hill
3. H.Taub&D.Shilling, Digital Integrated Electronics- Mc Graw Hill.
4. Douglas L.Perry, “VHDL: Programming by Example”, McGraw-Hill, 2002.
5. Charles H. Roth, Lizy Kurian John, “Digital systems design
using VHDL”, Thomson, 2008.

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 Syllabus
Proposed By
Maulana Abul Kalam Azad University of Technology (MAKAUT)
Digital System Design Laboratory Code: EC392
Contact: 2P
Credits: 1
Sl Name of the Experiment
No
1

Introduction to Digital Electronics Lab- Nomenclature of Digital Ics,

Specifications, Study of the Data Sheet, Concept of Vcc and Ground,
Verification of the Truth Tables of Logic Gates using TTL ICs.
2

Implementation of the Given Boolean Function using Logic Gates in

Both Sop and Pos Forms.
3 Verification of State Tables of Rs, J-k, T and D Flip-Flops using NAND & NOR
Gates
4 Implementation and Verification of Decoder/De-Multiplexer and Encoder using
Logic Gates.
5

Implementation of 4x1 Multiplexer using Logic Gates.

6 Implementation of 4-Bit Parallel Adder Using 7483 IC.
7 Design, and Verify the 4-Bit Synchronous Counter.
8 Design, and Verify the 4-Bit Asynchronous Counter.
9 Simulation of MOS Inverter with different loads using PSPICE
software.
10 Simulation of CMOS Inverter for different parameters Kn, Kp as a
design variable in suitable circuit simulator software.

11 Design of a 4-bit Multiplexer using VHDL\Verilog.

12 Design of a decade counter using VHDL\Verilog.

13 Design of a 3-input NAND gate and its simulation using suitable logic simulator.

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 List of Experiment Performed
Sl No Name of the Experiment

1 Introduction to Digital Electronics Lab- Nomenclature of Digital Ics, Specifications, Study of the
Data Sheet, Concept of Vcc and Ground, Verification of the Truth Tables of Logic Gates using
TTL ICs.
2 Realization the basic logic gates using universal logic gates (NAND & NOR).

3 Design and Implementation of adder and subtractor circuit using basic logic gates.

4 Implementation and Verification of Decoder using Logic Gates.

5

Implementation of 4x1 Multiplexer using Logic Gates.

Verification of State Tables of Rs, J-k, T and D Flip-Flops using NAND & NOR
Gates
7 Design, and Verify the 4-Bit Asynchronous Counter.

8 Simulation of MOS and CMOS Inverter with different loads using PSPICE software

9 Verification of the truth tables of logic gates using Xilinx software.

10 Design and Implementation of adder and subtractor circuit using Xilinx software

11 Design of a 4-bit Multiplexer using VHDL\Verilog

12 Implementation of Decoder Circuit and simulate its operation using Xilinx Software and VHDL
in behavioral model.

13 Design and simulation of JK Flip/Flop by using Xilinx.

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 Rubrics for Hardware Experiment

Each week, students will be assessed on their participation and performance in lab. The points
each week will be totaled and combined with other assessments/report writing.

Objectives:
Outcomes:

Overall Lab Performance (End of the Semester)

Lab participation – 40% of internal marks (i,e 16)
Assignments/Report Submission –60% of internal marks (24)

A: Lab performance is excellent with the majority of assessments rated as proficient. The
student has attended all labs.

B: Lab performance is good with most assessments at the adequate level (with no more than
2 substandard) or above. At most, the student has one lab absence.

C: Lab performance is fair with most assessments at the Adequate and substandard levels.
The student may have been absent 2-3 times.

D: Lab performance is barely adequate with less than half of assessments at the Adequate
level or higher. The student may have been absent up 40% of total experiments.

E: Lab performance is not sufficient to pass since 50% of assignments were not completed
(or unacceptable) and/or the student missed more than 50%

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Quality/Score Excellent (4) Good (3) Fair (2) Poor (1) Marks
Criteria
Lab Participation Student Student Student Student was
(Following Procedure demonstrates an arrives on unpreparedness absent from
+Lab Techniques+ accurate time to lab, makes it lab or did not
Subject Knowledge + understanding of but may be impossible to participate.
Contribution) the lab underprepar fully There was
objectives and ed. Answers participate. If no attempt to
concepts. They to questions able to make prior
can correctly are basic and participate, arrangements
answer questions superficial student has to make up
and if suggesting difficulty the lab.
appropriate, can that explaining key
explain concepts concepts are lab concepts.
to fellow not fully
classmates. grasped.
Lab Report Student Student has Student has Student turns
demonstrates an a basic problems with in lab report
accurate knowledge both the graphs late or the
understanding of of content, and the report is so
the lab but may lack answers. incomplete
objectives and some Student and/or so
concepts. understandin appears to have inaccurate
Questions are g of some not fully that it is
answered concepts. grasped the lab unacceptable
completely and Questions content and the
correctly. are graph(s)
Graphs are neat, answered possess
creative and fairly well multiple errors
include complete and/or
titles and graphs could
accurate units. have been
Errors, if any are done more
minimal neatly,
accurately or
with more
complete
information

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 Interaction with Very good Good Minimal No
Group (Team work) participation participation participation; participation;
with a good ; appears Shows little sits on the
leadership interested; interest; sidelines
quality; is enthusiastic doesn't pay with no
respectful of but talks attention to interaction;
others and theirover other group disinterested;
point of view; teammates; members; may No stake in
makes sure that try to help argue to get time
everyone gets a group point across; management
turn; conscious complete helps group
of time tasks; only when
somewhat asked; little
conscious of emphasis on
time time
Safety Proper safety Proper Proper safety Proper safety
precautions are safety precautions are precautions
consistently precautions often missed, are
followed. are generally consistently
followed missed;
Seldom
warned
Cleaning/Rearranging Placed all the Proper Needs to be Proper clean-
after experiment components as clean-up reminded more up
per instruction procedures than once procedures
after experiment; generally during the lab are seldom
Keep experiment followed. to use proper used.
station Station clean-up Requires
generally neat generally procedures. other’s help
and clean left clean. to complete
Consistently May need clean-up
uses proper reminding
clean-up occasionally
procedures; .
Reminds others
of their
responsibility.

Note: This document is a general guide line for a Particular Laboratory course (non
CSE/IT/MCA). It will be kept with the Laboratory manual. Teacher will complete the
Annexure after evaluation of each and every laboratory report and to be kept with student
Laboratory file.

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 Annexure

TECHNO MAIN, SALTLAKE

Name of Department: Name of Subject with code:

Name of the student: Roll No
Name of the experiment:

Objectives: Particular for the experiment (max 1-2 lines)

Quality/Score Excellent Good Fair Poor Marks

(4) (3) (2) (1)
Objective/Criteria

Lab Participation
Lab Report
Interaction with
Group
Safety
Cleaning/Rearrangi
ng after experiment
Total Marks with grade
20
+
Mark Evaluation Between 20-16 A (5)
Between 15-11 A (4)
Between 10-6 B+(3)
Between 5-0 B (2)
Comments:

Signature of Teacher with date:

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 EXPERIMENT -1
TITLE: - Introduction to digital electronics lab- nomenclature of digital ICs,
specifications, study of the data sheet, concept of Vcc and ground, verification of the
truth tables of logic gates using TTL ICs.

OBJECTIVE: - Introduction to digital electronics lab- nomenclature of digital ICs,

specifications, study of the data sheet, concept of Vcc and ground, verification of the
truth tables of logic gates using TTL ICs.

LIST OF EQUIPMENTS:
Power Supply, single strand wires, breadboard, Multi-meter, TTL IC’s

Gates IC NO.

AND 74LS08

OR 74LS32

NAND 74LS00

NOR 74LS02

NOT 74LS04

XOR 74LS86

THEORY:- Digital system are said to be constructed by using logic gates. Digital
electronics relies on the actions of just seven types of logic gates, called AND, OR,
NAND (Not AND), NOR (Not OR), XOR (Exclusive OR) XNOR (Exclusive NOR)
and NOT. Because, in binary logic there are only two states, 1 and 0 or ‘on and off,’
NOT in the world of binary logic therefore means ‘the opposite of’. If something is
not 1 it must be 0, if it is not on, it must be off. So NAND (not AND) simply means
that a NAND gate performs the opposite function to an AND gate.

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A logic gate is a small transistor circuit. Each type of gate has one or more (most often
two) inputs and one output.

The principle of operation is that the circuit operates on just two voltage levels, called
logic 0 and logic 1. When either of these voltage levels is applied to the inputs, the
output of the gate responds by assuming a 1 or a 0 level, depending on the particular
logic of the gate. The logic rules for each type of gate can be described by a truth table.
The 7400 series is a popular set of logic ICs. 7400 chips are generally 14-pin or 16-
pin DIP packages, although other form factors are available as well.
The power supply required is +5V. For most of the 7400 chips, pin 7 is the ground
(GND) connection and pin 14 is the +5V power supply.

DATASHEET

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 Example of 7400
Series IC74LS00 Quad 2
input NAND gates
IC74LS02 Quad 2 input
NOR gates IC74LS04
Hex NOT gates
(Inverters)

IC74LS08 Quad 2 input

AND gates IC74LS32
Quad 2 input OR gates
IC 74LS86 Quad 2
input XOR gates

PIN CONFIGURATIONS AND TRUTH TABLE:-

Basic Gates:
AND gate: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement: -

Input Input Outpu

A B t
1 1 1
1 0 0
0 1 0
0 0 0

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 IC74L08

OR gate: - Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify
the statement:

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 1

IC74LS32
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NOT gate: -Function of NOR gate is to reverse the nature of the input .It converts
true input to false and vice versa. Following table justifies the statement :-

Input Output
(A) (B)
1 0
0 1

IC74LS04

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Universal Gates

NAND gate: -Function of NAND gate is to give true output when one of the two
provided input are false. In the remaining output is true case .Following table
justifies the statement :-

Input A Input B Output

1 1 0
1 0 1
0 1 1
0 0 1

IC 74LS00

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NOR gate: - NOR gate gives the output true when both the two provided
input are false. In all the other cases output remains false. Following table
justifies the statement :-

Input Input (B) Output

( A)
1 1 0
1 0 0
0 1 0
0 0 1

IC 74LS02

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Advanced Gates
1. XOR gate: - The function of XOR gate is to give output true only
when both the inputs are true. Following table explain this:-

Input A Input B Output

1 1 0
1 0 1
0 1 1
0 0 0

IC 74LS86

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 OBSERVATION TABLE:-
Inputs NOT AND OR NAND NOR XOR XNOR
A B Y=A Y=A.B Y=A+B Y=(A.B)’ Y=(A+B)’ Y=A(+)B Y=A(.)B
(Volts) (Volts) (Volts) (Volts) (Volts) (Volts) (Volts) (Volts) (Volts)

0.00 0.00
0.00 5.00
5.00 0.00
5.00 5.00

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:
1. What is the full form of TTL?
2. What is the significant of 74LS and Why Each gate started from74?
3. Which gate is called Hex Inverter and why?

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 EXPERIMENT -2
TITLE: Realization of basic gates using universal gates.
OBJECTIVE: To realize the basic logic gates using universal logic gates (NAND & NOR).

LIST OF EQUIPMENT:-

Sl. No. Name Make Model no. Specification

1. Regulated power ELNOVA E-61 0-30V, 2A;
supply ±3V,±15V,1A,5V,
5A
2. Logic probe Made in Model-625 50 MHz
Taiwan frequency range
3. Bread board

4. IC : 74LS00 (NAND) MOTOROLA 74LS00 IC

5. IC : 74LS02 (NOR) MOTOROLA 74LS02 IC
6. Connecting wire FINOLEX N/A N/A

THEORY::
NAND & NOR are called universal logic gates because they can be used to implement
any of the other gates (AND, OR, NOT, XOR, XNOR).
NAND GATE::
It is the complement of the AND of the inputs. It has two or more inputs and an output.
The output will be high if any or all of the inputs are low. Mathematically it can be defined as
Y=(A.B)’ .

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NOR GATE::
It is the complement of OR of the inputs. It has two or more inputs and an output. The
output will be low if any or all of the inputs are high. Mathematically it can be defined as Y=
(A+B)’.
Implementation of various logic gates are shown below with corresponding TRUTH
TABLE.

CIRCUIT DIAGRAM:
NOT GATE:

TRUTH
TABLE
Logic symbol: Y=A’ A Y=A’
O 1
1 0

Using NAND gate:

Using NOR gate:

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AND GATE:

Logic symbol: Y=A.B

Using NAND gate:

Using NOR gate:

TRUTH TABLE
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

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OR GATE::

TRUTH TABLE
A B Y=A+B
0 0 0
0 1 1

Logical symbol: 1 0 1
1 1 1
Y=A+B

Using NAND gate:

Using NOR gate:

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NAND GATE:

Logical symbol
TRUTH TABLE
A B Y=(A.B)’
0 0 1
0 1 1
1 0 1
1 1 0

Y=(A.B)’

Using NOR gate:

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NOR GATE::

Logical symbol:
TRUTH TABLE
A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Y=(A+B)’

Using NAND gate:

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XOR GATE::

Logic symbol: Y=A(+)B

TRUTH TABLE
A B Y=A(+)B
0 0 0
0 1 1
1 0 1
Using NAND gate: 1 1 0

Using NOR gate:

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X-NOR GATE:

Logic symbol: Y= Y=A⊙B

TRUTH TABLE
A B Y=A⊙B
Using NAND gate: 0 0 1
0 1 0
1 0 0
1 1 1

Using NOR gate:

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OBSERVATION TABLE::
In the table given below we shall see that the behavior of the gates tallies totally with the
experimental results.

Inputs NOT AND OR NAND NOR XOR XNOR

A B Y=A’ Y=A.B Y=A+B Y=(A.B)’ Y=(A+B)’ Y=A(+)B Y=A(.)B

L L H L L H H L H
L H L H H L H L
H L L L H H L H L
H H H H L L L H

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:

1. Which gate is called Universal gate?

2. Why NAND and NOR is called universal gates?
3. Show the pin configuration of IC 74LS02 &IC 74LS00

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 EXPERIMENT-3

TITLE: Implementation of half adder, full adder ,half substractor and full subtractor using logic
gates.

OBJECTIVE: To realize the operation of adder and subtractor circuit using basic logic gates.

LIST OF MAJOR EQUIPMENTS:

Sl Name Manufacturer Model No Specification
No.

1. Power ELNOVA/ E-61 S1:0-30V, S2:0-2V,

Supply Aplab S3:5V,5A

2. Logic Probe Made in Taiwan Model-625 50 MHz freq. range

THEORY:
A combinational circuit that performs the addition of 2 bits is called the half adder. One that
performs the addition of three bits is called a full adder.
A half adder has 2 inputs and 2 outputs. The output variables produce the sum and carry.
In full adder two input variables A and B represents the two significant bits to be added. The third
input C represents the carry from the previous lower significant position. It has two outputs sum and
carry.
A half sub tractor is a combinational circuit that subtracts two bits. It has two inputs and two outputs.
The output variables produce difference and borrow. A full subtractor is a combinational circuit that
performs subtraction between two bits taking into account one may have been borrowed by a lower
significant stage. It has three inputs and two outputs.

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CIRCUIT DIAGRAM:

half adder

NOTE: give the Boolean expression for SUM and CARRY by yourself.

full adder
NOTE: give the Boolean expression for SUM and CARRY by yourself.

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 Half Sustractor

full subtractor
NOTE: give the Boolean expression for DIFFERENCE and BORROW by yourself.

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Truth table for Half adder and Full Adder:
half adder
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

A B Cin SUM CARRY

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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 Truth table for Half substractor

X Y Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Truth table for full substractor

X Y Bin DIFF Borrow

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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Observation table for half adder and half subtractor:

A B SUM CARRY
L L L L
L H H L
H L H L
H H L H

X Y DIFF Borrow
L L L L
L H H H
H L H L
H H L L

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Observation table for full adder and full subtractor:

Full adder

A B Cin Sum Carry

L L L L L
L L H H L
L H L H L
L H H L H
H L L H L
H L H L H
H H L L H
H H H H H

Full subtractor

A B Cin Diff Borrow

L L L L L
L L H H H
L H L H H
L H H L H
H L L H L
H L H L L
H H L L L
H H H H H

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K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

For Full Adder

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

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K-Map for CARRY:

CARRY = AB + BC + AC
For Half Subtractor

K-Map for difference:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

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For full Subtractor
K-Map for Difference:

Difference = A’B’C + A’

BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

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CONCLUSION : Student will write conclusion in their own words.

VIVA QUESTIONS:
1. Can we construct a full adder and full subtractor circuit using universal gates?

2. What are the uses of full adder and full subtractor circuit?

3. What is the boolean expression of full adder and full subtraction.

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 EXPERIMENT NO.- 4

TITLE :- Construction of simple decoder .

OBJECT :- To construct a simple decoder & to show its operation.

LIST OF EQUIPMENTS :

Sl No. Name Manufacturer Model No. Specification

1 Regulated DC ELNOVA E-61 5V, 5A

power Supply
2 Logic Probe Taiwan Make Model-625 50MHz Frequency
Range

THEORY :-
A decoder is a combinational logic circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines.
A 2 to 4 decoder is a combinational logic circuit that takes two input lines, typically labeled S0
and S1, and generates four output lines, usually labeled D0, D1, D2, and D3. The decoder
analyzes the input combination and activates the corresponding output.

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CIRCUIT DIAGRAM:

2:4 Decoder

42
PROCEDURE:
1. Fix the required IC chips i.e.74LS32,74LS04 and 74LS08 on the bread board.
2. Connect pin no. 14 of each chip to +Vcc and pin no.7 of each chip to ground.
3. Make the other required connections as shown in the circuit diagram.
4. Verify the output and write it in the observation table.

Truth table :-
1:2 Decoder
Inputs Enable Outputs
A E Y0 Y1
X 0 0 0
0 1 1 0
1 1 0 1

2:4 Decoder

INPUT LINES ENABLE OUTPUT LINES

A B E I0 I1 I2 I3
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

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OBSERVATION TABLE :
1:2 Decoder

Input Enable Output

A E Y0 Y0
L L L L
H L L L
L H H L
H H L H

2:4 Decoder

Input lines Enable Output lines

A B E I0 I1 I2 I3
L L H H L L L
L H H L H L L
H L H L L H L
H H H L L L H

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTION:
1. What are the use of DECODER circuit in practical?
2. What is an example of a decoder in real life?
3. How to implement 4 16 decoder using 3 8 decoder?

44
 EXPERIMENT NO:-5(a)

TITLE :- Construction of multiplexer circuits using basic logic gates.

OBJECT :- To construct multiplexer circuit using logic gates & to show its operation.

LIST OF EQUIPMENT’S :-
Sl No. Name Manufacturer Model No. Specification

1 Regulated ELNOVA E-61 5V, 5A

DC power
Supply
2 Logic Taiwan Make Model-625 50MHz Frequency
Probe Range

THEORY :-
Multiplexing is the process of transmitting a large number of information over a single line. A
multiplexer is a combinational logic circuit which has 2n input line, n select and only one output
line. The selection of a particular input line is controlled by the set of select line. It determines
which inputs will go to the output.

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CIRCUIT DIAGRAM:-

4:1 MUX

Truth table :
INPUT DATA LINES SELECT LINES OUTPUT
I0 I1 I2 I3 S0 S1 Y
1 0 0 0 0 0 1
0 1 0 0 0 1 1
0 0 1 0 1 0 1
0 0 0 1 1 1 1

46
 CONCLUSION .: Student will write conclusion in their own words.

VIVA QUESTIONS:
1. What are the use of MULTIPLEXER circuit in practical?
2. Why Multiplexer is called Data selector?

3. How many select line are required for 16:1?

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 EXPERIMENT:-(5b)

1. TITLE:- Design of combinational circuit using multiplexer.

OBJECTIVE:
1) To implement a Boolean function using 8:1 MUX chip.
2) To implement full adder and full subtractor using 4:1 MUX chip.
3) To implement logic gates using 2:1 MUX chip.

LIST OF MAJOR EQUIPMENT’S:

Sl Name Manufacturer Model Specification

No. No.
1 Regulated ELNOVA E-61 5V, 5A
DC
power
Supply
2 Logic Taiwan Make Model- 50MHz
Probe 625 Frequency
Range

THEORY:
Adigital multiplexer is a combinational circuit that selects binary information from one of the
many input lines and directs it to a single line.The selection of a particular input line is controlled
by a set of selection lines.Normally there are 2n input lines and n selection lines whose bit
combination determine which input is selected.

74LS151 is a 8:1 MUX chip.

74LS153 is a 4:1 MUX chip.
74LS157 is a 2:1 MUX chip.

1) Implement F(A,B,C,D) = (0,1,3,4,8,9,15) using 8:1 MUX.

48
TRUTH TABLE:

A B C D OUTPUT
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

Implementation Table:

I0 I1 I2 I3 I4 I5 I6 I7
Ᾱ 0 1 2 3 4 5 6 7
15
A 8 9 10 11 12 13 14

1 1 0 Ᾱ Ᾱ 0 0 A

49
Pin Configuration of 8:1 MUX.

CIRCUIT DIAGRAM:

PROCEDURE:

a) Fix the required chips i.e. 74LS151 and 74LS04 on the breadboard.
b) Connect pin np. 16 of both the chips to +Vcc and pin no. 8 to ground.
c) Make the other required connections as shown in the circuit diagram.
d) Verify the output and write the observation table.

50
OBSERVATION TABLE:

A B C D OUTPUT

2) Implement a Full Adder using 4:1 MUX.

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Implementation Table:

Sum:

I0 I1 I2 I3
Ᾱ 0 1 2 3
A 4 5 6 7
A Ᾱ Ᾱ A

Carry:

I0 I1 I2 I3
Ᾱ 0 1 2 3

A 4 5 6 7
0 A A 1

51
 Pin Configuration of Dual 4:1 MUX:

CIRCUIT DIAGRAM:

PROCEDURE:
a) Fix the required chips i.e. 74LS153 and 74LS04 on the breadboard.
b)Connect pin no. 16 of both the chips to +Vcc and pin no. 8 to ground.
c) Make the other required connections as shown in the circuit diagram.
d) Verify the output and write the observation table.
52
Observation Table:

A B C SUM CARRY

3) To implement logic gates using 2:1 MUX.

A) Truth Table of NAND gate:

A B OUTPUT
0 0 1
0 1 1
1 0 1
1 1 0

Implementation Table:

I0 I1
Ᾱ 0 1

A 2 3
1 Ᾱ

53
 Pin Configuration of Quad 2:1 MUX:

CIRCUIT DIAGRAM:

B) Truth Table of OR gate:

A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 1

54
Implementation Table:

I0 I1
Ᾱ 0 1

A 2 3
1 Ᾱ

CIRCUIT DIAGRAM:

PROCEDURE:
a) Fix the required chips i.e. 74LS157 and 74LS04 on the breadboard.
b) Connect pin no. 16 of both the chips to +Vcc and pin no. 8 to ground.
c) Make the other required connections as shown in the circuit diagram.
d) Verify the output and write the observation table.

55
OBSERVATION TABLE:

A B OUTPUT

***By using the above procedure implement other gates like NOT, AND, NOR, X-OR, X-
NOR and a Full Subtractor.

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:
1) Construct a 8:1 MUX using two 4:1 MUX.
2) Implement a full subtractor using 4:1 MUX.
3) Where we should be connected enable pin,ISTR, and 2STR pin?

56
 EXPERIMENT-6

TITLE:- Realization of RS, JK and D flip flop using universal logic gates.
OBJECTIVE: To implement RS, JK and D flip flop using NAND gates.

EQUIPMENTS:

Sl Name Manufacturer Model Specification

No. No.
1 Regulated ELNOVA E-61 5V, 5A
DC
power
Supply
2 Logic Taiwan Make Model- 50MHz
Probe 625 Frequency
Range

THEORY:
Flip Flops are memory elements capable of storing one bit of information. A flip flop circuit can
maintain a binary state indefinitely until directed by an input signal to switch states. A flip flop
has two states. A flip flop has two states i.e. set state when Q=1 and reset when Q=1.There are
different types of flip flops like RS,JK, D and T flip flops.

Preset (Pr) and Clear (Cr) inputs are called asynchronous inputs.

When Pr=1 and Cr=1 circuit will operate as normal flip flops.
When Pr=1 and Cr=0 the flop flop will reset.
When Pr=0 and Cr=1 the flip flop will set.
The condition Pr=Cr=0 must not be used since, this leads to uncertain state.

57
 RS FLIP FLOP: Clocked RS flip flop consists of four NAND gates. When the clock input
is low the output remains unchanged. When the clock input is high, output changes
according to values of the present.

 JK FLIP FLOP: JK flip flop is a refinement of an RS flip flop. The undefined states in a
SR flip flop are defined in a JK flip flop.

 D FLIP FLOP:D flip flop receives its designation from its ability to transfer data into a
flip flop. It is basically. An SR flip flop with an inverter at the R input.

CIRCUIT DIAGRAM:-

7410 3-input NAND gate

58
SR FLIP FLOP

JK FLIP FLOP

59
Truth Table:

a)RS flip flop

Clock Preset Clear S R Qn Qn+1 .

CK
Pr Cr Qn+1

1 1 1 0 0 0 0 1
(previous
condition)

1 1 1 0 0 1 1 0
(previous
condition)

1 1 1 0 1 0 0 1

1 1 1 0 1 1 0 1

1 1 1 1 0 0 1 0

1 1 1 1 0 1 1 0

1 1 1 1 1 0 undefined undefined

1 1 1 1 1 1 undefined undefined

60
b) JK flip flop

Clock Preset Clear J K Qn Qn+1 .

CK
Pr Cr Qn+1

1 1 1 0 0 0 0 1
(previous
condition)

1 1 1 0 0 1 1 0
(previous
condition)

1 1 1 0 1 0 0 1

1 1 1 0 1 1 0 1

1 1 1 1 0 0 1 0

1 1 1 1 0 1 1 0

1 1 1 1 1 0 1 (Toggle 0
State)

1 1 1 1 1 1 0 (Toggle 1
State)

61
c)D flip flop
Clear D Qn _
Clock Preset Qn+1
Cr Qn+1
Pr
CLK

1 1 1 0 0 0 1

1 1 1 0 1 0 1

1 1 1 1 0 1 0

1 1 1 1 1 1 0

OBSERVATION TABLE:
a)RS flip flop
Clock Preset Clear Qn+1 .
CK S R Qn
Pr Cr Qn+1

H H H L L L L H

H H H L L H H L

H H H L H L L H

H H H L H H L H

H H H H L L H L

H H H H L H H L

H H H H H L H H
(undefined) (undefined)

H H H H H H H H
(undefined) (undefined)

62
OBSERVATION TABLE:
b) JK flip flop

Clock Preset Clear J K Qn Qn+1 .

CK
Pr Cr Qn+1

H H H L L L L H
(previous
condition)

H H H L L H H L
(previous
condition)

H H H L H L L H

H H H L H H L H

H H H H L L H L

H H H H L H H L

H H H H H L H L
(Toggle
State)

H H H H H H L (Toggle H
State)

63
c)D flip flop

OBSERVATION TABLE:
Qn _
Clock Preset Clear D Qn+1
Qn+1
Pr
CLK Cr

H H H L L L H

H H H L H L H

H H H H L H L

H H H H H H L

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:-
1. What is Latch?
2. What is the difference between combinational and sequential ckt.?
3. How a RS F/F is converted in a D F/F?

64
 EXPERIMENT -7

TITLE:- Realization of Asynchronous up/down counter.

OBJECTIVE:- To realize 2-bit Asynchronous UP/DOWN counter using JK FLIP-FLOP.

LIST OF MAJOR EQUIPMENTS

SL NO. NAME MANUFACTURE MODEL SPECIFICATIONS

R
NO.
1 115W POWER ELNOVA E-61 0-30V, 0-2V,
SUPPLY
5V , 5A
2 20 MHz Pulse SCIENTECH HM503 20 MHz
Generator 5

THEORY:-
A counter is a circuit used for counting the number of pulses. There are two types of counters-
asynchronous counter and synchronous counter. In synchronous counter all the flip-flops are
clocked simultaneously.
A counter can count in the UP direction i.e. the decimal equivalent of the counter output
increases with successive clock pulses. It is also possible to make a counter in which the decimal
equivalent of the counter output decreases with successive clock pulses i.e. the counting process
in the DOWN direction. The former is referred to as an UP counter and later as a DOWN
counter.
The UP/DOWN operation can be combined in one circuit. A Synchronous UP/DOWN counter is
one which can count both in UP/DOWN direction depending on the status of the control input.

65
SEQUENCE OF COUNTER:

CONTROL SIGNAL OUTPUTS COUNTS

DOWN UP Q1 Q0 STATE

0 1 0 0 0
0 1 0 1 1
0 1 1 0 2
0 1 1 1 3
1 0 1 1 3
1 0 1 0 2
1 0 0 1 1
1 0 0 0 0
OBSERVATION TABLE:

CONTROL SIGNAL OUTPUTS COUNTS

DOWN UP Q1 Q0 STATE

L H L L 0
L H L H 1
L H H L 2
L H H H 3
H L H H 3
H L H L 2
H L L H 1
H L L L 0
66
JK FLIP FLOP

67
CIRCUIT DIAGRAM FOR 2-BIT ASYNCHRONOUS UP/DOWN COUNTER

FOR UP COUNTING->UP=1 &DOWN=0

FOR DOWN COUNTING->UP=0 &DOWN=1

68
TIMING DIAGRAM FOR 2-BIT ASYNCHRONOUS UP COUNTER

TIMING DIAGRAM FOR 2-BIT ASYNCHRONOUS DOWN COUNTER

69
 CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:
1.What is the difference between Synchronous and Asynchronous counter?
2.Draw the Timing diagram for down counter.
3. what do you mean by clock triggering?
4. What are the different types of clock trigger?

70
 EXPERIMENT NO:-8

TITLE: Simulation of NMOS Invertor using PSPICE.

OBJECTIVE: Simulation of NMOS Inverter using different resistive load using PSPICE.

THEORY: As shown in the circuit diagram, the drain terminal is connected to the supply
voltage (Vdd) via a resistance (R). The source terminal is grounded and the input is given at the
gate terminal.
Now, when Gate is at logic 1 or high , the n-MOS is activated (turned on) and thus a low
resistance path is generated from vdd to ground. So, the output voltage is negligibly low or is at
logic ‘0’. Similarly when Gate is at logic ‘0’ or low, n-MOS remain off, so vout is directly
connected to vdd, hence it is at logic high. So, whatever is the input the gate terminal, the
inverted or complementary output is obtained at the output terminal.

TRUTH TABLE:
INPUT(A) OUTPUT(A̅)=Y
0 1
1 0

71
CIRCUIT DIAGRAM:

BOOLEAN EXPRESSION: Y= A̅ (A→input)

PSPICE PROGRAM:
INVERTER
VDD 2 0 DC 5V
VIN 1 0 DC 0V
R 3 2 1000
Mn 3 1 0 0 nMOD W=4 μ L=10 μ
 Dc VIN 0V 5V .25V
 Model nMOD nMOD (Vto=1 KP= .25)
 Plot dc v(3)
 Probe
 End

72
OUTPUT WAVEFORM:

CONCLUSION .; Student will write conclusion in their own words.

VIVA QUESTIONS:

1. What is the Significant of .probe command?

2. Explain the line . Dc VIN 0V 5V .25V from the program.
3. What is Vto?

73
 EXPERIMENT NO-9

TITLE: Design and simulation of XOR gate using Xilinx.

OBJECTIVE: To design XOR gate and simulate its operation using Xilinx Software and
VHDL in dataflow model.

THEORY:
XOR gates have two inputs and one output and they implement the special Boolean logic of
inequality detection. The EXOR gate gives a high output every time it detects an inequality in
the inputs. Its equation is as follows Y (A xor B) = AB’ + A’B

This can be implemented using VHDL codes and can be simulated using a Verilog
program. It is verified by matching the output waveform with theoretical
knowledge.

74
VHDL PROGRAM:
entity XOR1 is
port(a: in STD_LOGIC;b: in STD_LOGIC;c: out STD_LOGIC;);
end XOR1;
architecture dataflow of XOR1 is
begin
c<=a XOR b;
end dataflow;

VERILOG PROGRAM:
Module XOR1
Reg a;
Reg b;
wire c;
XOR1 uut (a(a);b(b);c(c););
Initial begin
a=0;
b=0;
#100;
a=0;
b=1;

75
 #100
a=1;
b=0;
#100
a=1;
b=1;
#100
End;
End module;

OUTPUT WAVEFORM:

76
CONCLUSION : Student will write conclusion in their own words.

VIVA QUESTIONS:

1. Which Symbol is used to end all VHDL statements?

2. What part of a declaration define a literal constant in an entity block?
3. What is the data type of Std_logic in VHDL?

77
 EXPERIMENT NO-10

TITLE: Design and simulation of Half Adder using Xilinx.

OBJECTIVE: To design Half Adder and simulate its operation using Xilinx Software and
VHDL in dataflow model.

THEORY:

S=A XOR B;
C=A AND B;

CIRCUIT DIAGRAM:

78
Truth Table:

Half adder
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

This can be implemented using VHDL codes and can be simulated using a Verilog program. It is
verified by matching the output waveform with theoretical knowledge.

VHDL PROGRAM:
entity HA is
port(a: in STD_LOGIC;b: in STD_LOGIC;S: out STD_LOGIC;
C: out STD_LOGIC;);
end HA;
architecture dataflow of XOR1 is
Begin
S<=a XOR b;
C<=a AND b;
end dataflow;

79
VERILOG PROGRAM:
Module HA
Reg a;
Reg b;
Wire s;
Wire c;
XOR1 uut (.a(a);.b(b);.C(C);.S(S));
Initial begin
a=0;
b=0;
#100;
a=0;
b=1;
#100
a=1;
b=0;
#100
a=1;
b=1;
#100
End;
End module;

80
OUTPUT WAVEFORM:

CONCLUSION : Student will write conclusion in their own words

VIVA QUESTIONS:

1. Explain what is Verilog?

2. What is the basic building unit of a VHDL design?
3. What do all VHDL designs begin with?
4.What is the difference between simulation and synthesis?
5 Which block describes a design’s behavior?

81
 EXPERIMENT NO-11

TITLE: Design and simulation of 4:1 MUX using Xilinx.

OBJECTIVE: To design 4:1 MUX and simulate its operation using Xilinx Software and
VHDL in behavioral model.

THEORY:
A multiplexer is a data selector. It has multiple inputs, out of which it selects one and connects
that one to the output. This selection is done on the basis of the values of the select inputs. In this
program, we will write the VHDL code for a 4:1 Mux. A 4:1 mux will have two select inputs.
Since we are using behavioral architecture, it is necessary to understand and implement the logic
circuit’s truth table.

82
Truth table of a 4:1 Mux:

I0 I1 I2 I3 S0 S1 Y

I0 x x x 0 0 I0

x I1 x x 0 1 I1

x x I2 x 1 0 I2

x x x I3 1 1 I3

VHDL PROGRAM:
entity MUX_SOURCE is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
I : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC);
end MUX_SOURCE;
architecture Behavioral of MUX_SOURCE is
begin
process (S,I)
begin
if (S <= "00") then

83
Y <= I(0);
elsif (S <= "01") then
Y <= I(1);
elsif (S <= "10") then
Y <= I(2);
else
Y <= I(3);
end if;
end process;

end Behavioral;

VERILOG PROGRAM:
module MUX_SOURCE;
reg [3:0] a;
reg [3:0] b;
reg [3:0] c;
reg [3:0] d;
wire [3:0] out;
reg [1:0] sel;
integer i;
MUX_SOURCE mux0 ( .a (a),
.b (b),
.c (c),
.d (d),
.sel (sel),
.out (out));

84
initial begin
// Launch a monitor in background to display values to log whenever a/b/c/d/sel/out changes//
$monitor ("[%0t] sel=0x%0h a=0x%0h b=0x%0h c=0x%0h d=0x%0h out=0x%0h", $time, sel, a,
b, c, d, out);

// 1. At time 0, drive random values to a/b/c/d and keep sel = 0

sel <= 0;
a <= $random;
b <= $random;
c <= $random;
d <= $random;

// 2. Change the value of sel after every 5ns

for (i = 1; i < 4; i=i+1) begin
#5 sel <= i;
end

// 3. After Step2 is over, wait for 5ns and finish simulation

#5 $finish;
end
end module

85
OUTPUT WAVEFORM:

CONCLUSION : Student will write conclusion in their own words.

VIVA QUESTIONS:
1. What is VHDL?
2. Are Verilog/vhdl Concurrent Or Sequential Language In Nature? ...
3. What is multiplexer in VHDl?

86
 EXPERIMENT NO-12

TITLE: Implementation of Decoder.

OBJECTIVE: To design Decoder Circuit and simulate its operation using Xilinx Software
and VHDL in behavioral model.

THEORY:
A decoder is a combinational logic circuit that converts binary information from ‘n’ input lines
to a maximum of 2n unique output lines.

CIRCUIT DIAGRAM:

87
VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder2to4 is
Port ( a : in
STD_LOGIC;
b : in STD_LOGIC;
z0 : out
STD_LOGIC; z1 :
out STD_LOGIC;
z2 : out
STD_LOGIC; z3 :
out

88
 STD_LOGIC);
end decoder2to4;

architecture Behavioral of decoder2to4 is

begin
process(a,b)is
begin
if(a<='0' and b<='0')
then z0<='1';
z1<='0';
z2<='0';
z3<='0';

else if (a<='0' and b<='1') then

z0<='0';
z1<='1';
z2<='0';

z3<='0';

else if (a<='1' and b<='0')

then z0<='0';
z1<='0';

89
 z2<='1';
z3<='0';

elsif (a<='1' and b<='1')

then z0<='0';
z1<='0';
z2<='0';
z3<='1';
end if;
end process;

end Behavioral;

VERILOG CODE:

module decoder2to1;

//
Inputs
reg a;
reg b;
// Outputs wire z0; wire z1; wire z2; wire z3;

// Instantiate the Unit Under Test (UUT)

decoder2to4 uut (
90
 .a(a),
.b(b),
.z0(z0),
.z1(z1),
.z2(z2),
.z3(z3)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 0;
b = 1;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs

91
a = 1;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Initialize Inputs
a = 1;
b = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

End module;

92
OUTPUT WAVEFORM:

CONCLUSION : Student will write conclusion in their own words.

VIVA QUESTIONS:
1. What are the IEEE STD-LOGIC_1164 data type for single logic signals and Buses?
2. What are the numerical data type?
3. What are the only two values for a Boolean type?

93
 EXPERIMENT NO.-13

TITLE: Design and simulation of JK Flip/Flop by using Xilinx.

OBJECTIVE: To design JK Flip/Flop and simulate its operation using Xilinx Software and
VHDL in behavioral model.

THEORY:
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop
(note that in a JK flip-flop, the letter J is for set and the letter K is for clear). We will write the
VHDL code for a JK Flip/Flop.

CIRCUIT DIAGRAM:

94
Truth table of a JK Flip/Flop:

JK flip flop

Clock Preset Clear J K Qn Qn+1 .

CK
Pr Cr Qn+1

1 1 1 0 0 0 0 1
(previous
condition)

1 1 1 0 0 1 1 0
(previous
condition)

1 1 1 0 1 0 0 1

1 1 1 0 1 1 0 1

1 1 1 1 0 0 1 0

1 1 1 1 0 1 1 0

1 1 1 1 1 0 1 (Toggle 0
State)

1 1 1 1 1 1 0 (Toggle 1
State)

95
VHDL Code:
entity jjff is
Port ( j : in
STD_L
OGIC; k
: in
STD_L
OGIC;
q1 : in
STD_L
OGIC; c
: in
STD_L
OGIC;
q2 : out STD_LOGIC);
end jjff;

architecture Behavioral

of jjff is begin
process(
j,k,q1,c)
is begin
if(j<='0' and k<='0' and q1<='0'
and c<='0') then q2<='0';
elsif(j<='0' and k<='0' and q1<='0'
and c<='1') then q2<='0';
elsif(j<='0' and k<='0' and q1<='1'
and c<='0') then q2<='0';
elsif(j<='0' and k<='0' and q1<='1'
and c<='1') then q2<='1';
elsif(j<='0' and k<='1' and q1<='0'
and c<='0') then q2<='0';
elsif(j<='0' and k<='1' and q1<='0'
and c<='1') then q2<='0';
elsif(j<='0' and k<='1' and q1<='1'
and c<='0') then q2<='0';
elsif(j<='0' and k<='1' and q1<='1'
and c<='1') then q2<='0';

96
 elsif(j<='1' and k<='0' and q1<='0'
and c<='0') then q2<='0';
elsif(j<='1' and k<='0' and q1<='0'
and c<='1') then q2<='1';
elsif(j<='1' and k<='0' and q1<='1'
and c<='0') then q2<='0';
elsif(j<='1' and k<='0' and q1<='1'
and c<='1') then q2<='1';
elsif(j<='1' and k<='1' and q1<='0'
and c<='0') then q2<='0';
elsif(j<='1' and k<='1' and q1<='0'
and c<='1') then q2<='1';
elsif(j<='1' and k<='1' and q1<='1'
and c<='0') then q2<='0';
elsif(j<='1' and k<='1' and q1<='1' and c<='1') then

q2<='0';
end if;
end process; end Behavioral;

VERILOG Code
module JKFF;
//
Inputs
reg j;
reg k;
reg q1;
reg c;
// Outputs wire q2; j j f f u u t

(
.j(j),
.k(k),
.q1(q1),
.c(c),
.q2(q2)
);
97
j = 0;
k = 0;
q1 = 0;
c = 0;
#100;
j = 0;
k = 0;
q1 = 0;
c = 1;
#100;
j = 0;
k = 0;
q1 = 1;
c = 0;
#100;
j = 0;
k = 0;
q1 = 1;
c = 1;
#100;
j = 0;
k = 1;
q1 = 0;
c = 0;

#100;

j = 0;
k = 1;
q1 = 0;
c = 1;

#100;
j = 0;
k = 1;
q1 = 1;
c = 0;

#100;
j = 0;

98
k = 1;
q1 = 1;
c = 1;

#100;
j = 1;
k = 0;
q1 = 0;
c = 0;

#100;
j = 1;
k = 0;
q1 = 0;
c = 1;

#100;
j = 1;
k = 0;
q1 = 1;
c = 0;

#100;
j = 1;
k = 0;
q1 = 1;
c = 1;
#100;
j = 1;
k = 1;
q1 = 0;
c = 0;
#100;
j = 1;
k = 1;
q1 = 0;
c = 1;
#100;

99
 j = 1;
k = 1;
q1 = 1;
c = 0;
#100;
j = 1;
k = 1;
q1 = 1;
c = 1;
#100;
End module;

WAVEFORM:

CONCLUSION : Student will write conclusion in their own words.

VIVA QUESTIONS:-
1. Why is it called JK flip flop?
2. What is the condition on JK F/F to work as D F/F?
3. How to calculate output of JK flip flop?

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