Hindusthan College of Engineering and Technology
An Autonomous Institution, Approved by AICTE, New Delhi, Affiliated to Anna
University,Chennai Accredited by NBA (AERO, AUTO, CIVIL, CSE, ECE, EEE, IT,
MECH, MECHATRONICS) Accredited by NAAC with ‘A++’ Grade, An ISO Certified
InstitutionValley Campus, Coimbatore – 641 032, Tamil Nadu, INDIA
DEPARTMENT OF ELECTRONICS AND
COMMUNICATION
DESIGN AND SIMULATION OF AN NFC
COMMUNICATION MODULE FOR VLSI SYSTEM
PROJECT REPORT
Submitted by
NIVETHA P
720723106068
OBJECTIVE
To design, implement, and simulate a compact and energy-
efficient NFC (Near Field Communication) communication
module tailored for VLSI systems, enabling secure short-range
wireless data exchange. This project aims to develop a modular
and scalable architecture optimized for integration into SoCs
and smart embedded systems, with real-time simulation and
validation using HDL tools like Xilinx Vivado.
INTRODUCTION
Near Field Communication (NFC) is a short-range wireless
technology widely used for secure data exchange in smart
devices. Integrating NFC into VLSI systems enables seamless
communication in applications like contactless payments,
smart packaging, and secure authentication. This project
focuses on designing and simulating a compact NFC
communication module using HDL, optimized for low power
and high efficiency, making it suitable for integration into
modern VLSI-based embedded systems.
BLOCK DIAGRAM
TRUTH TABLE
CODING
MAIN MODULE:
module nfc_controller (
input wire clk,
input wire rst,
input wire enable,
input wire [7:0] tx_data,
output reg tx_done,
output reg [7:0] rx_data,
output reg rx_valid
);
reg [3:0] state;
localparam IDLE = 0, TX = 1, RX = 2, DONE = 3;
always @ (posedge clk or posedge rst) begin
if (rst) begin
state <= IDLE;
tx_done <= 0;
rx_valid <= 0;
rx_data <= 8'b0;
end else begin
case (state)
IDLE: begin
tx_done <= 0;
if (enable) state <= TX;
end
TX: begin
// Simulate transmission delay
tx_done <= 1;
state <= RX;
end
RX: begin
// Simulate reception
rx_data <= tx_data ^ 8'hFF; // Mock processing
rx_valid <= 1;
state <= DONE;
end
DONE: begin
tx_done <= 0;
rx_valid <= 0;
state <= IDLE;
end
endcase
end
endmodule
TESTBENCH:
`timescale 1ns/1ps
module tb_nfc_controller;
reg clk;
reg rst;
reg enable;
reg [7:0] tx_data;
wire tx_done;
wire [7:0] rx_data;
wire rx_valid;
// Instantiate module
nfc_controller uut (
.clk(clk),
.rst(rst),
.enable(enable),
.tx_data(tx_data),
.tx_done(tx_done),
.rx_data(rx_data),
.rx_valid(rx_valid)
);
// Clock generation
always #5 clk = ~clk;
initial begin
clk = 0;
rst = 1;
enable = 0;
tx_data = 8'hA5;
#20 rst = 0;
#10 enable = 1;
#10 enable = 0;
#100 $finish;
end
initial begin
$monitor("Time=%0t | TX=%h | TX_DONE=%b |
RX=%h | RX_VALID=%b",
$time, tx_data, tx_done, rx_data, rx_valid);
end
endmodule
CONSTRAIN FILE:
## Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
## Reset
set_property PACKAGE_PIN V4 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
## Enable
set_property PACKAGE_PIN T4 [get_ports enable]
set_property IOSTANDARD LVCMOS33 [get_ports enable]
## tx_data[7:0]
set_property PACKAGE_PIN U7 [get_ports {tx_data[0]}]
set_property PACKAGE_PIN U8 [get_ports {tx_data[1]}]
set_property PACKAGE_PIN V8 [get_ports {tx_data[2]}]
set_property PACKAGE_PIN W8 [get_ports {tx_data[3]}]
set_property PACKAGE_PIN Y7 [get_ports {tx_data[4]}]
set_property PACKAGE_PIN Y8 [get_ports {tx_data[5]}]
set_property PACKAGE_PIN W7 [get_ports {tx_data[6]}]
set_property PACKAGE_PIN V7 [get_ports {tx_data[7]}]
## tx_done
set_property PACKAGE_PIN U6 [get_ports tx_done]
set_property IOSTANDARD LVCMOS33 [get_ports tx_done]
## rx_data[7:0] — output pins, same style
## rx_valid
SIMULATION OUTPUT:
LINTER ELABORATED DESIGN:
SYNTHESIS OUTPUT:
SYNTHESIS SCHEMATIC OUTPUT:
POWER REPORT:
Old NFC Communication Module:
Size (PCB area): ~1000 to 5000 mm² (module + antenna)
Power Consumption: 10 mW to 100 mW (active mode)
Data Rate :106_424kbps
Operating Voltage&Security: 3.3V or 5V& Basics
Modern VLSI-Based NFC Communication Module
Design:
Size (PCB area): < 100 mm² (chip area, excluding antenna)
Power Consumption: < 1 mW (active), sub-µW (standby)
Data Rate: 424 kbps – 848 kbps
OperatingVoltage&Security: 1.2V – 1.8V&Advanced
CONCLUSION:
The design and simulation of an NFC Communication Module
for VLSI systems demonstrates the feasibility of integrating
secure, short-range wireless communication directly into
digital hardware. Through the use of Verilog HDL and
simulation in the vivado tool, the module was successfully
implemented with key functionalities such as read, write, data
exchange, and control logic handled via an FSM-based
architecture. The results confirm that such a system is not only
power-efficient and compact but also scalable for real-world
applications in IoT, secure authentication, and smart
packaging. This project lays the groundwork for further
enhancements, including encryption support and real-time
hardware interfacing.
