Modern Operating Systems
Fifth Edition
Chapter 5
Input /Output
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Overview
• Principles of I/O Hardware
• Principles of I/O Software
• I/O Devices
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Overview
• Principles of I/O Hardware
• Principles of I/O Software
• I/O Devices
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I/O Devices (1 of 2)
• Block devices (e.g., hard disks and SSDs)
– Stores information in fixed-size blocks
– Transfers are in units of entire blocks
– I/O occurs with random access (by block ID)
• Character devices (e.g., printers, network interfaces)
– No blocks, only stream of characters (or bytes)
– Not addressable, does not have any seek operation
– I/O occurs with sequential access
• Distinction is a bit blurred
– Is a tape drive a block or a character device?
– Some devices do not fit in this model, e.g. clocks
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Device Controller
• Located between actual device and computer
• Offers electronic interface in form of I/O registers
• R/W those registers to ask the controller to perform actions
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Example: Parallel Port
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Example: Parallel Port
Base:
0x278 → LPT1
0x2f8 → LPT2 Copyright © 2023, 2025, 2008 Pearson Education, Inc. All Rights Reserved
Example: USB
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Accessing I/O Registers
Port-mapped I/O (PMIO)
• I/O Registers are accessed via dedicated port numbers and special
instructions
inb ax, 0x278 # load value of I/O register
# 0x278 to register ax
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Accessing I/O Registers
Memory-mapped I/O (MMIO)
• I/O Registers are mapped into addresses of main memory and accessed like
memory
mov 0x278, ax # store value of ax
# to address 0x278
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Accessing I/O Registers
Hybrid (PMMIO + MMIO)
• Both implementation can coexist on a given architecture
• Example: x86
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PMIO Example (IBM PC)
Port range Summary
0x0000-0x001F The first legacy DMA controller, often used for transfers to floppies.
0x0020-0x0021 The first Programmable Interrupt Controller
0x0040-0x0047 The PIT (Programmable Interval Timer)
0x0060-0x0064 The "8042" PS/2 Controller or its predecessors,
dealing with keyboards and mice.
0x0070-0x0071 The CMOS and RTC registers
0x0080-0x008F The DMA (Page registers)
0x0092 The location of the fast A20 gate register
0x00A0-0x00A1 The second PIC
0x00C0-0x00DF The second DMA controller, often used for sound blasters
0x0170-0x0177 The secondary ATA hard disk controller.
0x01F0-0x01F7 The primary ATA hard disk controller.
0x0278-0x027A Parallel port
0x02F8-0x02FF Second parallel port
0x03B0-0x03DF The range used for the IBM VGA, its direct predecessors,
as well as any modern video card in legacy mode.
0x03F0-0x03F7 Floppy disk controller
0x03F8-0x03FF First serial port
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MMIO Example (OMAP 3)
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Quiz
What mechanism (PMIO vs. MMIO) is more flexible and
efficient to implement device access control for unprivileged
user processes?
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Waiting for I/O Requests…
We can now send commands to devices, but what if the requested operation
takes time?
• Most devices offer status bits in their registers to signal that a request has
been finished (and the error code)
• OS can poll this status bit (polling)
• Is this a good solution?
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Interrupts
• Device controller can trigger interrupts to signal that a I/O request is
complete
– For the device, this means simply changing the voltage on an electrical
interrupt line
• Each controller has interrupt vector assigned
– CPU runs vector-specific handler when int occurs
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Interrupts
• Different terminology used to describe interrupts
– Trap: deliberate action from a program
– Fault (exception): usually not deliberate
– Hardware interrupt: device such as printer or network sends a signal to
the CPU
• Interrupts can be precise or imprecise
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Data Exchange Between Device and CPU
• How do we transfer data from e.g., hard disk to memory?
– Program disk controller to read a sector
– Wait for interrupt
– Read sizeof(sector) bytes from I/O registers
– Repeat for next sector
• Problem?
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Data Exchange Between Device and CPU
• How do we transfer data from e.g., hard disk to memory?
– Program disk controller to read a sector
– Wait for interrupt
– Read sizeof(sector) bytes from I/O registers
– Repeat for next sector
• Problem?
– CPU cycles can be spent in a better way!
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Direct Memory Access (DMA)
• Solution:
– Let the hardware do the transfer via DMA!
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DMA Controller
• On ISA systems there was a dedicated DMA controller (third-party DMA)
• On PCI (and PCIe) systems each PCI device may become “Bus Master” and
perform DMA (first-party DMA)
– Device and DMA controller are combined
– Do you see a problem here?
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DMA Controller
• On ISA systems there was a dedicated DMA controller (third-party DMA)
• On PCI (and PCIe) systems each PCI device may become “Bus Master” and
perform DMA (first-party DMA)
– Device and DMA controller are combined
– Do you see a problem here?
– You have to trust your Hw (or use a I/O MMU)
• Note:
– Embedded systems still have dedicated DMA controller
– Disk controller still uses own buffers
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Quiz
You’re comparing the performance of two systems, both
using no interrupts for device data transfer, but one using
DMA + polling while the other system uses polling alone.
Do you expect comparable or different performance for the
two systems?
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Overview
• Principles of I/O Hardware
• Principles of I/O Software
• I/O Devices
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Principles of I/O Software
Issues:
• Device independence
• Uniform naming
• Error handling
• Buffering
• Synchronous versus asynchronous
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Principles of I/O Software
• Device independence
– I/O software provides abstraction over actual hardware
– Programs should not have to care about device particularities
• Uniform naming
– We don’t want to type ST6NM04 to address the first hard disk
– /dev/sda is better
– /mnt/movies even better
• Error handling
– Errors should be handled closest to their source
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Principles of I/O Software
• Buffering
– Networking: incoming packets have to be buffered
– Audio: buffering to avoid clicks
• Synchronous vs. asynchronous I/O
– Programs don’t want to deal with interrupts → OS turns async operations
into blocking operations
– Lower levels have to deal with interrupts, DMA, etc.
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I/O Software Layers
Figure 5-11. Layers of the I/O software system.
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Layers of I/O Software
Figure 5-17. Layers of the I/O system and the main functions of each layer.
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Overview
• Principles of I/O Hardware
• Principles of I/O Software
• I/O Devices
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Storage Devices:
SSD vs. HDD
Vs
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Storage Devices:
SSD vs. HDD
SSD HDD
Power
Heat
Noise
Vibration
Weight
Durability
Speed
Cost
Capacity
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Solid-State Drive (SSD)
• DRAM or NOR/NAND flash memory based
– No mechanical parts (only controller+mem)
– Can be used as part of SSHDs
• NAND flash memory
– Organized in cells (SLCs or MLCs), pages, blocks
– Controller can read/program at page granularity
– Controller can erase at block granularity
– RND/SEQ access latency comparable
– Reads more efficient than writes
– Wear leveling to improve write endurance
– Garbage collection to implement write operations
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Hard Disk Drive (HDD)
• Multiple platters and cylinders in a single disk with as many tracks as their
heads. Each track → N sectors
• Addressing modes:
– CHS (Cylinder-head-sector), virtual/physical
– LBA (Logical Block Addressing), virtual
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Hard Disk:
Block Read/Write Time
Factors determining disk block read/write time:
1. Seek time
▪ The time to move the arm to the proper cylinder
2. Rotational delay
▪ The time for the sector to come under the head
3. Data transfer time
▪ The time to transfer a single block
• Which one dominates the read/write time?
• How do we minimize it and where?
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Disk Arm Scheduling Algorithms (1 of 2)
Figure 5-22. Shortest Seek First (SSF) disk scheduling algorithm.
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Disk Arm Scheduling Algorithms (2 of 2)
Figure 5-23. The elevator algorithm for scheduling disk requests.
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Hard Disk:
Error Handling
• Programming Errors
– e.g., request for nonexistent sector
• Transient Errors
– e.g., caused by dust on the head
• Permanent Errors
– e.g., disk block physically damaged
• Seek Errors
– e.g., the arm was sent to cylinder 6 but it went to 7
• Controller Errors
– e.g., controller refuses to accept commands
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Hard Disk:
Bad Sector Remapping
Figure 5-24. (a) A disk track with a bad sector. (b) Substituting a spare for the bad sector. (c) Shifting all the sectors to
bypass the bad one.
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Clock Hardware
• Two types:
– Simple clocks deliver hardware interrupts for each voltage cycle of the
power supply (i.e., every 20 or 16.7 ms)
– Advanced programmable clocks that have own crystal oscillator that
decrements a counter in a register. If counter hits zero → HW interrupt
• Hw also provides “counters” sw can read as needed
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Advanced Programmable Clock Example
• Oscillator has a frequency of 1 MHz
• The register is 16 bit
• Hence, we can set the timer between 1 and 65536 μs
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Clock Software (1 of 4)
Typical duties of a clock driver:
1. Maintaining the time of day
▪ System boot time (backup clock) + uptime (ticks)
2. Preventing processes from running longer than allowed
▪ Decrement current process' quantum at each tick
3. Accounting for CPU usage
▪ Increment current process’ cpu time at each tick
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Clock Software (2 of 4)
Typical duties of a clock driver:
4. Handling alarm system call from user processes
▪ Decrement alarm counter at each tick
5. Providing watchdog timers for parts of system itself
▪ Generate sys notifications for synchronous alarms
6. Profiling, monitoring, statistics gathering
▪ Increment specific counters at each tick
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Textbook (Chapter 5)
All sections except:
• Section 5.1.5.2 (“Precise and imprecise interrupts”)
• Section 5.2.[2-4]
• Section 5.5.3
• Section 5.[6-10].*
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