Evolution of CAD Tools &
Verilog HDL Definition
K.Sivasankaran
Assistant Professor (Senior)
VLSI Division
School of Electronics Engineering
VIT University
Outline
• Evolution of CAD
• Different CAD Tools for IC Flow
• Emergence & Features of HDL
• VHDL Vs VerilogHDL
• Design Methodologies
• Verilog HDL – Definition
• Levels of Abstraction
K Sivasankaran ECE 301- VLSI SYSTEM DESIGN 2
Evolution of CAD
•The first Integrated Circuit (IC) or silicon chip was fabricated in 1960s.
• IC chip evolution -> SSI, MSI, LSI, VLSI…
• Designing single chip with more than 100,000
transistors - VLSI.
• Complicated design processes.
• Traditional / conventional design method includes manual translation of
design description into logical equations and then to schematic.
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Evolution of CAD
•Verification through bread-boarding?
• CAD (back-end) tools became critical.
• Graphic packages (PSpice, Workbench, OrCAD) for
gate level / schematic representation.
–Cannot handle higher complexities.
–Poor portability.
–Poor readability for high complex designs.
• In all the above design methods the functional bugs cannot be identified till
the design is implemented in hardware, and hence the design time is very
long.
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CAD for ASIC Design Flow
• Cadence
– Digital, Analog and Mixed Signal, PCB Design, Testing and
Verification.
• Synopsys
• Mentor graphics
• Magic
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CAD for FPGA Design Flow
• Xilinx ISE and PAR , Partial Reconfiguration Flow
– All Xilinx Devices
• ALTERA EDA Tools
- All ALTERA Devices
• National Instruments
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CAD Tools for Process and Device Simulation
• Synopsys TCAD
– Sentaurus Process Simulator
– Sentaurus Device Simulator
• Silvaco TCAD
– Athena Process Simulator
– Atlas Device Simulator
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HDL?
• In electronics, a hardware description language or HDL is any
language from a class of computer languages for formal
description of electronic circuits. It can describe the circuit's
operation, its design, and tests to verify its operation by
means of simulation
• Popular HDLs are Verilog HDL & VHDL (for any complexity).
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• High level languages such as FORTRAN, PASCAL, C, C++, etc., are
sequential in nature.
• Digital designers felt the need for a standard language to describe digital
systems / hardware.
• Hardware Description Languages (HDLs) comes into existence and these
have special constructs to model the concurrency of processes found in
digital systems.
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• Easy development, verification and debugging through HDLs.
• HDL descriptions are easily portable, and is also compatible to all design
tools.
• HDLs can describe the digital systems at various abstraction levels & also
supports hierarchical modeling.
• HDL descriptions can be functionally simulated with Logic Simulators .
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• Advent of Logic synthesis tools in late 1980’s pushes HDLs to the forefront
of digital design.
• Digital circuits described at Register Transfer Level (RTL) using HDLs, can
also be synthesized through automated logic synthesis tools.
• Logic Synthesis tools can extract gate level details automatically from HDL
(RTL) description.
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VHDL Vs Verilog HDL
VHDL : Very High Speed Integrated Circuit Hardware Description Language
Verilog HDL: Verification Logic Hardware Description Language
Differences:
VHDL was designed to support system level design and specification.
Verilog HDL was designed primarily for digital hardware designers
developing FPGAs and ASICs.
The differences becomes clear when one analyze the language features.
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Design Methodologies
•Top-Down Design
Top – Define the top-level block
– Identify the sub-blocks
Sub-blocks necessary to build the top-
level block
Leaf cells – Sub-blocks are formed by leaf
cells - the cells that can not be
further divided
•Bottom-up Design
Top
– Build macro cells using leaf
Macro cells cells
– Move up the hierarchy until
the top-level is reached
Leaf cells
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What is Verilog HDL?
• Verilog HDL is a hardware description language used to design
and document electronic systems.
• It allows designers to design at various levels of abstraction.
• It supports the development, verification, synthesis, and
testing of hardware designs;.
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Levels of Abstraction
• Four Levels of Abstraction to represent the digital design
The highest level of abstraction provided by Verilog HDL. A
Behavioral module is implemented in terms of the desired design
algorithm
At this level the module is designed by specifying the data
Data Flow flow
The module is implemented in terms of logic gates and
Gate Level interconnections between these gates
This is the lowest level of abstraction provided by Verilog.
Switch Level A module can be implemented in terms of switches, storage
nodes and the interconnections between them
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Review
• Define HDL.
• Difference between HDL and HLL.
• Difference between VHDL and Verilog HDL
• Different design methodologies
• Different level of abstraction in verilog
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