EE2000 Logic Circuit

Design

Recap Lecture 7 – Latch and Flip-

Flop Circuits
Two Classes of Logic Circuits
Combinational logic circuit
Output depends only on the inputs (As discussed in
previous lectures)
Sequential logic circuit
Output depends on present input + past history
Memory circuit (to store previous STATE information)
is required

2
Sequential Logic Circuit

Vending Machine
Food/ drink / MTR tickets

Digital counter / clock

Latches and Flip-Flops are building blocks of

sequential logic circuit. Traffic light controller 3
Active High SR Latch

R Q

S Q

𝑡𝑡 1 2 3 4 5 6 7 8 9
𝑆𝑆 1 0 0 0 0 1 1 1 0
𝑅𝑅 0 0 1 0 0 0 1 0 0
𝑄𝑄 1 1 0 0 0 1 0 1 1
𝑄𝑄� 0 0 1 1 1 0 0 0 0
State S H R H H S U S H

4
Active Low Latch

𝑡𝑡 1 2 3 4 5 6 7 8 9
𝑆𝑆̅ 1 1 0 1 1 1 0 1 1
𝑅𝑅� 0 1 1 1 1 0 0 0 1
𝑄𝑄 0 0 1 1 1 0 1 0 0
𝑄𝑄� 1 1 0 0 0 1 1 1 1
State R H S H H R U R H

5
Summary

Note that the input is active high for NOR gate

implementation, whereas the input is active low for
NAND gate implementation

R Q S Q

S Q R Q

Require a 1 signal to change its state Require a 0 signal to change its state

6
Drawback - Noise
If inputs S, R are unstable (or noise), output produces an
unstable short pulse

Solution: Gated Latch!

𝐸𝐸 𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State

0 x x 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 0 0 Undefined

7
Drawback – Undefined State
The latches will enter undefined state for some inputs (e.g.
R = S = 1)

Solution: D Latch!

𝑅𝑅
𝐸𝐸 𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 x 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 1 1 0 Set
1 0 0 1 Reset
𝑆𝑆

8
Set-Reset FF Logic
symbol
𝑆𝑆
𝐶𝐶
𝑄𝑄

𝑅𝑅 𝑄𝑄�
A clocked signal is connected
to the Enable input of a gated
latch. 𝐶𝐶 𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 x x 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 0 0 Undefined

9
Table Given (Test and Exam)
𝑆𝑆 𝑅𝑅 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold 0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 1 0 1 Reset 0 1 0 1 Reset
1 0 1 0 Set 1 0 1 0 Set
1 1 1 1 Undefined 1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State

1 1 0 Set 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 0 1 Reset 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

10
Summary

11
Transparency & Glitch 𝐷𝐷
𝐶𝐶
𝑄𝑄

𝑄𝑄�

Pulse
𝐶𝐶

𝐷𝐷

𝑄𝑄

• FF is activated when C is HIGH (Pulse or Level

triggered)
• Transparency: Input passes through directly to
output
• Glitch: Undesired signal 12
Race Around Condition
𝑡𝑡𝑝𝑝
𝐽𝐽 𝐶𝐶
𝑄𝑄
𝐶𝐶 𝐽𝐽
𝐾𝐾 𝑄𝑄� 𝐾𝐾
∆𝜏𝜏
𝑄𝑄

• When both J and K are HIGH, the output toggles

continuously (racing) and becomes uncertain.
• Unless propagation delay of the gates larger than the
pulse width (∆𝜏𝜏 > 𝑡𝑡𝑝𝑝 )
13
7.3 Master-Slave Flip-Flop
• A combination of two flip-flops together in a series
configuration.
• At any time, only one flip-flop is enabled.

14
Characteristics

• Y is updated when Clk goes to and remains at 1.

• Q is updated when Clk goes to 0 and remains unchanged until the
next pulse.

Therefore,
For each clock pulse, Q only changes state at most once.
State change only occurs during the transition of Clk from 1 to 0.
15
Master-Slave D Flip-Flop

C’

16
Master-Slave JK Flip-Flop
Master Slave
𝐽𝐽 𝑆𝑆𝑚𝑚 𝑌𝑌�
𝑅𝑅𝑠𝑠 𝑄𝑄
𝐶𝐶̅
𝐶𝐶

𝐾𝐾 𝑅𝑅𝑚𝑚 𝑆𝑆𝑠𝑠 𝑄𝑄�

𝑌𝑌

𝐶𝐶
𝐽𝐽
𝐾𝐾

𝑌𝑌
𝑄𝑄

No racing! 17
Exercise
Master Slave
𝑆𝑆𝑚𝑚 𝑌𝑌�
𝑇𝑇 𝑅𝑅𝑠𝑠 𝑄𝑄
𝐶𝐶̅
𝐶𝐶
𝑅𝑅𝑚𝑚 𝑆𝑆𝑠𝑠 𝑄𝑄�
𝑌𝑌

𝐶𝐶
𝑇𝑇

𝑌𝑌

𝑄𝑄

18
Problem
• For the presented MSFF, master is enabled during
the period when the clock pulse is 1 (Level
triggered)
• Undesired behavior produced when inputs values
of S and R (or J, K, D, T) change at that period,
especially just before the clock pulse changes to 0
• Undesired output due to glitch could not be fully
avoided
• Better solution: Edge-triggered FFs

19
Edge-Triggered FF

20
Positive-Edge-Triggered D-FF
𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
1 1 0 Set
0 0 1 Reset

This table is given. You just need to remember change

state when CLK 0 → 1.

21
Negative-Edge-Triggered D-FF
𝐷𝐷 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
1 1 0 Set
0 0 1 Reset

This table is given. You just need to remember change

state when CLK 1 → 0.

22
Positive-Edge-Triggered JK-FF
𝐽𝐽 𝐾𝐾 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
0 1 0 1 Reset
1 0 1 0 Set
1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

This table is given. You just need to remember change

state when CLK 0 → 1.

23
Positive-Edge-Triggered T-FF
𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State
0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold
1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle

This table is given. You just need to remember change

state when CLK 0 → 1.

24
 Negative-Edge Positive-Edge
Logic Symbols

25
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 x, A, B, C = 0
𝐴𝐴 T = x + C = 0 (HOLD STATE)
S = A = 0, R = A’ = 1 (RESET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
26
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 x, A, B, C = 0
𝐴𝐴 T = x + C = 0 (HOLD STATE)
S = A = 0, R = A’ = 1 (RESET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
27
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 x = 1; A, B, C = 0
𝐴𝐴 T = x + C = 1 (TOGGLE STATE)
S = A = 0, R = A’ = 1 (RESET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
28
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 x = 1; A, B, C = 0
𝐴𝐴 T = x + C = 1 (TOGGLE STATE)
S = A = 0, R = A’ = 1 (RESET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
29
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 A = 1; x, B, C = 0
𝐴𝐴 T = x + C = 0 (HOLD STATE)
S = A = 1, R = A’ = 0 (SET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
30
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 A = 1; x, B, C = 0
𝐴𝐴 T = x + C = 0 (HOLD STATE)
S = A = 1, R = A’ = 0 (SET STATE)
𝐵𝐵 J = K = B = 0 (HOLD STATE)
𝐶𝐶
31
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 C = 0; x, A, B = 1
𝐴𝐴 T = x + C = 1 (TOGGLE STATE)
S = A = 1, R = A’ = 0 (SET STATE)
𝐵𝐵 J = K = B = 1 (TOGGLE STATE)
𝐶𝐶
32
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥 C = 0; x, A, B = 1
T = x + C = 1 (TOGGLE STATE)
𝐴𝐴 S = A = 1, R = A’ = 0 (SET
STATE)
𝐵𝐵
J = K = B = 1 (TOGGLE STATE)
𝐶𝐶
33
Exercise
𝑇𝑇 = 𝑥𝑥 + 𝐶𝐶 𝑆𝑆 = 𝐴𝐴 𝑅𝑅 = 𝐴𝐴′
𝐽𝐽 = 𝐾𝐾 = 𝐵𝐵

𝑥𝑥 𝐴𝐴 𝐵𝐵 𝐶𝐶

clk

clk
𝑥𝑥
𝐴𝐴
𝐵𝐵
𝐶𝐶
34
Asynchronous Inputs (PRE’ and CLR’)

35
Exercise
Work out the timing diagram for the state of each flip-flop
and the output (𝑞𝑞1 , 𝑞𝑞2 , 𝑧𝑧). (Ignore delay)

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝑧𝑧

clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1
𝑞𝑞2
𝑧𝑧 36
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1
CLR’ = 0 (All FFs RESET to 0)
𝑞𝑞2
𝑧𝑧
37
Exercise
Ignore z first because z is a combinational circuit

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1, q2 = 0
𝑞𝑞2 D = x = 1 (SET STATE)
K = 𝑞𝑞1 = 1, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (TOGGLE STATE)
𝑧𝑧
38
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1, q2 = 0
𝑞𝑞2 D = x = 1 (SET STATE)
K = 𝑞𝑞1 = 1, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (TOGGLE STATE)
𝑧𝑧
39
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 0; q1, q2 = 1
𝑞𝑞2 D = x = 0 (RESET STATE)
K = 𝑞𝑞1 = 0, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (SET STATE)
𝑧𝑧
40
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 0; q1, q2 = 1
𝑞𝑞2 D = x = 0 (RESET STATE)
K = 𝑞𝑞1 = 0, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (SET STATE)
𝑧𝑧
41
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1 = 0, q2 = 1
𝑞𝑞2 D = x = 1 (SET STATE)
K = 𝑞𝑞1 = 1, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (TOGGLE STATE)
𝑧𝑧
42
Exercise

𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1 = 0, q2 = 1
D = x = 1 (SET STATE)
𝑞𝑞2 K = 𝑞𝑞1 = 1, J = 𝑥𝑥 + 𝑞𝑞1 = 1 (TOGGLE
STATE)
𝑧𝑧
43
Exercise
𝑥𝑥 𝑞𝑞1 𝑞𝑞2 𝐷𝐷 = 𝑥𝑥
𝑧𝑧
𝐾𝐾 = 𝑞𝑞1
𝐽𝐽 = 𝑥𝑥 + 𝑞𝑞1
𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2
clk CLR′

clk
𝑥𝑥
CLR′
𝑞𝑞1
𝑞𝑞2
𝑧𝑧

Final Step: Work out z

44
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
𝑞𝑞2 CLR’ = 0 (All FFs RESET to 0)

𝑧𝑧

45
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1 = 0, q2 = 0
𝑞𝑞2 T = x = 1 (TOGGLE STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 1 (SET STATE)
𝑧𝑧

46
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1 x = 1; q1 = 0, q2 = 0
𝑞𝑞2 T = x = 1 (TOGGLE STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 1 (SET STATE)
𝑧𝑧

47
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
x = 0; q1 = 1, q2 = 1
𝑞𝑞2 T = x = 0 (HOLD STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 0 (HOLD STATE)
𝑧𝑧

48
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
x = 0; q1 = 1, q2 = 1
𝑞𝑞2 T = x = 0 (HOLD STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 0 (HOLD STATE)
𝑧𝑧

49
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
x = 1; q1 = 1, q2 = 1
𝑞𝑞2 T = x = 1 (TOGGLE STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 0 (HOLD STATE)
𝑧𝑧

50
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
x = 1; q1 = 1, q2 = 1
𝑞𝑞2 T = x = 1 (TOGGLE STATE)
K =𝑥𝑥 + 𝑞𝑞1 = 0, J = 𝑞𝑞1 = 0 (HOLD STATE)
𝑧𝑧

51
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
𝑞𝑞2
𝑧𝑧

52
Exercise
𝑥𝑥 T 𝑞𝑞2
𝑇𝑇 = 𝑥𝑥
𝑞𝑞1 𝑧𝑧
𝐽𝐽 = 𝑞𝑞1
𝐾𝐾 = 𝑥𝑥 + 𝑞𝑞1
clk CLR′ 𝑧𝑧 = 𝑞𝑞1 𝑞𝑞2

clk
𝑥𝑥
CLR′
𝑞𝑞1
𝑞𝑞2
𝑧𝑧

53
EE2000 Logic Circuit Design

Lecture 8– VHDL 2
Outline
8.1 Component and instantiation
8.2 Conditional signal assignment
8.3 Selected signal assignment
8.4 Sequential statements
8.5 Decoder designs
- Using Boolean Operators
- Using Case statement
- Using IF statement
- With ENable Signal
8.6 Other examples – Encoder, MUX, DMUX, Flip-Flop

55
8.2 Conditional Signal Assignment
signal_name <= expression1 when condition1 else
expression2 when condition2 else
[expressionN];
• Concurrent statement
• Conditions are evaluated successively until a true
condition is found
• Conditions could be based on different signals
This means
d <= a when b = ‘1’ else 1. When b = ‘1’ then d = a or else
c when d = ‘0’ else 2. When d = ‘0’ then d = c else
e; 3. d = e
56
Examples
Y <= (C and B) when a = ‘0’ else
‘0’ when b = ‘1’ else
‘1’ when c = (d or e) else
d;

Z <= “00” when D > “0010” and D <= “0110” else

“01” when D = “0101” else
“10” when D > “1000” and D < “1100” else
“11”;

57
Example 2-to-1 MUX OUT1

OUT1 <= D0 when S = ‘0’ else

D1;
This means
1. When S = ‘0’ then OUT1 = D0
or else
2. OUT1 = D1

58
Example 4-to-1 MUX a

b
OUT1
c

s0 s1

OUT1 <= a when (s1 = ‘0’ and s0 = ‘0’) else

b when (s1 = ‘0’ and s0 = ‘1’) else
c when (s1 = ‘1’ and s0 = ‘0’) else
d;

59
8.3 Selected Signal Assignment
with expression_s select
signal_s <= expression1 [after delay-time] when choice1,
expression2 [after delay-time] when choice2,
…
expression_n [after delay-time] when others];

• Concurrent statement
• Each line ends with ‘,’ and the last line with ‘;’
• “when others” is used to handle the default case,
and also the don’t care cases
• No priority and based on a single signal

60
Examples

with d select This means

Y <= ‘0’ when “000”, 1. When d = ‘000’ then Y = ‘0’ or
‘1’ when “001”, else
‘1’ when “010”, 2. When d = ‘001’ then Y = ‘1’ or
‘0’ when “011”, else
‘1’ when “100”, 3. When d = ‘010’ then Y = ‘1’ or
‘0’ when “101”, else
‘1’ when “110”, ......
‘1’ when “111”,
NULL when others; 9. For other cases (don’t care),
then Y = NULL

61
Example 4-to-1 MUX a

b
signal sel: integer; OUT1
c

sel <= 0 when (s1 = ‘0’ and d

s0 = ‘0’) else
1 when (s1 = ‘0’ and s0 s1
s0 = ‘1’) else This means
2 when (s1 = ‘1’ and
1. When sel = ‘0’ (00)
s0 = ‘0’) else then OUT1 = a or else
3;
2. When sel = ‘1’ (01)
with sel select then OUT1 = b or else
OUT1 <= a when 0, 3. When sel = ‘2’ (10)
b when 1, then OUT1 = c or else
c when 2, 4. OUT1 = d
d when others; 62
Example 4-to-1 MUX a

b
signal sel: integer; OUT1
c

sel <= 0 when (s1 = ‘0’ and d

s0 = ‘0’) else
1 when (s1 = ‘0’ and s0 s1
s0 = ‘1’) else This means
2 when (s1 = ‘1’ and
1. When sel = ‘0’ (00)
s0 = ‘0’) else then OUT1 = a or else
3;
2. When sel = ‘1’ (01)
with sel select then OUT1 = b or else
OUT1 <= a when 0, 3. When sel = ‘2’ (10)
b when 1, then OUT1 = c or else
c when 2, 4. OUT1 = d
d when others; 63
Conditional Selected

with d select
Y <= ‘0’ when “000”,
d <= a when b = ‘1’ else
‘0’ when “011”,
c when d = ‘0’ else
‘0’ when “101”,
e;
‘1’ when others;

 Can be based on different  Based on a single signal only

signals  Only one condition is TRUE
 Evaluated successively until a
true condition is found

64
8.4 Sequential Statements
• Process statement is used to enclose sequential
statements that are executed in order
• Sequential statements are used in processes to specify
how signals are assigned
• After all the sequential statements in the process are
executed, the signals are assigned to their new values

[name:] process [(sensitivity_list)]

begin
sequential statements
end process;

65
Multiple Process Statements
Process statement is concurrent statement and can have
more than one Process statements in an architecture

66
Recap from Lab Session 1
simgen: process -- no sensitivity list
begin
sw <= ‘0’;
wait for 50 ns;
sw <= ‘1’;
wait for 100 ns;
sw <= ‘0’;
wait for 50 ns
end process;
• Without the sensitivity list, the process will be run
continuously
• With the sensitivity list, the process will be executed once
when a new event (change value) occurs on any of the
signals in the list 67
Sensitivity List
proc1: process (a, b, c)
begin
x <= a and b and c;
end process;

When either a, b or c changes from ‘1’ to ‘0’ or vice versa,

the process will run one time to update the value of x
proc1: process
begin
x <= a and b and c;
wait on a, b, c;
end process;

68
Wait Statement Forms
wait for 50 ns;

wait on a, b, c;

wait until signal = value;

wait until clk = ‘1’;

The process will pause until clk changes to ‘1’

69
WHILE Loop Statement
[label:] while condition loop
sequential statements
end loop [label];

• Conditional loop statement

• Condition is tested before the execution of the loop
• Terminate when the condition tested becomes false
while i < 10 loop
while j < 20 loop
...
j <= j + 1;
end loop;
i <= i + 1;
end loop; 70
FOR Loop Statement
[label:] for counter in range loop
sequential statements
end loop [label];

• For the repeated execution of a sequence of statements

a fixed number of times
• An iteration counter and a range are specified
• After an iteration, the counter is assigned the next value
from the range
• Ascending order use to; descending order use downto

71
FOR Loop Statement

Compute the squares of integer values between 1 and 10

and stores them into the i_square array

for i in 1 to 10 loop
i_square (i) <= i * i;
end loop;

i starts with 1, after computing i_square (1)

i becomes 2 (i = 2).....
Until i = 10.
72
FOR Loop Statement
entity match_bits is
port (a, b: in bit_vector (7 downto 0);
matches: out bit_vector (7 downto 0));
end match_bits

architecture functional of match_bits is

begin
process (a, b)
begin
for i in 7 downto 0 loop
matches (i) <= not (a(i) xor b(i));
end loop;
end process;
end functional; what is the function?
73
FOR Loop Statement
• A set of 1-bit comparators to compare the bits of the
same order of vectors a and b
• Result is stored into the matches vector, which will
contain '1' wherever the bits of the two vectors match
and '0' otherwise

74
NEXT Statement
next [label:] [when condition];

The execution of the current iteration is skipped and the

control is passed to the beginning of the loop statement

for i in 1 to 10 loop
next when v(i) = ‘0’;
count := count + 1;
end loop;

75
8.5 Decoder Designs (2-to-4 decoder)

• Input A (2 bits)
• Output X (4 bits)

76
Using Boolean Operators

77
Using CASE statement
case expression is
when option1 =>
statement;
when option2 =>
statement;
...
[when others =>
statement;]
end case;
When A is “00” X <= “0001”

78
Using IF statement
if condition then
statement;
[elseif condition then
statement;]
...
[else statement;]
end if;
If A is “00” X <= “0001”

79
With Enable Input

Active Low

80
With Enable Input

81
8.6 Other Examples

82
Schematic Diagram

83
Simulation

84
Recap (Decimal-to-Binary Encoder)
Inputs Outputs
0 1 2 3 4 5 6 7 8 9 A3 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
Encoder (Decimal-to-BCD Encoder)
R
OUT0
S
T
OUT1

OUT2
Y
OUT3
Z

Enter your codes here

86
BCD-to-7 Segment

Inputs Outputs
B0 B1 B2 B3 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1
87
BCD-to-7 Segment
Inputs Outputs
B0B1
B0 B1 B2 B3 a
B2B3
0 0 0 0 1
0 0 0 1 0 x
0 0 1 0 1
0 0 1 1 1 x
0 1 0 0 0
0 1 0 1 1
x x
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1 x x
1 0 0 1 1

𝑎𝑎 = 𝐵𝐵𝐵 + 𝐵𝐵𝐵 + 𝐵𝐵𝐵𝐵𝐵𝐵 + 𝐵𝐵1′ 𝐵𝐵𝐵𝐵

a <= B0 OR B2 OR (B1 AND B3) OR (NOT B1 AND
NOT B3);

88
BCD-to-7 Segment
Inputs Outputs
B0B1
B0 B1 B2 B3 e
B2B3
0 0 0 0 1
0 0 0 1 0 x
0 0 1 0 1
0 0 1 1 0 x
0 1 0 0 0
0 1 0 1 0
x x
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1 x x
1 0 0 1 0

𝑒𝑒 =
e <=

89
BCD-to-7 Segment
Inputs Outputs
B0B1
B0 B1 B2 B3 f
B2B3
0 0 0 0 1
0 0 0 1 0 x
0 0 1 0 0
0 0 1 1 0 x
0 1 0 0 1
0 1 0 1 1
x x
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1 x x
1 0 0 1 1

𝑓𝑓 =

f <=

90
BCD-to-7 Segment
Inputs Outputs
B0B1
B0 B1 B2 B3 g
B2B3
0 0 0 0 0
0 0 0 1 0 x
0 0 1 0 1
0 0 1 1 1 x
0 1 0 0 1
0 1 0 1 1
x x
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1 x x
1 0 0 1 1

𝑔𝑔 =

g <=

91
Multiplexer

92
Simulation

93
Demultiplexer

94
D-Flip Flop

Rising-edge triggered Falling-edge triggered

process(clk) process(clk)
begin begin
if rising_edge(clk) if falling_edge(clk)
then then
q <= d; q <= d;
end if; end if;
end process; end process;

95
D-Flip Flop with RESET
Edge condition comes before reset
Syn active “high” reset Syn active “low” reset
Rising edge FF Falling edge FF

process(clk) process(clk)
begin begin
if rising_edge(clk) if falling_edge(clk)
then then
if sreset = '1’ then if sreset = ‘0’ then
q <= '0'; q <= '0';
else else
q <= d; q <= d;
end if; end if;
end if; end if;
end process; end process;

96
D-Flip Flop with RESET
Reset condition comes before edge

Asyn active “high” reset Asyn active “low” reset

Rising edge FF Falling edge FF
process(clk, areset) process(clk, areset)
begin begin
if areset = '1' then if areset = ‘0' then
q <= '0'; q <= '0';
elsif rising_edge(clk) then elsif falling_edge(clk) then
q <= d; q <= d;
end if; end if;
end process; end process;

97
D-Flip Flop with RESET

98
D-Flip Flop with SET and RESET
Asyn set active “high” , reset active “low”
Rising edge FF
process(clk, areset, aset)
begin
if aset = '1' then
q <= '1';
elsif areset = '0' then
q <= '0';
elsif rising_edge(clk)
then
q <= d;
end if;
end process;

Note: set has higher priority than reset

99
T-Flip Flop with RESET
Rising edge FF architecture behavioral of TFF is
signal tmp : std_logic;
Asyn Active High Reset begin
process(clk)
𝐶𝐶 𝑇𝑇 𝑄𝑄𝑡𝑡+1 𝑄𝑄𝑡𝑡+1 State begin
0 x 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold if areset = ‘1’ then
TMP <= ‘0’;
1 0 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Hold elsif rising_edge(clk) then
1 1 𝑄𝑄𝑡𝑡 𝑄𝑄𝑡𝑡 Toggle if (T = ‘1’) then
TMP := not TMP;
end if;
library ieee;
end if;
use ieee.std_logic_1164.all;
Q <= TMP;
end process;
entity TFF is
end behavioral;
port( T: in std_logic;
clk: in std_logic;
areset: in std_logic;
Q: out std_logic;
end TFF;

100
Simulation

101
Lab Session 3
Objectives
• To practice designing combinational logic circuit
• To reuse the materials and knowledge from previous
labs
• To learn how to perform type conversion in VHDL Code
• To apply bit slicing and bit concatenation technique in
VHDL
• To learn how to use a logic analyzer to trace the digital
signals

102
Lab Session 3
• An arithmetic logic unit (ALU) is to perform arithmetic
and bitwise operation on integer binary numbers
• In this experiment, you will implement a simple 3- bit
ALU
• Given two 3-bit operands A, B and the 2-bit operator
op, the result is shown in the table

100 + 011 = 111

100 AND 111 = 100
100 XOR 111 = 011
Left shift A 011 -> 110
103
VHDL Codes

104
VHDL Codes

105
Type Conversion

106
Expand to 4 Bits

107
Selected Signal Assignment

108
RTL Analysis

As the design is different from one another, the

schematic may not be the same 109
Hardware

• SW0-SW2 as input “A”, SW3-SW5 as input “B”,

SW6-SW7 as input “op”
• LD0-LD2 as output “result”, LD3 as output “carry”
• JA1-JA3 as output port dup_result and JA4 as
dup_carry (To connect to logic analyser using JA ports)

110
Results

111
Logic Analyzer

112
Logic Analyzer

113
8.1 Components and Instantiation
• Structural modeling: Modular design of a complex
project
• When designing a complex project, we can split it
into two or more simple designs (sub-modules/sub-
circuits/components)
• Example: A full adder (FA) contains of 2 half adders
(HAs); Half adder can be modeled by a component

115
Structural Modeling
• Structural modeling or modular design allows us to pack
low-level functionalities into modules
• Allows a designed module to be reused without the need
to reinvent and re-test the same functions/modules
every time
• To include a component into a module, we need to
(1) declare the component
(2) instance the component
in architecture

116
Component Declaration
• An architecture may contain multiple components and
they must be declared first
architecture [name] …
[signal]

component XX -- Component declaration

…
end component;

component YY -- Component declaration

…
end component;

begin
… -- Component instantiation
end [name];

117
Half Adder
Inputs Outputs
a b c s
0 0 0 0
Create the sub-module of half adder first 0 1 0 1
1 0 0 1
sum = 𝑎𝑎 ⊕ 𝑏𝑏 carry = 𝑎𝑎 � 𝑏𝑏 = 𝑎𝑎𝑎𝑎
1 1 1 0

--sub module(half adder) entity declaration

entity halfadder is
port (a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC
);
end halfadder;

architecture Behavioral of halfadder is

begin
sum <= a xor b;
carry <= a and b;
end Behavioral;
118
Full Adder
- Create the component entity halfadder
- Create the module entity fulladder
- Determine the number of components (i.e. 2 halfadder
in this case) used in the design
- Define signals for inter-connections between halfadder
- Provide each component a different name
- Then instantiates the declared component

119
Full Adder
--top module(full adder) entity declaration
entity fulladder is
port (a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic
);
end fulladder;

--top module architecture declaration

architecture behavior of fulladder is

component halfadder
port(
a : in std_logic;
b : in std_logic;
sum : out std_logic; --sub-module(half adder) is
carry : out std_logic declared as a component
); before the keyword "begin“
end component;
120
Component Instantiation
Differences between a component and an entity
declaration:
• Entity declaration declares a circuit model containing
one or multiple architectures
• Component declaration declares a virtual circuit
template, which must be instantiated to take effect
during the design
• Instantiation – To map the signals in the entity with the
input/output of the component
• Port map is required for component instantiation
121
Full Adder
• Two HAs are needed
• Internal signals s1,c1,c2 are used to connect the two Has
• In HA, we define port (a:in STD_LOGIC; b:in STD_LOGIC;
sum:out STD_LOGIC; carry:out STD_LOGIC);

signal s1,c1,c2 : std_logic:='0’; --declare internal signal

begin

--Provide a different name for each half adder.

--instantiate and do port map for the half adders.

HA1 : halfadder port map (a,b,s1,c1);

HA2 : halfadder port map (s1,cin,sum,c2);
carry <= c1 or c2; --final carry calculation

end;
122
Component Instantiation
For Creating connections between components and ports
3 steps in VHDL instantiation:
• Label: identify a unique instance of component
• Component type: select a targeted declared component
• Port Map: Connect component to signals

Signals must be of the same data type for the connecting

pins 123
Component Instantiation
signal s1,c1,c2 : std_logic:='0’; --declare internal signal

begin

--Provide a different name for each half adder.

--instantiate and do port map for the half adders.

HA1 : halfadder port map (a,b,s1,c1);

HA2 : halfadder port map (
a => s1,
b => cin,
sum => sum,
carry => c2
);
carry <= c1 or c2; --final carry calculation

end;

124
Port Map
Module FA
entity halfadder is
Port ( a : in STD_LOGIC;
Module HA
b : in STD_LOGIC;
a
sum : out STD_LOGIC;
carry : out STD_LOGIC b
); sum
end halfadder; carry

Port name of Halfadder (a,b,sum,carry)

Module HA
begin a
b
--Provide a different name for each half adder.
--instantiate and do port map for the half adders. sum
carry
HA1 : halfadder port map (a,b,s1,c1);
HA2 : halfadder port map (s1, cin,sum,c2);
carry <= c1 or c2; --final carry calculation

end; 125
Half-Adder 1

HA1 : halfadder port map (a,b,s1,c1);

a sum s1
HA1: halfadder
a b carry c1 sum
b
cin a sum
HA2: halfadder carry
b carry

126
Half-Adder 2

HA2 : halfadder port map (s1,cin,sum,c2);

a sum s1
HA1: halfadder
a b carry c1 sum
b
cin a sum
HA2: halfadder carry
b carry c2

carry <= c1 or c2; 127