University of Baghdad Sequential Circuits

College of Engineering/ Dept. of Computer Engineering Lecture No. 12

Logic By Zainab Hassan
Logic Circuits:
The digital cct. considered thus far have been combinational, i.e., the outputs
at any instant of time are entirely dependant upon the inputs presents at that time.
Although every digital system likely to have combinational circuits, most systems
encountered in practice also includes memory elements, which require the system
be described in terms of sequential logic.
Output

Input Combinational Memory

cct Element

The sequential logic cct. use combinational gates and F-F cct. in their
design.
Latches:
The latches are a type of bi-stable storage device that in normally places in a
category separate from that of flip-flops. Latches are basically similar to flip-flops
because they are bi-stable devices that can reside in either of two states by virtue of
feed back arrangement, in which the outputs are connected back to the opposite
inputs. The main difference between latches and flip-flops is method used for
changing their state.
S-R Latch (Basic F/F)
S R Qn Qn+1
0 0 0 0 If S and R =0
S S-R Q
Qn=Qn+1 (no change)
F-F S
Q
0 0 1 1
R 0 1 0 0 S=0, R=1
Qn+1 (Reset)
0 1 1 0
SR SR SR SR 1 0 0 1 S=0, R=0

Q 0 0 x 1 1 0 1 1 Qn+1 (Set)

1 1 0 X S=1, R=1
Q 1 0 x 1 1 1 1 X Qn+1 (Undefiend)

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
Qn1  S  RQn
Qn  Qn1  S  RQn
Qn  Qn1  S  RQn
Using (NOR) gates: R
S Q
Qn1  S  RQn Q
 S  RQn
Q
 S  Qn  R S
R R

Using (NAND) gates: S Q

S
Q
Qn1  S  RQn

 S  RQn
Q
 S . RQn R
R
R
Example: S, R waveforms in figure below applied to input of S-R latch,
determine the waveform of Q. assume that Q is initially low.

Gated S-R Latch:

A gated latch requires an enable inputs (En). The logic diagram and logic
symbol for gated S-R latch are shown in following figure. The S and R inputs
control the state to which the latch will go when high level is applied to En input.
The latch will not change until the En input is high, but as long as it remains high,
the output is determined by S
S Q
the state of S and R inputs.
Q
S En
Q
En S-R R
F-F Q Q
R
R R R
R Logic Diagram
Logic Symbol

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 University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
Example: Determine the Q waveform if input shown in following figure are
applied to a gated S-R latch that is initially RESET.

Edge-triggered Flip-Flops:
Flip-Flops are synchronous bi-stable devices. In this case the term
synchronous means that the output changes state only at specified point on a
triggering input called Clock (designated C as a control input); that is, changes in
output occur in synchronization with clock.

1. S-R Edge triggered Flip-Flop:

S Q S Q
Top-positive Buttom-negative
C S-R Edge Edge
C S-R
Triggered Triggered
F-F F-F
R Q R Q

S S
S Q S Q
Q Q
En Logic Diagram En
R R
Q Q
R R R R
R R

Example: Determine Q and Q output waveform of Flip-Flops in the figure below.

Assume that the positive edge triggered F/F is initially RESET.

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan

S Q

C S-R
F-F
R Q

2. J-K Flip-Flop:

J Q |J K Qn Qn+1
J-K 0 0 0 0
C (no change)
F-F 0 0 1 1
K Q 0 1 0 0
Symbol Diagram 0 1 1 0
(Reset)
1 0 0 1
1 0 1 1 (Set)
K 1 1 0 1
S Q 1 1 1 0
(Toggle)
Q
c/k
R JK JK JK JK
Q 1
Q 1 Qn1  J Qn  KQn
J R
R Q 1 1
Logic Diagram

Example: Find the output Q for the following input waveforms, assuming negative
edge triggered J-K flip-flop.

CLK

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
3. Delay Flip-Flop (D- Flip/Flop):
D Qn Qn+1
D Q
0 0 0
C D 0 1 0
F-F
1 0 1
Q
1 1 1
Symbol Diagram

D
Q D D Qn 1  D
Q Q 1
c/k
R Q 1
Q
R
Logic Diagram

Example: Find the output Q for the following input waveforms, assuming positive
edge triggered D- flip/flop.

4. |Toggle Flip-Flop (T- Flip/Flop):

T Qn Qn+1
T Q 0 0 0
(no change)
T 0 1 1
C
F-F 1 0 1
Q 1 1 0
(Toggle Qn)

Symbol Diagram

T
S Q
Q
c/k
R
Q
R

Logic Diagram
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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
Master-Slave Flip-Flops:
Another class of F/Fs is the master-slave. Although this type of F/Fs has
largely been replaced by the edge-triggered devices, a limited selection is still
available from Ic manufacturer. There are two basic types of Master-Slave F/F:-
 Pulse triggered: does not allow data changed while clock active.
 Data-look out: has no restriction.
In both types data are entered into F/Fs on the leading edge of the clock
pulse, but the output does not reflect the input state until trailing edge.

S Y S Q  Flip Flop without pebble

changes output on leading edge
of positive going clock pulse.
R R Q  Flip Flop with pebble changes
Y
output on trailing edge of
Clock
positive going clock pulse.

J
S Q
Q
c/k
R
Q
K R
R

Asynchronous inputs:
The flip-flops discussed before S-R, D, J-K, T inputs are called synchronous
inputs because data on these inputs are transferred to the flip-flop output only on
triggering edge of the clock pulse. That is, the data are transferred synchronously
with the clock. Most integrated circuits flip-flops also have asynchronous inputs.
These inputs are affecting the state of the flip-flop independent of the clock. They
are normally labeled Preset (PRE) and Clear (CLR) or direct set (SD) and direct
reset (RD) by some manufacturers.

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
 An active level on the preset input will SET the flip-flop.
 An active level on the clear input will RESET the flip-flop.

Example:
PRE
High

C J-K
F-F
Q

CLR

Conversion between flip-flops:

Qn Qn+1 D T S R J K

0 0 0 0 0 X 0 X

0 1 1 1 1 0 1 X

1 0 0 1 0 1 X 1

1 1 1 0 X 0 X 0

Example: Design a D- flip/flop using S-R flip/flop?

D Qn Qn+1 S R D D D D
0 0 0 0 X
Qn 0 1 Qn x 0
0 1 0 0 1
Qn 0 x Qn 1 0
1 0 1 1 0

1 1 1 X 0
SD RD

D Q
S S-R
C
F-F
Q

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
Example: Design a T- flip/flop using J-K flip/flop?

T Qn Qn+1 J K T T T T
0 0 0 0 X
Qn 0 1 Qn x x
0 1 1 X 0
Qn x x Qn 0 1
1 0 1 1 X

1 1 0 X 1
J T K T

T Q

C J-K
F-F
Q

Example: Find the output Q for the following input waveforms using the circuit
below?
J Q
C J-K
F-F
K Q

Propagation Delay Times:

A propagation delay is an interval of time required after an inputs signal has
been applied for the resulting output change to occur. Several categories of
propagation delay are important in the operation of F/F.
1. Propagation tPLH as measured from the triggering edge of the clock pulse to
the Low-to-High transition of output.

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
2. Propagation delay tPHL as measured from the triggering edge of the clock
pulse to the High-to-Low transition of output.

3. Propagation delay tPLH as measured from the preset input to the Low-to-High
transition of output.

4. Propagation delay tPHL as measured from the clear input to the High-to-Low
transition of the output.

Set up Time:
The set up time (ts) is the minimum interval required for the logic levels to
be maintained constantly on the inputs (J & K) or (S & R) or D prior to the
triggering edge of the clock pulse in order the levels to be reliably clocked into the
F/F. This is illustrated in the figure below.

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
Hold Time:
The hold time (th) is the minimum interval required for the logic levels to
remain on the input after the triggering edge of the clock pulse in order the levels
to be reliably clocked into the F/F. This is illustrated in the figure below for D flip-
flop.

Review Questions:
1. For a gated S-R latch, determine Q and Q output for input in figure shown in
proper relationship to the enable. Assume that Q starts Low.

2. Solve the previous problem with this input.

3. For a gated D-latch, the waveforms shown in figure are observed on input.
Sketch output timing diagram. Assume the latch is initially RESET.

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University of Baghdad Sequential Circuits
College of Engineering/ Dept. of Computer Engineering Lecture No. 12
Logic By Zainab Hassan
4. Two edge triggered F/Fs, if their inputs are shown in figure. Sketch the Q
output. Assume the two F/Fs are initially RESET.

5. Determine the Q waveform relative to the clock if the signals shown in figure
are applied to the input of J-K flip-flop. Assume Q initially Low.

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