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Programmable Logic Devices
 General Structure of PLD
• Inputs to the PLD are applied to a set of buffer/inverters.
These devices have both the true value of the input as well as
the complemented value of the input as its outputs.

• Outputs from these devices are the inputs to an array of and-

gates. The AND array generates a set of p product terms.

• The product terms are inputs to an array of or-gates to realize

a set of m sum-of-product expressions.
General Structure of PLD
 General Structure of PLD
• One or both of the gate arrays are programmable.
• The logic designer can specify the connections within an array.
• PLDs serve as general circuits for the realization of a set of
Boolean functions.

Device AND-array OR-array

PROM Fixed Programmable

PLA Programmable Programmable

PAL Programmable Fixed

General block diagrams

Fixed Fusible
input Output
ROM AND
Array
OR
Array

Fusible Fixed
PAL input AND
Array
OR
Array
Output

Fusible Fusible
PLA input AND OR Output
Array Array
 Programming a PLD
• In a programmable array, the connections to each gate can be
modified.
• Simple approach is to have each of the gate inputs connected
to a fuse.

• Gate realizes the product term 𝑎𝑏𝑐𝑑.

• To generate the product term 𝑏𝑐 we remove the 𝑎, 𝑑
connections by blowing the corresponding fuses.
• Thus, programming is a hardware procedure. Specialized
equipment called programmers is needed to carry out the
programming of a PLD.
 Programming a PLD
• Erasable PLD—connections can be reset to their original
conditions and then reprogrammed.
– Can be achieved by exposing the PLD to ultraviolet light or
using electrical signals
• PLDs programmed by a user are called field programmable.
• User can also specify the desired connections and supply the
information to the manufacturer. Manufacturer prepares an
overlay that is used to complete the connections as the last
step in the fabrication process.
• Such PLDs are called mask programmable.
 PLD Notation
• Simplified notation: Each gate has only a single input
line.
• Inputs are indicated by lines at right angles to the
single gate lines.
• A cross at the intersection denotes a fusible link is
intact.
 PLD Notation
• Lack of cross indicates the fuse is blown or no
connection exists.
 PLD Notation
• The occurrence of a hard-wired connection that is not fusible
is indicated by a junction dot.

• For the special case when all the input fuses to a gate are kept
intact, a cross is placed inside the gate symbol.
 Programmable Read-Only Memory
(PROM)
• AND-array with buffer/inverter is an 𝑛-to-2𝑛 -line decoder.
• OR-array is a collection of programmable or-gates.
• Decoder is a min-term generator.
• n-variable minterms appear on the 2𝑛 lines at the decoder
output. These are also known as word lines.
• n input lines called address lines, m output lines called bit
lines.
• 2𝑛 × 𝑚 PROM.
• Realization of Boolean expressions same as realization using
decoder discussed previously.
PROM Structure

Logic Diagram
Internal Logic diagram of PROM
And gate realization using ROM

4*1
Memory

0
Decoder 0

Address (2:4) 0
1

Y
PROM Structure

PLD Notation
 Example
Realizing 𝑓1 𝑥2 , 𝑥1 , 𝑥0 = ∑𝑚 0,1,2,5,7
𝑓2 𝑥2 , 𝑥1 , 𝑥0 = ∑𝑚(1,2,4,6)
 Why is it called PROM?
• 3-bit input combination to the 𝑥0 , 𝑥1 , 𝑥2 lines is regarded as
an address of one of the word lines.
• As a consequence of selecting a given word line, a pattern of
0’s and 1’s, a word, as determined by the fusible connections
to the selected word line appears at the bit lines of the
device.
• This 0-1 pattern is considered the word stored at the address
associated with the selected word line.
• E.g. the word stored at address 𝑥2 𝑥1 𝑥0 = 100 is 𝑓1 𝑓2 = 01.
• “Read only”: The fact that the connections associated with
the fusible links normally cannot be altered once they are
formed.
Programmable Logic Array
PLA (Contd.)

F0 = m(0,1,4,6) = A’B’+AC’
F1 = m(2,3,4,6,7) = B+AC’
F2 = m(0,1,2,6) =A’B’+BC’
F3 = m(2,3,5,6,7) =AC+B
PLA (Contd.)
• PLA Table
F0 = m(0,1,4,6) = A’B’+AC’
F1 = m(2,3,4,6,7) = B+AC’
F2 = m(0,1,2,6) =A’B’+BC’
F3 = m(2,3,5,6,7) =AC+B