CPLD & FPGA ARCHITECTURE & APPLICATIONS

Introduction : The need of programmable devices was realized in early 70s itself with the
design of PLD by Ron Cline from Signetics . The digital ICs like TTL or CMOS have fixed
functionality and the user has no option to change or modify their functionality .i.e they work
according to the design given by the manufacturer. So,to change this people started thinking of a
methodology by which the functionality of an IC can be modified or changed. Then the concept
of using Fuses in ICs entered and gained momentum. This method of changing or modifying
the functionality of an IC using the Fuses was appreciated and this method of blowing a Fuse
between two contacts or keeping the Fuse intact was done by using a software and hence these
devices were called Programmable Logic Devices(PLDs). Many digital chips were considered
under the category of PLDs .But the most fundamental and primitive was the Memories like
ROM or PROM etc.
The realization of Digital circuits by PLDs can be classified as shown in the diagram below.

PLAs were introduced in the early 1970s, by Philips, but their main drawbacks were that they
were expensive to manufacture and offered somewhat poor speed-performance. Both
disadvantages were due to the two levels of configurable logic, because programmable logic
planes were difficult to manufacture and introduced significant propagation delays. To overcome
these problems , Programmable Array Logic (PAL) devices were developed.
Memory : Memory is used to store, provide access to, and allow modification of data and
program code for use within a processor-based electronic circuit or system. The two basic types
of memory are ROM (read-only memory) and RAM (random access memory).
ROM is used for holding program code that must be retained when the memory power is
removed. It is considered to provide nonvolatile storage. The code can either be fixed when the
memory is fabricated (mask programmable ROM) or electrically programmed once (PROM,
Programmable ROM) or multiple times. Multiple programming capacity requires the ability to
erase prior programming, which is available with EPROM (electrically programmable ROM,
erased using ultraviolet [UV] light), EEPROM or EEPROM (electrically erasable PROM), or
flash (also electrically erased). PROM is sometimes considered to be in the same category of
circuit as programmable logic, although in this text, PROM is considered in the memory
category only.
RAM is used for holding data and program code that require fast access and the ability to modify
the contents during normal operation. RAM differs from read-only memory (ROM) in that it can
be both read from and written to in the normal circuit application. However, flash memory can
also be referred to as nonvolatile RAM (NVRAM). RAM is considered to provide a volatile
storage, because unlike ROM, the contents of RAM will be lost when the power is removed.
There are two main types of RAM: static RAM (SRAM) and dynamic RAM (DRAM).

ROM- READ ONLY MEMORY : A ROM is essentially a memory device for storage purpose
in which a fixed set of binary information is stored. The user must first specify the binary
information to be stored and then it is embedded in the unit to form the required interconnection
pattern. ROM contains special internal links that can be fused or broken. Certain links are to be
broken or blown out to realize the desired interconnections for a particular application and to
form the required circuit path. Once a pattern is established for a ROM, it remained fixed even if
the power supply to the circuit is switched off and then switched on again.
The block diagram of ROM is shown below. It consists of n input lines and m-output lines.
Each bit combination of input variables is called an address and each bit combination that is
formed at output lines is called a word. Thus, an address is essentially binary number that
denotes one of the min-terms of n variables and the number of bits per word is equal to the
number of output lines m. It is possible to generate p = 2n number of distinct addresses from n
number of input variables. Since there are 2n distinct addresses in a ROM, there are 2n distinct
words which are said to be stored in the device and an output word can be selected by a unique
address. The address value applied to the input lines specifies the word at output lines at any
given time. A ROM is characterized by the number of words 2 n and number of bits per word m
and denoted as 2n × m ROM.
For example a 32 × 8 ROM contains 32 words of 8 bits each. This means there are eight output
lines and there are 32 numbers of distinct words stored in that unit, each of which is applied to
the output lines. The particular word selected from the presently available output lines is
determined by five input variables, as there are five input lines for a 32 × 8 ROM, because 2 5 =
32. Five input variables can specify 32 addresses or min-terms and for each address input there is
a unique selected word. Thus, if the input address is 0000, word number 0 is selected. For
address 0001, word number 1 is selected and so on.

A ROM is sometimes specified by the total number of bits it contains, which is 2 n × m. For
example, a 4,096-bit ROM may be organized as 512 words of 8 bits each. That means the device
has 9 input lines (29 × m = 512) and 8 output lines.
In Figure below, the block consisting of an AND array with buffers or inverters is equivalent to a
decoder. The decoder basically is a combinational circuit that generates 2n numbers of minterms
from n number of input lines. 2n or p numbers of minterms are realized from n number of input
variables with the help of n numbers of buffers, n numbers of inverters, and 2n numbers of AND
gates.
Each of the minterms is applied to the inputs of m number of OR gates through fusible links.
Thus, m numbers of output functions can be produced after blowing of some selected fuses. The
equivalent logic diagram of a 2n×m ROM is shown below

ROM has many important applications in the design of digital computer systems. Realization of
complex combinational circuits, code conversions, generating bit patterns, performing arithmetic
functions like multipliers, forming look-up tables for arithmetic functions, and bit patterns for
characters are some of its applications. They are particularly useful for the realization of multiple
output combinational circuits with the same set of inputs. As such, they are used to store fixed bit
patterns that represent the sequence of control variables needed to enable the various operations
in the system. They are also used in association with microprocessors and microcontrollers.
PROGRAMMABLE LOGIC DEVICE-(PLD): The logic devices other than TTL ,CMOS
families whose logical operation is specified by the user through a process called programming
are called Programmable Logic Devices. So, the programmable logic device is the IC that
contain digital logic cells and programmable interconnect . The idea of PLD was first conceived
by Ron Cline from Signetics in 1975 with programmable AND and OR planes. The basic idea
with these devices is to enable the designer to configure the logic cells and interconnect to form a
digital electronic circuit within a single IC package. Here, the hardware resources will be
configured to implement a required functionality. By changing the hardware configuration, the
PLD will operate a different function. The functioning and basic working principle of PLD is
explained below through the diagrams.
There are three types of PLD available. The simple programmable logic device (SPLD), the
Complex programmable logic device(CPLD), and the Field programmable gate array (FPGA).

Device Type AND Array OR Array

ROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed

Simple Programmable Logic Device (SPLD)

The PLD with simple architectural features can be called as SPLD or Simple programmable
Logic Device. The SPLD was introduced prior to the CPLD and FPGA. Based on the
architecture the SPLDs are classified into three types. Programmable logic array (PLA),
Programmable array of logic (PAL), and Generic Array of Logic (GAL).

PLA-Programmable Logic Array

PLA, Programmable Logic Array is a type of LSI device and conceptually similar to a ROM.
However, a PLA does not contain all AND gates to form the decoder or does not generate all the
minterms like ROM. In the PLA, the decoder is replaced by a group of AND gates with
buffers/inverters, each of which can be programmed to generate some product terms of input
variable combinations that are essential to realize the output functions. The AND and OR gates
inside the PLA are initially fabricated with the fusible links among them. The required Boolean
functions are implemented in sum of the products form by opening the appropriate links and
retaining the desired connections.

So, the PLA consists of two programmable planes AND and OR planes . The AND plane
consists of programmable interconnect along with AND gates. The OR plane consists of
programmable interconnect along with OR gates. In this view, there are four inputs to the PLA
and four outputs from the PLA. Each of the inputs can be connected to an AND gate with any of
the other inputs by connecting the crossover point of the vertical and horizontal interconnect
lines in the AND gate programmable interconnect. Initially, the crossover points are not
electrically connected, but configuring the PLA will connect particular cross over points
together. In this view, the AND gate is seen with a single line to the input. This view is by
convention, but this also means that any of the inputs (vertical lines) can be connected. Hence,
for four PLA inputs, the AND gate also has four inputs. The single output from each of the AND
gates is applied to an OR gate programmable inter connect.
Again, the crossover points are initially not electrically connected, but configuring the PLA will
connect particular crossover points together. In this view, the OR gate is seen with a single line
to the input. This view is by convention, but this also means that any of AND gate outputs can be
connected to the OR gate inputs. Hence, for four AND gates, the OR gate also has four inputs

Therefore, the function is implemented in either AND-OR form when the output link across
INVERTER is in place, or in AND-OR-INVERT form when the link is blown off. The general
structure of a PLA with internal connections is shown in figure below.
The size of a PLA is specified by the number of inputs, the number of product terms,and the
number of outputs. The number of sum terms is equal to the number of outputs. The PLA
described in figure above is specified as n × p × m PLA. The number of programmable links is
2n × p + p × m + m, whereas that of ROM is 2 n × m. A typical PLA of 16 × 48 × 8 has 16 input
variables, 48 product terms, and 8 output lines.
To implement the same combinational circuit, a 216 × 8 ROM is needed, which consists of 2 16 =
65536 minterms or product terms. So there is a drastic reduction in number of AND gates within
the PAL chip, thus reducing the fabrication time and cost.
PROGRAMMABLE ARRAY LOGIC (PAL) :
The first programmable device was the programmable array logic (PAL) developed by
Monolithic Memories Inc(MMI). The Programmable Array Logic or PAL is similar to PLA,
but in a PAL device only AND gates are programmable. The OR array is fixed by the
manufacturer. This makes PAL devices easier to program and less expensive than PLA. On the
other hand, since the OR array is fixed, it is less flexible than a PLA device.
The PAL device. has n input lines which are fed to buffers/inverters. Buffers/inverters are
connected to inputs of AND gates through programmable links. Outputs of AND gates are then
fed to the OR array with fixed connections. It should be noted that, all the outputs of an AND
array are not connected to an OR array. In contrast to that, only some of the AND outputs are
connected to an OR array which is at the manufacturer's discretion. This can be clarified by
above, which illustrates the internal connection of a four-input, eight AND-gates and three-
output PAL device before programming. Note that while every buffer/inverter is connected to
AND gates through links, F1-related OR gates are connected to only three AND outputs, F2 with
three AND gates, and F3 with two AND gates. So this particular device can generate only eight
product terms, out of which two of the three OR gates may have three product terms each and the
rest of the OR gates will have only two product terms. Therefore, while designing with PAL,
particular attention is to be given to the fixed OR array.
GAL-Generic Array Logic

PAL and PLA devices are one-time programmable (OTP) based on PROM, so the PAL or PLA
configuration cannot be changed after it has been configured. This limitation means that the
configured device would have to be discarded and a new device configured. The GAL, although
similar to the PAL architecture, uses EEPROM and can be reconfigured.
The Generic Array Logic (GAL) device was invented by Lattice Semiconductor. The GAL was
an improvement on the PAL because one device was able to take the place of many PAL devices
or could even have functionality not covered by the original range. Its primary benefit, however,
was that it was erasable and re-programmable making prototyping and design changes easier for
engineers. The GAL is very useful in the prototyping stage of a design, when any bugs in the
logic can be corrected by reprogramming.
Complex Programmable Logic Device (CPLD):
CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then
in three additional series, called MAX 5000, MAX 7000 and MAX 9000. The CPLD is the
complex programmable Logic Device which is more complex than the SPLD. This is build on
SPLD architecture and creates a much larger design. Consequently, the SPLD can be used to
integrate the functions of a number of discrete digital ICs into a single device and the CPLD can
be used to integrate the functions of a number of SPLDs into a single device.
So, the CPLD architecture is based on a small number of logic blocks and a global
programmable interconnect. Instead of relying on a programming unit to configure chip , it is
advantageous to be able to perform the programming while the chip is still attached to its circuit
board. This method of programming is known is called In-System programming (ISP). It is not
usually provided for PLAs (or) PALs , but it is available for the more sophisticated chips known
as Complex programmable logic device.

The CPLD consists of a number of logic blocks or functional blocks, each of which contains a
macrocell and either a PLA or PAL circuit arrangement. In this view, eight logic blocks are
shown. The building block of the CPLD is the macro-cell, which contains logic implementing
disjunctive normal form expressions and more specialized logic operations. The macro cell
provides additional circuitry to accommodate registered or nonregistered outputs, along with
signal polarity control. Polarity control provides an output that is a true signal or a complement
of the true signal. The actual number of logic blocks within a CPLD varies; the more logic
blocks available, the larger the design that can be configured.

In the center of the design is a global programmable interconnect. This interconnect allows
connections to the logic block macrocells and the I/O cell arrays (the digital I/O cells of the
CPLD connecting to the pins of the CPLD package).The programmable interconnect is usually
based on either array-based interconnect or multiplexer-based interconnect:• Array-based
interconnect allows any signal within the programmable interconnect to connect to any logic
block within the CPLD.
This is achieved by allowing horizontal and vertical routing within the programmable
interconnect and allowing the crossover points to be connected or unconnected (the same idea as
with the PLA and PAL), depending on the CPLD configuration.
• Multiplexer-based interconnect uses digital multiplexers connected to each of the macrocell
inputs within the logic blocks. Specific signals within the programmable interconnect are
connected to specific inputs of the multiplexers. It would not be practical to connect all internal
signals within the programmable interconnect to the inputs of all multiplexers due to size
and speed of operation considerations.

FPGAs – FIELD PROGRAMMABLE GATE ARRAYS

The FPGA concept emerged in 1985 with the XC2064TM FPGA family from Xilinx . The
“FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that
can be viewed as standard components.” The individual cells are interconnected by a matrix of
wires and programmable switches. A user's design is implemented by specifying the simple
logic function for each cell and selectively closing the switches in the interconnect matrix. The
array of logic cells and interconnect form a fabric of basic building blocks for logic circuits.
Complex designs are created by combining these basic blocks to create the desired circuit.

Unlike CPLDs (Complex Programmable Logic Devices) FPGAs contain neither AND nor OR
planes.The FPGA architecture consists of configurable logic blocks, configurable I/O blocks,
and programmable interconnect. Also, there will be clock circuitry for driving the clock signals
to each logic block, and additional logic resources such as ALUs, memory, and decoders may be
available. The two basic types of programmable elements for an FPGA are Static RAM and anti-
fuses.
Each logic block in an FPGA has a small number of inputs and one output. A look
up table (LUT) is the most commonly used type of logic block used within FPGAs.
There are two types of FPGAs.(i) SRAM based FPGAs and (ii) Antifuse technology based(OTP)

Every FPGA consists of the following elements

 Configurable logic blocks(CLBs)

 Configurable input output blocks(IOBs)
 Two layer metal network of vertical and horizontal lines for interconnecting the CLBS
Configurable logic blocks(CLBs):
The configurable logic block is the basic logic cell and it is either RAM based or PLD based .
It consists of registers (memory), Muxes and combinatorial functional unit. An array of CLBS
are embedded within a set of vertical and horizontal channels that contain routing which can be
personalized to interconnect CLBs.

Configurable Input / Output logic locks (IOBs):

CLBs and routing channels are surrounded by a set of programmable I/Os which is
an arrangement of transistors for configurable I/O drivers.
Programmable interconnects:
These are un programmed interconnection resources on the chip which have
channeled routing with fuse links. Four types of interconnect architectures are available. They
are
 Row-Column Architecture
 Island Style Architecture
 Sea-of-Gates Architecture
Advantages of FPGAs:
  Design cycle is significantly reduced. A user can program an FPGA design in a few
minutes or seconds rather than weeks or months required for mask programmed parts.
 High gate density i.e, it offers large gate counts.
 No custom masks tooling is required (Low cost).
 Low risk and highly flexible.
 Reprogram ability for some FPGAs (design can be altered easily).
 Suitable for prototyping.
 Parallelism
 Allows for system-level extraction of parallelism to match input data
at design time
 Huge computational capability
 Fast development and Dynamic reconfiguration
 Updating new pattern matching rules (or simply rules)
 Device should not stop when updating new rules
 Update time for new rules
 To provide fast response to new attacks, the compilation and updating
time for new rules needs to be short

 In case of a hardwired FPGA architecture, the update time is mostly dependent

on place & route time
 Memory-based units can provide near instantaneous updates
Limitations:

 Speed is comparatively less.

 The circuit delay depends on the performance of the design implementation tools.
 The mapping of the logic design into FPGA architecture requires sophisticated design
implementation (CAD) tools than PLDs.
FPGA Programming Technologies:
(a) Antifuse Technology:
An antifuse is a two terminal device that when un-programmed has a very high resistance
between the two terminals and when programmed, or “blown”, creates a very low resistance or
permanent connection. The application of a high voltage from 11 V to 21 V will create the low
resistive permanent connection. Antifuse technologies come in two types. The first is oxide-
nitride-oxide (ONO) dielectric based and the other is amorphous silicon or metal-to-metal
antifuse structures.
Dielectric based antifuses consist of a dielectric material between N+ diffusion and polysilicon
which breaks down when a high voltage is applied. Early dielectrics were a single-layered oxide
dielectric until Actel came out with the programmable low impedance circuit element (PLICE),
which is a multi-layer oxide-nitride-oxide (ONO) dielectric fuse. A high voltage across the
PLICE melts the dielectric and creates polycrystalline silicon between the terminals. When the
PLICE is blown, it adds three layers rather than the double metal CMOS process. The layers are
a thin layer of oxide an top off the N+ surface, Low-pressure Chemical Vapor Deposition
(LPCVD) nitride and the reoxidized top oxide. The programming current has an important effect
because the higher the current during programming, the lower the link resistance, resulting in
smaller thickness for the antifuse material. Programming circuits for antifuses need to supply
high currents (15 ma for Actel) to insure high reliability and performance.
Amorphous silicon antifuse technology is the alternative to dielectric antifuse. It consists of
amorphous silicon between two layers of metal that changes phases when current is applied.
When the antifuse is not programmed the amorphous silicon has a resistance of 1 Giga ohm.
When a high current (about 20 mA) is applied to the anitfuse the amorphous silicon changes into
a conductive polysilicon link. Quick Logic pASIC FPGA is a perfect example of an amorphous
silicon antifuse technology.
(b). SRAM-based Technology:
SRAM FPGA architecture consists of static RAM cells to control pass gates or multiplexers.
The FPGA speed is determined by the delay introduced by the logic cells and the routing
channels. Multiplexers, look-up tables and output drivers affect the speed of signals through the
logic cells. An FPGA with more PIPs is easier to route but introducing more routing delay. The
size of the look-up table plays an important role depending on the design. Smaller LUTs provide
higher density but larger ones are preferred for high-speed applications.
Distinguish between SRAM and Antifuse Technologies: The following points explains the
differences between the two technologies.
1. Antifuse programming technology is faster than SRAM programming technology due to the
RC delays introduced by the interconnect structure.
2. Antifuse technology has more silicon area per gate and is easier to route than SRAM
technology.
3. A disadvantage of antifuse FPGA is that they require more process layers and mask steps and
also contain high voltage programming transistors.
4. SRAM-based technology contains higher capacity than antifuse technologies.
5. SRAM based technology is very flexible with in-system programmability and the ability to
reconfigure the design during the debugging stage while antifuse technology is one-time
programmable (OTP). This ability reduces design and development, which reduces overall
cost of the design. Another advantage to this is that SRAM technology can be programmed at
the factory through complete verification test where the antifuse are tested as “blanks” and
require programming by the user to verify design requirements and operation.
6. A disadvantage of SRAM technology is that it is volatile meaning it has to be reprogrammed
every time power is turned off and on again. The SRAM usually require an extra memory
element to program the chip which occupies board space .

Standard cells:
In semiconductor design, standard cell methodology is a method of designing application-
specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology
is an example of design abstraction, whereby a low-level very-large-scale integration
(VLSI) layout is encapsulated into an abstract logic representation (such as a NAND gate). Cell-
based methodology — the general class to which standard cells belong — makes it possible for
one designer to focus on the high-level (logical function) aspect of digital design, while another
designer focuses on the implementation (physical) aspect. Along with semiconductor
manufacturing advances, standard cell methodology has helped designers scale ASICs from
comparatively simple single-function ICs (of several thousand gates), to complex multi-million
gate system-on-a-chip (SoC) devices.

A standard cell is a group of transistor and interconnect structures that provides a boolean logic
function (e.g., AND, OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The
simplest cells are direct representations of the elemental NAND, NOR, and XOR boolean
function, although cells of much greater complexity are commonly used (such as a 2-bit full-
adder, or muxed D-input flipflop.) The cell's boolean logic function is called its logical view:
functional behavior is captured in the form of a truth table or Boolean algebraequation (for
combinational logic), or a state transition table (for sequential logic).
Usually, the initial design of a standard cell is developed at the transistor level, in the form of
a transistor netlist or schematic view. The netlist is a nodal description of transistors, of their
connections to each other, and of their terminals (ports) to the external environment. A schematic
view may be generated with a number of different Computer Aided Design(CAD) or Electronic
Design Automation(EDA) programs that provide a Graphical User Interface (GUI) for this netlist
generation process. Designers use additional CAD programs such as SPICE or Spectre to
simulate the electronic behavior of the netlist, by declaring input stimulus (voltage or current
waveforms) and then calculating the circuit's time domain (analogue) response. The simulations
verify whether the netlist implements the desired function and predict other pertinent parameters,
such as power consumption or signal propagation delay.
Since the logical and netlist views are only useful for abstract (algebraic) simulation, and not
device fabrication, the physical representation of the standard cell must be designed too. Also
called the layout view, this is the lowest level of design abstraction in common design practice.
From a manufacturing perspective, the standard cell's VLSI layout is the most important view, as
it is closest to an actual "manufacturing blueprint" of the standard cell. The layout is organized
into base layers, which correspond to the different structures of the transistor devices,
and interconnect wiring layers and via layers, which join together the terminals of the transistor
formations. The interconnect wiring layers are usually numbered and have specific via layers
representing specific connections between each sequential layer. Non-manufacturing layers may
be also be present in a layout for purposes of Design Automation, but many layers used
explicitly for Place and route (PNR) CAD programs are often included in a separate but
similar abstract view. The abstract view often contains much less information than the layout and
may be recognizable as a Layout Extraction Format (LEF) file or an equivalent.
After a layout is created, additional CAD tools are often used to perform a number of common
validations. A Design Rule Check (DRC) is done to verify that the design meets foundry and
other layout requirements. A Parasitic Extraction (PEX) then is performed to generate a PEX-net
list with parasitic properties from the layout. The nodal connections of that net list are then
compared to those of the schematic net list with a Layout Vs Schematic (LVS) procedure to
verify that the connectivity models are equivalent.

Application of Standard cell:

Strictly speaking, a 2-input NAND or NOR function is sufficient to form any arbitrary Boolean
function set. But in modern ASIC design, standard-cell methodology is practiced with a sizable
library (or libraries) of cells. The library usually contains multiple implementations of the same
logic function, differing in area and speed. This variety enhances the efficiency of automated
synthesis, place, and route (SPR) tools. Indirectly, it also gives the designer greater freedom to
perform implementation trade-offs (area vs. speed vs. power consumption). A complete group of
standard-cell descriptions is commonly called a technology library.
Commercially available Electronic Design Automation (EDA) tools use the technology libraries
to automate synthesis, placement, and routing of a digital ASIC. The technology library is
developed and distributed by the foundry operator. The library (along with a design netlist
format) is the basis for exchanging design information between different phases of the SPR
process.
Programmable Array logic:
The PAL device is a special case of PLA which has a programmable AND arrayand a fixed OR
array. The basic structure of Rom is same as PLA. It is cheap comparedto PLA as only the AND
array is programmable. It is also easy to program a PALcompared to PLA as only AND must be
programmed.
The figure 1 below shows a segment of an unprogrammed PAL. The input bufferwith non
inverted and inverted outputs is used, since each PAL must drive many ANDGates inputs. When
the PAL is programmed, the fusible links (F1, F2, F3…F8) areselectively blown to leave the
desired connections to the AND Gate inputs. Connectionsto the AND Gate inputs in a PAL are
represented byXs, as shown here:

Figure 1: segment of an un programmed and programmed PAL.

As an example, we will use the PAL segment of figure 1 to realize the function I1I2‘+I1I2. The
Xs indicate that the I1 and I2‘ lines are connected to the first AND Gate, and the I1‘ and I2 lines
are connected to the other Gate. Typical combinational PAL have 10 to 20 inputs and from 2 to
10 outputs with 2to 8 AND gates driving each OR gate. PALs are also available which contain D
flip-flop switch inputs driven from the programming array logic. Such PAL provides a
convenient way of realizing sequential networks. Figure 2 below shows a segment of a
sequential PAL. The D flip-flop is driven from the OR gate, which is fed by two AND gates. The
flip-flop output is fed back to the programmable AND array through a buffer. Thus the AND
gate inputs can be connected to A, A‘, B, B‘, Q, or Q‘. The Xs on the diagram show the
realization of the next-state equation.

Q+ = D = A‘BQ‘ + AB‘Q

The flip-flop output is connected to an inverting tristate buffer, which is enabled when

EN = 1

Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4.This PAL has an
AND gate array with 16 input variables, and it has 4 D flip-flops. Each flip-flop output goes
through a tri state-inverting buffer (output pins 14-17). One input(pin 11) is used to enable these
buffers. The rising edge of a common clock (pin 1) causes the flip-flops to change the state. Each
D flip-flop input is driven from an OR gate, and each OR gate is fed from 8 AND gates. The
AND gate inputs can come from the external PAL inputs (pins2-9) or from the flip-flop outputs,
which are fed back internally. In addition there are four input/output (i/o) terminals (pins
12,13,18 and 19), which can be used as either network outputs or as inputs to the AND gates.
Thus each AND gate can have a maximum of 16 inputs (8 external inputs, 4 inputs fed back
from the flip-flop outputs, and 4 inputs from the i/o terminals). When used as an output, each I/O
terminals driven from an inverting tri state buffer. Each of these buffers is fed from an OR gate
and each OR gate is fed from 7 AND gates. An eighth AND gate is used to enable the output.
Design Approach:

n CMOS integrated circuit design there is a trade-off between static power consumption and
technology scaling. Recently, the power density has increased due to combination of higher
clock speeds, greater functional integration, and smaller process geometries. As a result static
power consumption is becoming more dominant. This is a challenge for the circuit designers.
However, the designers do have a few methods which they can use to reduce this static power
consumption. But all of these methods have some drawbacks. In order to achieve lower static
power consumption, one has to sacrifice design area and circuit performance. In this paper, we
propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body
Biasing technique without being penalized in area requirement and circuit performance
 CMOS TESTING:
CMOS TESTING

Testing is one of the most expensive parts of chips

1) Logic verification accounts for > 50% of design effort for many chips

2) Debug time after fabrication has enormous opportunity cost

3) Shipping defective parts can sink a company

NEED FOR TESTING:

The need of testing is to find out errors in the application.

The good reasons of testing are

1) Quality Assurance.

2) Verification and validating the product/application before it goes live in the market.

3) Defect free and user friendly.

4) Meets the requirements.

Logic Verification:

1) Does the chip simulate correctly?

2) Usually done at HDL level

3) Verification engineers write test bench for HDL

• Can’t test all cases

• Look for corner cases

• Try to break logic design

Ex: 32-bit adder

Test all combinations of corner cases as inputs:

• 0, 1, 2, 231-1, -1, -231, a few random numbers Good tests require ingenuity.

Manufacturing Test: A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < 100%

Must test chips after manufacturing before delivery to customers to only ship good parts.

1) Manufacturing testers are very expensive

2) Minimize time on tester

3) Careful selection of test vectors

Observability & Controllability:

Observability: ease of observing a node by watching external output pins of the chip

Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip

Combinational logic is usually easy to observe and control. Finite state machines can be very difficult,
requiring many cycles to enter desired state especially if state transition diagram is not known to the
test engineer.

Test Pattern Generation:

Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the
smallest sequence of test vectors necessary to prove each node is not stuck.

Good observability and controllability reduces number of test vectors required for manufacturing test.

1) Reduces the cost of testing

2) Motivates design-for-test.

Design for Test:

Design the chip to increase observability and controllability.

If each register could be observed and controlled, test problem reduces to testing combinational logic
between registers.

Better yet, logic blocks could enter test mode where they generate test patterns and report the results
automatically.

Scan: Convert each flip-flop to a scan register

``