CACHE MAPPING

Main memory

Cache 0 0123
Virtually B
0 divided 1 4567 L
L O
1 2 8 9 10 11
I C
N 12 13 14 15 K
2
E S
3 S
15 60 61 62 63
Number of lines in Cache 16 Words
= total number of Words in cache 64 Words
memory / Block Size
= 16/4 = 4 lines
Assuming 1 Word = 1 Byte Block Size = 4 words
Minimum addressable unit in Computer Number of Blocks in Main Memory
= Word, CPU is interested in Words = total number of Words in Main
memory/Block Size
William Stalling, chap 4 = 64/4 =16 blocks
LECTURE 13 14 and 15 CACHE MAPPING 1
Eighth edition Cache
 DIRECT MAPPING
• To address 64 words of main memory we
require 6 bits. Main memory

0
• For e.g. 000101address means that 0123

1 4567
CPU is interested in 5th word from main
2 8 9 10 11
memory. 12 13 14 15

• The address is divided into two parts:

15 60 61 62 63
4 BIT Block
number 000101 2 BIT Block offset 64 Words

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 2
Eighth edition Cache
 DIRECT MAPPING Main
memory
Many to one function
Cache 0 0123

0 blocks 0 0 4 8 12 1 4567
1
1 1 5 9 13 2 8 9 10 11
2
3 line
2 2 6 10 14 3 12 13 14 15
4
5 0 3 3 7 11 15
6 1 Block
7 2 16 Words 15 60 61 62 63
number
8 3
9 0000 0100 1000 1100 64 Words
10 0001 0101 1001 1101
11 0010 0110 1010 1110 Physical Address
12 0011 0111 1011 1111 ____ __
13
14
MSB shows Tag bit LSB shows line number Block
15
William Stalling, chap 4 Block Number offset3
LECTURE 13 14 and 15 CACHE MAPPING
Eighth edition Cache
 Direct Mapping
A comparator is required to
Tag bit line # line offset
compare tag bit.
2 bit 2 bit 2 bit

6 bit Physical Address 00 00 00,

00 00 01,
00 00 10,
tag line 00 00 11,
11 01 00,
00 0 0,1,2,3 11 01 01,
11 1 52,53,54,55 11 01 10,
11 01 11,
10 2
11 3
QS: So if CPU generate address
Cache 110110, would it be a cache Hit or
Miss?

QS: What about 100111?

William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 4
Eighth edition Cache
 problems
Main memory Cache Size Block Size Tag bits Tag Directory
Size Size
128 KB 16 KB 256 B ? ?
32 GB 32 KB 1 KB ? ?
? 512 KB 1 KB 7 ?
16 GB ? 4 KB 10 ?

Assume the memory is byte addressable

Tag Line No. Offset
PA = 17 bits 3 6 8
Cache lines = Cache Size/ block Size
= 16 KB/256 B = 214-8= 26 17 bits
Block Offset = 256 bytes = 28
Tag Directory Size = Sum of all the tag
bits associated with cache lines= Cache
Lines X tag bits = 26 X 3 William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 5
Eighth edition Cache
 Direct mapping Summary
• The address is broken into three parts: (s-r) MSB bits represent the tag to
be stored in a line of the cache corresponding to the block stored in the
line; r bits in the middle identifying which line the block is always stored
in; and the w LSB bits identifying each word within the block. This means
that:
• The number of addressable units = 2s+w words or bytes
• The block size (cache line width not including tag) = 2w words or bytes
• The number of blocks in main memory = 2s (i.e., all the bits that are not in
w)
• The number of lines in cache = m = 2r
• The size of the tag stored in each line of the cache = (s - r) bits
• Direct mapping is simple and inexpensive to implement, but if a program
accesses 2 blocks that map to the same line repeatedly, the cache begins
to thrash back and forth reloading the line over and over again meaning
misses are very high.

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 6
Eighth edition Cache
 Mapping of Block on Cache line

• For 64 word main memory and 16 word cache,

the upper 4 MSb shows the block number
and the least 2 LSb of the 4 MSb identified as
Block number
line number. or Block Address offset

l
m
No Of Blocks in the Cache

Block Address % No Of blocks in the Cache =

cache line = m % 2l
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 7
Eighth edition Cache
 Example
• If CPU is interested in block number 0,1,2,6,8
… then ( here m = 4 bits, l= 2bits)
• 0 mod 22 = 0 mapped to 0th line 08

1
• 1 mod 2 = 1 mapped to 1 line
2 st
26
• 2 mod 22 = 2 mapped to 2nd line
• 6 mod 22 = 2 mapped to 2nd line
• 8 mod 22 = 0 mapped to 0th line
CONFLICT MISS
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 8
Eighth edition Cache
 Example
• What if block number 0,4,8,12,16 are
requested

0 4 8 12 16

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 9
Eighth edition Cache
 Advantages and Disadvantages of
Direct mapping
• Simple
• Only tag bit is compare associated to Single
line in Cache.
• Conflict miss issue.

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 10
Eighth edition Cache
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 11
Eighth edition Cache
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 12
Eighth edition Cache
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 13
Eighth edition Cache
 How to handle Write Operation
in Memory Systems
• Writing in the cache raises several additional
issues.
• First assumes that the address, we want to
write to is already loaded in the cache. We will
assume a simple data mapped Cache.

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 14
Eighth edition Cache
 Issues

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 15
Eighth edition Cache
 Write Through Cache

Performance,
latency,
bandwidth, Slow? Write buffer
William Stalling, chap 4
LECTURE 13 14 and 15 CACHE MAPPING 16
Eighth edition Cache
 Write back Cache

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 17
Eighth edition Cache
 Finishing the Write back

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 18
Eighth edition Cache
 Write-back Cache
Discussion

William Stalling, chap 4

LECTURE 13 14 and 15 CACHE MAPPING 19
Eighth edition Cache