2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

Design and Analysis of a 2.4 GHz Fully Integrated

1.8V Power Amplifier in TSMC l80nm CMOS RF
Process for Wireless Communication

Santosh B. Patil Rajendra D. Kanphade

VLSI &ESD Center, SGlARC, N utan Maharashtra Institute Of
S.S.G.M. College of Engineering, Technology & Engineering
Shegaon, India Talegaon(D),Pune, India
[email protected] [email protected]

Abstract-Fully integrated single stage 1.8V power amplifier consumption of the whole transceiver. The efficiency of the
working at 2.4GHz is designed in TSMC 180nm CMOS RF power amplifier becomes one of the crucial parameters to be
process. In this paper, cascode topology with inductively optimized for power saving. However, the efficiency of the
degenerated common-source CMOS power amplifier is suggested power amplifier is degraded by reducing supply voltage.
with improved gain, isolation, better stability and sufficient Efficiency and linearity are the major considerations when a
linearity over the operating range. Though noise figure is not that
class of power amplifier is to be selected. It is very important to
much relevant for PA design, optimum matching network is
understand the specifications of the power amplifier in advance
designed to minimize the noise figure (NF) and maximize the
because different applications will result in different choices of
power gain. The proposed circuit is simulated using Cadence
power amplifiers. PA performance in all the classes is
EDA tools (Version IC 6.14). Results showed that PA delivered
summarized in table 1.
14.08dBm output power with 37% power-added efficiency (PAE)
at 1.8V. The proposed PA has a linear power gain of 15.91 dB, TABLE I. PERFORMANCE SUMMARIES OF DIFFERENT CLASSES OF
Sl1 and S22 is -12.66dB and -9.22dB respectively and it offers POWER AMPLIFIERS
better isolation (-22.56dB) between the ports. The circuit
Class Ideal Line.arity Practical Process
consumed 10.69mW power. Finally, PA is laid out using Cadence
Efficiency efficiency
virtuoso layout out editor and its size is O.079mm2. Class A 50% Good 35% sOl 0.5!,m CMOS [4)
ClassAB 50% · 78 .5% Good 45% 0 . 35/lmCMOS [5)
Index Terms-An inductively degenerated PA, Cascode Class B 78.5% Moderate 49% PHEMT [6)
Topology, Layout, S- parameter analysis, TSMC 180nm CMOS Class C 78.5% · 1 00% Poor 55% 0.6.u mCMOS [7)
Class E 100% Poor 62% 0.35 !,mCMOS [8)
RF process.
Class F 100% Poor 80% PHEMT 161

I. INTRODUCTION This paper presents, a single ended power amplifier

operated at 2.4GHz and I.8V supply designed in TSMC I80nm
Gallium Arsenide (GaAs), BiCMOS and silicon bipolar are
RF CMOS technology. A common-gate Class E output stage,
some of the the dominant technologies used for RF front-end
which operates under low supply voltage without degrading the
circuits. These technologies offer higher breakdown voltage,
efficiency, is proposed. A pre-amplifier with positive feedback
lower substrate loss and higher quality of monolithic inductors
configuration is employed to drive the common-gate output
and capacitors compared with CMOS technology. However,
stage.
they are much more expensive. The realization of RF front-end
circuits using CMOS technology can provide single-chip
solution which greatly reduces the cost. Moreover, the advance IT. DESIGN METHODOLOGY
in CMOS process has made it more possible to realize CMOS Among all classes of non-linear power amplifiers, the class­
RF circuits with performance comparable to that using GaAs, E power amplifier is the most attractive candidate in terms of
BiCMOS and silicon bipolar. Most of the essential building circuit simplicity and high efficiency performance (Table 1).
blocks of a receiver, such as LN A, mixer, frequency Class-E configuration is used to design the proposed power
synthesizer and IF filters, have been realized by CMOS amplifier at I.8V. Typically, class-E amplifier can operate with
processes [1,2]. However, not much work has been done or power losses smaller than a factor of about 2.3 compared with
reported on CMOS power amplifier, in particular at low supply conventional class-B or class-C amplifiers using same
voltage. As supply voltage is reduced, performance of PA in transistors at same frequency and output power [9]. A typical
terms of output power and efficiency are degraded. CMOS RF class-E amplifier in cascade topology is shown in Fig.I. During
front-end circuits are capable to meet the specifications in most operation the common source transistor acts as a simple switch
of the applications so that the whole system can be integrated owing to the hard driving action of the input waveform. If the
into one chipset [3]. voltage reaches sufficiently high, the common gate transistor is
The PA, compared with other building blocks of a also switched, provided the cascode bias voltage Vb is high
transceiver, contributes the most in terms of power enough to put transistor M2 in triode region. In this case, with

978-1-4799-7926-4115/$31.00©2015 IEEE
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

lower drain-gate voltage swing the amplifier reliability can be

increased. It has also been observed that, this implementation d

�
increases the amplifier input-output isolation by decreasing the
Miller multiplication effect and also helps in improving the
stability [10]. Rlo.d

f
02
The common-source (CS), common-gate (CO) topology
Rb
has one of the major advantages that it allows independent
optimization of noise and linearity by optimizing the CS and G2
CO transistors separately [11-13]. Moreover, compared to the
CS amplifier, the drain-gate capacitance of CG transistor is no Vin
�:n G1 :41...- ------IJ

Cb
longer connected between output and input of amplifier. Thus,
reverse isolation and stability are improved. Furthermore, Rg . Sl
because the input resistance of the CO is small, the voltage S
gain of the CS is almost unity, assuming that the CS and CG
have the same transconductance. Thus, the Miller capacitance V'g
appearing at input of CS, due to its drain-to-gate parasitic
capacitance , is very small. Tn this paper same topology is used
for the proposed PA. A self biasing cascode amplifier, shown Fig.2. A self Biased cascode amplifier [14]

in Fig.2, is proposed in [14] allows us to design PA such that

both transistors get the same maximum gate-drain voltage. As a � (N 1:138) to withstand a larger output voltage swing thereby
result we can have a RF swing at D2 before encountering hot mcreasmg output power. M2(NM38) is converted from a
carrier degradation. The bias for G2 is provided by Rb-Cb. The common gate (CG) to common source amplifier by the current
DC voltage applied to 02 is same as DC voltage applied to D2. reused technique. Capacitors C7 and C4 at input and output
The RF swing is attenuated by low pass nature of Rb-Cb. The stage is for DC blocking and inductors LO and L1 forms
values of Rb-Cb can be chosen for the optimum performance inductive source degeneration with transistor MI(NM38),
and equal to gate-drain swing of Ml and M2. which helps in reducing circuit noise. Ml(NM37) and M3
(NM36) are current mirrors used to enlarge the gain.
Ml(NM38) is properly biased to achieve sufficient linearity
and efficiency.

VOG2i
Vbo I

Fig.l. Cascode Class-E Amplifier

FigJ A proposed PA design in Cadence Virtuoso

Ill. PROPOSED POWER AMPLIFIER DESIGN
Based methodologies explained in section 11, the proposed
PA is designed as shown in Fig.3. The wideband matching is IV. SIMULATION RESULTS AND PERFORMANCE ANALYSIS
improved by resistive shunt feedback and inductance source Test bench setup for simulating PA results is shown in FigA.
degeneration used to obtain stability of amplifier. A method for
Results are validated using parameters like port isolation, gain,
increasing maximum useable supply voltage in an amplifier
linearity, impedance matching, stability and power dissipation.
circuit is presented. A self-biased cascode amplifier circuit
Return loss is a measure of the input and output matching
composed of Ml(NM38) and M2(NM38) connected in series
conditions. . A return loss greater than 10 dB, at the input and
and input RF signal terminal is applied to gate of MI(NM38).
the output, usually indicates acceptable power transfer
Gate of the M2(NM38) is connected to VDD through R7 and
conditions. A match is good if the return loss is high. PA is
its biased is provided by R7-C7. This configuration does not
designed to match with 50n input and output impedance.
use complex biasing circuitry and permits Ml(NM37) and
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

freQ(GHl)

Fig.4. Test bench setup for PA simulations

Fig.6. GTGAGP

From the simulation results shown in Fig.5, it is evident that

between the output signal and the input signal. Here both input
that proposed power amplifier has -12.66 dB input return loss
and output impedances are kept to 500. PA has power gain of
and - 9.932 dB output return loss at 2.40Hz. As both S11 and
15.91 dB at 2.40Hz frequency (Fig.5.). This is also evident
S22 well less than -10 dB, it can be said that the circuit is
from the transient response shown in Fig.l o.
properly matched. Also, the resulted three power gains
transducer power gain (GT ), available power gain (GA) and Stability test is very important in power amplifier analysis
operating power gain (OP ) coincide at same point at 2.4 OHz, as circuit might oscillate because of voltage variations at
shown in Fig.6, this means input and output matching is unexpectedly high or low frequencies. Specially, when there is
perfect. a feedback path from output to input, the circuit might become
unstable for certain combinations of source and load
impedances. According to Rollett stability factor (K) as given
in equation (1) when K > 1 and � < 1, the circuit is
unconditionally stable. To ensure stability over a wide range of
frequencies, the stability was tested from 100 MHz up to 5
OHz. The Fig.7 shows Kf (K) is 1.056 and B1f (�) is 0.7783
Therefore, it can be said that amplifier is very much stable
around 2.40Hz frequency range.

(1)

Fig.5. S-Parameter Results

Rreverse isolation is important to quantify in PA

performance analysis as practically some signal transmitted
back to the input from the output (Ideally should be no back
reflection). This unwanted reverse signal interferes with
fundamental signal flowing in forward direction from input to
the output. Tn our proposed PA design, the active output
matching stage (source-follower) does not easily allow signals
to propagate from source terminal of transistor to gate terminal.
Fig.5 shows that PA has -22.56 dB reverse isolation at 2.4GHz.
This figure is within the acceptable range. Power gain is the "
(req (GHrJ

measure of the variation of gain over a specified frequency

range. Power gain is defined as the difference in power Fig.7. kfBlf
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

N onlinear amplifier can corrupt RF input signal and cause

various types of distortion like harmonic distortions, cross
modulation, gain compression, intermodulation etc. PA
linearity is characterized by the I dB compression point (PI
dB) and the 3rd order interception point (lP3). The I dB
compression point is the point at which the actual output power
is 1 dB below the expected value for a linear amplifier and the
third-order intercept point is the input power level at which the
first and third order harmonics have same output power level.
From the graph shown in Fig.8 and Fig.9 respectively, the IdB
point is -3.38dBm and TP3 is -28.122dBm, which shows that
the proposed power amplifier is sufficiently liner over the
operating frequency range.

Fig.lO. Transient Response- Input (NeWS) and Output (Net4)

TABLE II. PA SPECTFTCAnON AND SIMULATED RESULTS

Parameter Targeted Specification Simulation Result

Pl-ocess TSMC 180nm TSMC 180nm

Supply Voltage 1.8V 1.8V

Frequency 2.4 GHz 2.4 GHz

Source/Load !vIa Tching 500hm 50 0hm

Noise Figure 2dB I . 070 dE

Input rerumloss (S II) ·10 dE -12.66 dE

Isolation (S 12) -20 dE -22.56 dE

Power Gain (S2 1) 20 dE 15. 91dE

OutpuTreturn loss (S22) ·IOdE -9.932 dE

P IdBPoint Sufficient ovel-operating range -3.38 dEm

Fig.S. I dB Compression Point lIP3Point Sufficient over operating range -28.122dBm

OutpuTPO\Vel- Adequate 14.08dBm

Periodic Steadv Slate Responle
PAE 40-50% 37%

CUtTen! consumption <3nlA <5.93mA

Power Consumption 5-10m\V IO.69mW

V. PERFORMANCE COMPARISON WITH RECENT POWER

AMPLIFIERS AT 2.4 GHz

Though, most of the reported design used different

topologies and presented the results at different frequency band
depending on intended applications, we tried to compare our
design with others. The comparison (Table 3) shows that the
proposed design yield better results when compared with recent
work in this direction.

Parameters Ibis [11] [12] [13] [15]1 [16]b [17]{

Work
Frequency (GHz) 2 .4 3.1·4.8 2.4 2.4 3.1·4.8 3-5 3.1·4.8
Fig.9. 3'd order intercept point CMOS Process (�lm) 0.18 0.18 0.18 0.18 0.18 0.18 0.18
Supply vo1ta.ge 00 1.8 1 3.3 2.5 0.18 .. 1.9
After the DC simulation, we got the current value of .. .. .. ..
Power conSlunption (m\\� 10.69 22 25
5.93mA. So the power dissipation is 10.69mW
POlrer gain - S2 1 (dB) 15.91 18.4 .. .. 19 17.5 223
(1.8V*5.93mA). Table 2 summarizes the performance of the
proposed power amplifier Output Power (dBm) 14.08 6.4 23 12 1. )"( 0.42 ..
PAr (%) 37 18.4 44.5 43.6 .. 3.9 ..
.a. Pre·layoutslmulatlon resu�
b . Measurement result
c. Estimated va lue
 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA)

VI. PA LAYOUT proposed design offers a power gain of 15.91 with 37% PAE
Using Cadence Virtuoso layout editor (Version 6.14) the under 1.8V supply. It is capable of delivering output power
proposed PA is laid in TSMC 180nm RF CMOS process in 14.08dB with high efficiency. As explained and proved by
which first level of metal is the most resistive while top level of simulation results the proposed PA is sufficiently linear and
metals the least resistive. The metals are separated by a stable at 2.4GHz frequency. Layout size is is 0.079mm2
polysilicon layer. Vias used to connect one metal to other. The
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