Logic Circuits and Switching Theory

DIGITAL ELECTRONICS Example: 125.17510 → 𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 16 (ℎ𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒)

 a field of electronics involving the study of digital signals and
the engineering of devices that use or produce them. 𝟕𝟕𝟕𝟕
125 ÷ 16 𝟏𝟏𝟏𝟏 0.175 × 16 4
7 𝟐𝟐
16 5
.Number system. 7 ÷ 16 𝟕𝟕 4
× 16 𝟏𝟏𝟏𝟏
4
 system of wri�ng to express number. 16 5 5
 Mathema�cal nota�on for represen�ng numbers of a given set 4 4
× 16 𝟏𝟏𝟏𝟏
by using digits (0-9) or other symbols (A-F) in a consistent 5 5
manner. 4 4
× 16 𝟏𝟏𝟏𝟏
• Decimal -Base 10, (0-9) 5 5
• Binary – Base 2, (0,1) 4
× 16 𝟏𝟏𝟏𝟏
4
• Octal – Base 8, (0-7) 5 5
4 4
• Hexadecimal – Base 16 (0-9, A-F) × 16 𝟏𝟏𝟏𝟏
5 5
…. ……

BASE n to DECIMAL
𝟎𝟎. 𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 ….
𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎. 𝑓𝑓𝑓𝑓ℎ𝑛𝑛 = (𝑎𝑎 × 𝑛𝑛3 ) + (𝑏𝑏 × 𝑛𝑛2 ) + (𝑐𝑐 × 𝑛𝑛1 )
+ (𝑑𝑑 × 𝑛𝑛0 ) . (𝑒𝑒 × 𝑛𝑛−1 ) + (𝑓𝑓 × 𝑛𝑛−2 ) (𝟏𝟏𝟏𝟏𝟏𝟏. 𝟏𝟏𝟏𝟏𝟏𝟏)𝟏𝟏𝟏𝟏 = (𝟕𝟕𝟕𝟕. 𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐𝟐 … . )𝟏𝟏𝟏𝟏
+ (𝑔𝑔 × 𝑛𝑛−3 )
Where: n = base
radix point (.) Binary and hexadecimal
 most important bases in digital electronics
 Conversion between any other bases can always be performed
via base-10. That is from base-n to base-10 and then from
DECIMAL to BASE n base-10 to base-n.
 (Con�nuous Division).(Con�nuous Mul�plica�on)
 Mnemonic song: What is 1001111100112 in hexadecimal?
Con�nuous Division from the botom to the top!

Example: 125.17510 → 𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 8 (𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜) OPERATIONS

 Convert into decimal, perform the opera�on, and then
𝟏𝟏𝟏𝟏𝟏𝟏 Convert back to the original base.

125 ÷ 8 𝟓𝟓 0.175 × 8 2
15 𝟏𝟏 COMPLEMENTS
8 5
15 ÷ 8 𝟕𝟕 2 1  A – B = A + (-B)
1 ×8 𝟑𝟑 where -B is the complement of B.
8 5 5
1 3 A – B = A + (complement of B)
1÷8 𝟏𝟏
×8 𝟏𝟏
8 5 5
complement of B = 𝑛𝑛𝑟𝑟 – B
3 4
×8 𝟒𝟒 where n = base
5 5 r = # of digits/bits
4 2 note: # digits of A = # digits of B
×8 𝟔𝟔
5 5
2 1 if 𝐴𝐴 ≥ 𝐵𝐵 then:
×8 𝟑𝟑
5 5 𝐴𝐴 + 𝐵𝐵 = 𝐴𝐴 + (𝑛𝑛𝑟𝑟 – B)
…. ……
if 𝐴𝐴 ≤ 𝐵𝐵 then:
𝐴𝐴 + 𝐵𝐵 = − 𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐𝑐 𝑜𝑜𝑜𝑜 [𝐴𝐴 + (𝑛𝑛𝑟𝑟 − 𝐵𝐵)]
𝟎𝟎. 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 ….

(𝟏𝟏𝟏𝟏𝟏𝟏. 𝟏𝟏𝟏𝟏𝟏𝟏)𝟏𝟏𝟏𝟏 = (𝟏𝟏𝟏𝟏𝟏𝟏. 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 … . )𝟖𝟖 2's complement

 replacing 1's with 0's and 0's with 1's and leaving the Least
Significant Bit unchanged.
 Nega�ve numbers
 Logic Circuits and Switching Theory
Signed Binary number Excess-3
Most significant Bit (MSB)  binary value plus 3
indicates the sign of the binary number.  used in some older computer.
0 = posi�ve  self-complemen�ng property. Excess-3 is an unweighted code
1 = nega�ve in which each coded combina�on is obtained from the
corresponding binary value plus 3.

OTHER BINARY CODING SYSTEMS

Binary Coded Decimal (BCD)
 BCD encodes each decimal digit with its binary equivalent using
four bits.

Ex. 91610 𝑡𝑡𝑡𝑡 𝐵𝐵𝐵𝐵𝐵𝐵?

9, 1 and 6 are 1001, 0001 and 0110 respec�vely, then
91610 = 100100010110𝐵𝐵𝐵𝐵𝐵𝐵 .

12 bits long since each of the decimal digits is coded by

four bits.

Gray code
 If binary numbers are used. A change. for example. from 0111
to 100 may produce an intermediate error number 1001 if the
value of the rightmost bit takes longer to change than do the
values of the other three bits. The Gray code eliminates this
problem. Since only one bit changes its value during any
transi�on between two numbers.
 Logic Circuits and Switching Theory
.ASCII Character Code. .BINARY LOGIC.
 7-bitcode (27 = 128 𝑐𝑐ℎ𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎)  consists of binary variables and a set of logical opera�ons.
 In prac�ce, usually stored in 8-bits (1 byte), with the most  variables are designated by leters of the alphabet. such as A, B,
significant bit (MSB) set to 0. This is done to make it easier to C, x, y, z. etc. with each variable having two and only two
store and transmit ASCII data, as most computers use 8-bit, dis�nct possible values: 1 and 0.
extra bit (10000000 =128 character) is some�mes used for
other purposes (Greek, italic, parity bit, etc.).
 128 ASCII characters: BOOLEAN ALGEBRA
26 UPPERCASE leters (A-Z)  May be defined with a set of elements and a set of operators.
26 lowercase leters (a-z)  A tool for the analysis and design of digital systems\
10 numerals (0 through 9)
32 special printable characters Boolean Func�ons
34 non-prin�ng characters (control character)
 described by an algebraic expression consist of binary variables,
the constants 0 and 1, and the logic opera�on symbols.
 func�on can be equal to either 1 or 0.
 Boolean func�on can be transformed from an algebraic
expression into a circuit diagram composed of logic gates
connected in a par�cular structure.

Algebraic Manipula�on
 each term requires a gate and each variable(literal) within the
term designates an input to the gate.

Duality Principle
 States that every algebraic expression deducible from the
postulates of Boolean algebra remains valid if the operators
and iden�ty elements are interchanged.
 0 and 1 are swapped and (+) and (×) are swapped.

Complement of a Func�on
 complement of a func�on F is not F (F').
 De morgan’s Law -> is derived from Duality Principle.

LAW AND form OR form

Iden�ty 1𝑥𝑥 = 𝑥𝑥 0 + 𝑥𝑥 = 𝑥𝑥

Null 0𝑥𝑥 = 0 1 + 𝑥𝑥 = 1

Idempotent 𝑥𝑥𝑥𝑥 = 𝑥𝑥 𝑥𝑥 + 𝑥𝑥 = 𝑥𝑥
Ex. A = 010000012 = 6510
Inverse 𝑥𝑥𝑥𝑥′ = 0 𝑥𝑥 + 𝑥𝑥′ = 1
Error-Detec�ng Code
Commuta�ve 𝑥𝑥𝑥𝑥 = 𝑦𝑦𝑦𝑦 𝑥𝑥 + 𝑦𝑦 = 𝑦𝑦 + 𝑥𝑥
Parity bit
 is an extra bit included with a message to make the total
Associa�ve (𝑥𝑥𝑥𝑥)𝑧𝑧 = 𝑥𝑥(𝑦𝑦𝑦𝑦) (𝒙𝒙 + 𝒚𝒚) + 𝒛𝒛 = 𝒙𝒙 + (𝒚𝒚 + 𝒛𝒛)
number of 1's either even or odd.

Absorp�on 𝑥𝑥(𝑥𝑥 + 𝑦𝑦) = 𝑥𝑥 𝑥𝑥 + 𝑥𝑥𝑥𝑥 = 𝑥𝑥

Distribu�ve 𝒙𝒙 + 𝒚𝒚𝒚𝒚 = (𝒙𝒙 + 𝒚𝒚)(𝒙𝒙 + 𝒛𝒛) 𝑥𝑥(𝑦𝑦 + 𝑧𝑧) = 𝑥𝑥𝑥𝑥 + 𝑥𝑥𝑥𝑥

 if the receiver detects a parity error. it sends back the ASCII De Morgan’s (𝑥𝑥𝑥𝑥)′ = 𝑥𝑥′ + 𝑦𝑦′ (𝑥𝑥 + 𝑦𝑦)′ = 𝑥𝑥′𝑦𝑦′
NAK (nega�ve acknowledge) consis�ng of an even-parity eight
bits 10010 101. If no error is detected. the receiver sends back
Involu�on (𝑥𝑥 ′ )′ = 𝑥𝑥
an ACK (acknowledge) 00000110. The sending end will respond
to NAK by transmi�ng the message again un�l the correct
parity is received.
 Logic Circuits and Switching Theory
Truth Table .Logic Circuits.
 A table of combina�ons of all possible values of the input
 A circuit that provides an input – output rela�onship
variables and its corresponding output. corresponding to a Boolean Algebra logic func�on to govern a
par�cular sequence of opera�ons in each system.
M = 2n
n = # 𝑜𝑜𝑜𝑜 𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖
M = # 𝑜𝑜𝑜𝑜 𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜𝑜

Types Of Boolean Func�on

1. Canonical form
2. Standard form

Logic Gates
 electronic circuit that operates on one or more input signals to
produce an output signal.

Minterms (SOP – F1)  Mi kaau ang SOP #1

𝐹𝐹𝑚𝑚𝑚𝑚𝑚𝑚 = �(𝐹𝐹1 ) @ 𝐹𝐹 = 1
𝐹𝐹𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑥𝑥 ′ 𝑦𝑦 ′ 𝑧𝑧 + 𝑥𝑥 ′ 𝑦𝑦𝑦𝑦 + 𝑥𝑥𝑥𝑥𝑧𝑧 ′ + 𝑥𝑥𝑥𝑥𝑥𝑥 → 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹
𝐹𝐹𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑚𝑚1 + 𝑚𝑚3 + 𝑚𝑚6 + 𝑚𝑚7
𝐹𝐹𝑚𝑚𝑚𝑚𝑚𝑚 = �(1,2,6,7) → 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹

Maxterms (POS – F0)

𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀 = �(𝐹𝐹0 ) @ 𝐹𝐹 = 0
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀 = (𝑥𝑥 + 𝑦𝑦 + 𝑧𝑧)(𝑥𝑥 + 𝑦𝑦 ′ + 𝑧𝑧)(𝑥𝑥 ′ + 𝑦𝑦 + 𝑧𝑧)(𝑥𝑥 ′ + 𝑦𝑦 + 𝑧𝑧 ′ )
→ 𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀 = 𝑀𝑀0 ∙ 𝑀𝑀2 ∙ 𝑀𝑀4 ∙ 𝑀𝑀5
𝐹𝐹𝑀𝑀𝑀𝑀𝑀𝑀 = �(0,2,4,5) → 𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶𝐶 𝐹𝐹𝐹𝐹𝐹𝐹𝐹𝐹 X or Y, but not both

(X or Y, but not both) ’ = xy, both

XY AND NAND OR NOR XOR XNOR

00 0 1 0 1 0 1
01 0 1 1 0 1 0
10 0 1 1 0 1 0
11 1 0 1 0 0 1
 Logic Circuits and Switching Theory
Universal Logic Gates NOR only Equivalent
AND/NOT Equivalent

OR/NOT Equivalent

Karnaugh map
 pictorial form of a truth table.
 straigh�orward procedure for minimizing Boolean func�ons.
 square represen�ng one minterm of the func�on.
 Gray code (1 bit at a �me)

NAND only Equivalent

 Logic Circuits and Switching Theory
.COMBINATIONAL LOGIC CIRCUITS. HALF-ADDER
 Input: 2 bits
 Output: 2 bits (S = sum, C = carry)

FULL ADDER
 Input: 3 bits
 Output: 2 bits (S = sum, C = carry)

ARITHMETIC CIRCUITS
 combina�onal logic circuits that perform the different binary
arithme�c opera�ons
 Logic Circuits and Switching Theory
BINARY PARALLEL ADDER Code Converters
 Produces the arithme�c sum of two binary numbers.  used to convert one type of binary code to another. There are
different types of binary codes like BCD code, gray code, excess-
3 code, etc. Different codes are used for different types of
digital applica�ons.

ENCODER
 Decimal input, Binary equivalent output

BCD adder
 4-bit binary adder that can add 4-bit numbers having a BCD
format.

DECODER
 Binary input, Decimal equivalent output

Binary-to-Gray

Gray-to-Binary
 Logic Circuits and Switching Theory
Mul�plexer (MUX) – shared w/ EST
 Data selector 4-to-1 Channel Mul�plexer
 switching circuits that just switch or route signals.
 select binary informa�on from one of many inputs
line and direct it to a single output line. The selec�on
of a par�cular input line is controlled by a set of
selec�on lines. normally, there are 2𝑛𝑛 input line and
n selec�on lines whose bit combina�on determine
which input is selected.
 Multiplexing is the generic term used to describe
the opera�on of sending one or more analogue or
digital signals over a common transmission line at
different �mes or speeds and as such, the device we
use to do just that is called the mul�plexer.

𝑏𝑏𝑏𝑏𝑏𝑏
𝑡𝑡𝑏𝑏𝑏𝑏𝑏𝑏 =
𝑓𝑓𝑏𝑏
𝑓𝑓𝑏𝑏(𝑡𝑡) = 𝑛𝑛𝑓𝑓𝑏𝑏 Digitally Adjustable Amplifier Gain (MUX)
1
𝑡𝑡𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 =
𝑓𝑓𝑏𝑏(𝑡𝑡)

𝑡𝑡𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 = � 𝑡𝑡𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠

2-input Mul�plexer Design

 Logic Circuits and Switching Theory
Demul�plexer (DeMUX) Digital Comparator
 Data distributor  compares the magnitude of two n-bit binary numbers.
 a circuit that receives informa�on
on a single line and transmits this
informa�on on one of 2𝑛𝑛 possible 1-bit Digital Comparator Circuit
output lines.
 takes one single input data line and
then switches it to any one of a number
of individual output lines one at a �me.
 Converts a serial data signal at the input to a parallel data
at its output lines.

1-to-4 Channel De-mul�plexer

4-bit Magnitude Comparator

Digitally Adjustable Amplifier Gain (DeMUX)

8-bit Word Comparator

 Logic Circuits and Switching Theory
.Sequen�al Logic Circuits.
Asynchronous Synchronous
Feature Sequen�al Logic Sequen�al Logic
Does not use a clock
signal to determine Uses a clock signal to
the �ming of its determine the �ming
Clock signal opera�ons. of its opera�ons.
State changes occur on
State changes occur in the rising or falling
State response to changes edge of the clock
changes in the inputs. signal.
Speed Faster Slower
Less sensi�vity to More sensi�vity to
 use flip-flops as memory elements and in which their output
Noise noise noise
depends on the present value of its input signals and on the
Timing
sequence of past inputs. This is in contrast to combina�onal flexibility More �ming flexible Less �ming flexible
logic, whose output is a func�on of only the present value of its Power
input signals. consump�on more power less power than
 two state or Bistable devices which can have their output or Complexity More complex Less complex
outputs set in one of two basic states, a logic level “1” or a logic
level “0” and will remain “latched” (hence the name latch)
indefinitely in this current state or condi�on un�l some other
input trigger pulse or signal is applied which will cause the
bistable to change its state once again.
 specified by a �me sequence of inputs, outputs, and internal
states. Asynchronous Sequen�al Logic (ASL)
 Operates without a central clock signal. State changes occur
immediately in response to input changes.

Two main types of ASL

Unclocked flip-flops:
 simple memory elements that can store one bit of data. They
are typically used to store the state of a circuit.

Classifica�on of Sequen�al Logic Time-delay elements:

 are devices that delay the passage of a signal by a specific
amount of �me.
 typically used to create delays in asynchronous sequen�al logic
circuits.

Event Driven – asynchronous

 circuits that change state immediately when
enabled (change in input).

Clock Driven – synchronous

 circuits that are synchronised to a specific clock signal.

Pulse Driven
 which is a combina�on of the two that responds to
triggering pulses.
 Logic Circuits and Switching Theory
Synchronous Sequen�al Logic RST flip-flop
 Does not use a clock signal to determine the �ming of its  An RS flip-flop with a third toggle that enables or disables the
opera�ons. R&S inputs.
 State changes occur in response to changes in the inputs.

FLIP-FLOPS
 also called a Bistable Multivibrator
 A circuit that has two stable states that can remain in either state
indefinitely.
 An external trigger can change the output.
D flip-flop
 can be used to store state informa�on.
 Output state follows the state of the D-input.

RS Flip-flop
 2-input memory element with designated R and S.
 Logic 1 on the S input will give Logic 1 at the output.
 Logic 1 at the R input, it will Reset.
 Logic 1 at R and S input will give undefined output.

JK flip-flop
 Most important flip-flop
 Gated SR flip-flop that prevents the illegal or invalid output
condi�on that occur when both inputs S and R are Logic 1.

Master-Slave flip-flop
 Combina�on of two JK flip-flops connected in a series
configura�on.
 Logic Circuits and Switching Theory
.BINARY STORAGE, REGISTERS and Register Transfer
 is a basic opera�on that consist of a transfer of binary
COUNTERS. informa�on from one set of registers into another set of
registers.

Binary cell
 A binary cell can be made using a flip-flop, but it is not
necessary to do so. A binary cell can also be made using other
types of logic gates, such as AND gates, OR gates, and NOT
gates.
 is a device that possesses two stable states and can store one
bit (0 or I) of informa�on.

Register
 register is a group of binary cells/flip-flops, each one of
which can store one bit of informa�on. An n-bit register
consists of a group of n cells/flip-flops can store n bit of
binary informa�on.
 is a temporary storage loca�on for data.
 It is used to hold data that is being processed by the
processor or that is wai�ng to be processed.
 much faster than main memory, so they can be used to
improve the performance of a computer system.

Type Description
General- A general-purpose register can be used to store any type
purpose of data. They are the most common type of register and
register are used for a variety of purposes.
An address register is used to store the address of a
Address memory location. They are used by the processor to
register access data from memory.
A control register is used to control the operation of the
processor. They are used to set the processor's mode of
Control operation, control the flow of execution, and manage
register interrupts.
A status register stores information about the state of
Status the processor. They are used to keep track of the
register processor's flags, such as the carry flag and the zero flag.
An index register is used to store an offset value that can
Index be added to the address of a memory location. This is
register used to access data in a memory array.
A stack pointer is used to store the address of the top of
Stack the stack. The stack is a data structure that is used to
pointer store temporary data.
Program The program counter is used to store the address of the
counter next instruction to be executed.
 Logic Circuits and Switching Theory
SHIFT REGISTERS COUNTER
 A shi� register basically consists of several single-bit D-type data  is essen�ally a register that goes through a predetermined
latches connected together in a serial type of daisy-chain sequence of binary state. The gate in the counter is connected in
arrangement so that the output from one data latch becomes such a way as to produce the prescribed sequence of state.
the input of the next latch and so on  typically used to count the number of clock pulses they receive.
 capable of shi�ing the binary informa�on held in each cell to its This can be used to measure �me, generate frequencies, or
neighboring cell, in a selected direc�on. count events.
 typically used to store data or to convert between serial and
parallel data formats.
Synchronous Counters
 counts the number of clock pulses it receives
 changes to the output occurs in “synchroniza�on” with the clock
signal.
 is a parallel counter because the clock input is connected in
parallel to each and every flip-flop

4 DIFFERENT MODES
Serial-in to Parallel-out (SIPO)
 the register is loaded with serial data, one bit at a �me, with the
stored data being available at the output in parallel form.

Asynchronous Counters
 also known as ripple counters
 triggered by changes in the input signal.

Serial-in to Serial-out (SISO)

 the data is shi�ed serially “IN” and “OUT” of the register, one bit
at a �me in either a le� or right direc�on under clock control.

Parallel-in to Serial-out (PISO)

 the parallel data is loaded into the register simultaneously and
shi�ed out serially one bit at a �me under clock control.

Synchronous Counters:
Parallel-in to Parallel-out (PIPO) 74LS160 - Programmable synchronous BCD counter with asynchronous reset
 the parallel data is loaded simultaneously into the register and 74LS161 - 4-Bit decade counter with asynchronous reset and synchronous load
74LS163 - 4-Bit binary counter with asynchronous reset and synchronous load
transferred together to their respec�ve outputs by the clock
74LS191 - 4-bit synchronous binary up/down counter with reset and load
pulse. 74LS192 - 4-Bit synchronous BCD counter with asynchronous reset and load
74LS193 - 4-Bit synchronous binary counter with asynchronous reset and load.

Asynchronous (Ripple) Counters:

74LS90 - Asynchronous ripple counter/divider
74LS390 - Dual decade ripple counter
74LS393 - Dual 4-stage binary ripple counter
74HC4040 - 12-Stage binary ripple counter
74HC4060 - 14-Stage binary ripple counter
 Logic Circuits and Switching Theory
.DIGITAL LOGIC FAMILIES. Opera�ng Speed:
 depends upon the �me that elapses between the applica�on of
Integrated Circuits (IC) a signal to an input terminal and the resul�ng change in logical
 AKA Solid State Circuit, chip state at the output terminals.
 A circuit of transistor, resistors, and capacitors
 specific device designed to perform specific func�ons. Fan-In
 The fan-in of a logic gate is defined as the number of inputs
1. Film (coming from similar circuits) that it can handle properly.
 passive components (RC) + external diode and transistors
2. Monolithic Fan-Out
 Ac�ve and passive in 1 chip
3. Hybrid  AKA loading factor
 More than one chips are interconnected.  defined as the maximum number of standard logic inputs that
an output can drive reliably.
 For example, a logic gate that is specified to have a fan-out of 8
Chip Density
can drive 8 standard logic inputs. if this number exceeds the
output logic-level voltages cannot be guaranteed.
# 𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇𝑇 𝐼𝐼𝑂𝑂𝑂𝑂 𝐼𝐼𝑂𝑂𝑂𝑂
𝜌𝜌𝑐𝑐ℎ𝑖𝑖𝑖𝑖 =  =
𝑐𝑐𝑐𝑐3 𝐼𝐼𝐼𝐼𝐼𝐼 𝐼𝐼𝐼𝐼𝐼𝐼

Scale Integra�on (# Trans) Propaga�on delay

 is the average transi�on delay �me for a signal to propagate
• SSI  < 10
from input to output.
• MSI  10-100  A measure of the rela�ve speed of the logic circuit
• LSI  100-1000
• VLSI  >1000 𝑡𝑡𝑃𝑃𝑃𝑃𝑃𝑃 + 𝑡𝑡𝑃𝑃𝑃𝑃𝑃𝑃
𝑡𝑡𝑃𝑃 =
• ULSI  >1M 2
where: 𝑡𝑡𝑃𝑃 = propaga�on delay
𝑡𝑡𝑃𝑃𝑃𝑃𝑃𝑃 = propaga�on delay high to low
Moore’s Law
𝑡𝑡𝑃𝑃𝑃𝑃𝑃𝑃 = propaga�on delay low to high
 “Number of transistors on a chip will double every one to two
years.”
𝟏𝟏
𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔𝒔 ∝
Linear IC  con�nuous range of values 𝒕𝒕𝒑𝒑
Digital IC  1’s and 0’s

Power Dissipa�on:
Type of IC:  the amount of power dissipated in an IC.
DTL  simplest logic family.
It uses diodes to isolate the
inputs from the transistor.
HTL  is a speed improvement over DTL.
It uses a higher threshold voltage for the transistors.
TTL  most common logic family.
It is a good compromise between speed and power
consump�on.
RTL  most power consuming.
ECL  is the fastest logic family,
it uses a nega�ve power supply voltage, which allows it to Noise Margin
switch even faster than TTL.  Maximum noise voltage added to the input signal of a digital
However, it is also the most power-consuming logic family. circuit that does not cause an undesirable change in the circuit
NMOS  low-power logic family that uses N-channel MOSFETs. output.
CMOS  lowest-power logic family.
It uses both N-channel and P-channel MOSFETs.
It is slower than NMOS, but it consumes even less power.

Bipolar CMOS (BiCMOS) Combina�on of BJT and CMOS

 Logic Circuits and Switching Theory
Noise Immunity:
 refers to the circuits’ ability to tolerate noise voltages on its
inputs.
 Higher the noise margin, beter the logic circuit.

Opera�ng Temperature Range:

 00Cto 700C for consumers
 -550C to +1250C for military applica�ons.

Figure of Merit
 product of speed and power.
 The speed is specified in terms of propaga�on delay �me
expressed in nano seconds.
Logic Family Transistor Speed Power
Type Consump�on
Flexibili�es Available DTL (Diode- BJT Low High
Transistor Logic)
1. Wire-logic Capability:
HTL (High BJT Medium Medium
 Connec�on of gate output terminals together or using
Threshold Logic)
them directly to perform addi�onal logic func�ons
without any extra hardware. TTL (Transistor- BJT Medium Low
Transistor Logic)
2. Availability of Complement Outputs: RTL (Resistor- BJT Low High
 This eliminates the need for addi�onal inverters. Transistor Logic)
ECL (Emiter- BJT High High
3. Breadth of Series: Coupled Logic)
 Types of different logic func�ons available in the series. NMOS (N- MOSFET Low Medium
channel MOS)
4. Popularity of Series: CMOS MOSFET Low Low
 The cost of manufacturing depends upon the number of
(Complementary-
ICs manufactured.
MOS
5. Input-Output Facili�es:
 For high fan-out, the gates have low output impedance for
both 0 and 1.
 Logic Circuits and Switching Theory
.Algorithmic State Machine (ASM). ASM charts
 sequen�al network is used to control a digital system which  represent physical hardware.
carries out a step by a step –by step procedure.  equivalent to a state graph
 A mathema�cal abstrac�on used to design algorithms.  can be described the opera�on of both combina�onal and
 It reads a set of inputs and changes to a different state based sequen�al circuits.
on those inputs.  equivalently expressed as a state and output table.
 Mealy and Moore Machine
Principal Component of an ASM Chart
1. State Box
Mealy Machine
 Changes its output based on its present state and current input.

Example: Det. The current state and output of a Mealy Machine

a�er an input sequence of 110100 is applied per clock cycle.

2. Decision box

Ans: 𝑆𝑆2 , 0 3. Condi�onal output box

Moore Machine
 Output depends only on the current state.
 It does not depend on the current input.