CSC TUTORIAL ANSWERS

1. Briefly explain the following: (i) latency (ii) throughput (iii). Instruction set

• Latency: The time delay between initiating a request and getting a response in a
system or network.
• Throughput: The rate at which data is successfully transmitted over a system or
network, usually measured in bits per second.
• Instruction Set: The basic set of operations or commands a processor
understands to perform tasks, bridging hardware and software.

2. Briefly discuss the effects of advancements in computer hardware technology on

computer software industry.
• Enhanced Capabilities: Faster processors, increased memory, and advanced graphics
have allowed software to handle more complex tasks and create richer user experiences.
• Parallel Processing: The shift to multi-core systems has pushed developers to design
software that can run tasks concurrently, optimizing performance.
• Innovation and Specialization: New hardware features have led to specialized
software (like AI applications running on GPUs), fostering niche markets and creative
solutions.
• Improved Efficiency: With more robust hardware, software can operate more
efficiently and effectively, paving the way for innovations in high-performance and
real-time computing.

3. Briefly the different types of interrupts in a microprocessor system?

• Maskable Interrupts: These interrupts can be enabled or disabled by the
processor and typically come from external devices (like keyboards or network
cards) to signal that they need attention.
• Non-Maskable Interrupts (NMIs): These are high-priority signals that cannot be
ignored or masked by the processor, and are reserved for critical events such as
hardware malfunctions.
• Software Interrupts: Triggered by specific instructions within a program,
software interrupts enable a program to request services from the operating
system, often
• used for system calls.
• Internal Interrupts (Exceptions): These occur as a direct result of errors or
special conditions during program execution (such as division by zero or invalid
memory access) and invoke corresponding error-handling routines.

4. Describe the three categories of computer architecture?

Computer architecture is categorized into three main types: system design
architecture, instruction set architecture (ISA), and microarchitecture.

System design architecture focuses on the overall structure and interaction of a

computer's components. It defines how the CPU, memory, and input/output devices
communicate with each other. Different models, such as the Von Neumann and Harvard
architectures, determine how data and instructions are stored and processed.

Instruction set architecture (ISA) serves as the interface between hardware and software.
It defines the set of instructions a processor can execute, how data is accessed, and how
operations like arithmetic and logic functions are performed. Different ISAs, such as x86,
ARM, and MIPS, influence a processor's capabilities and compatibility with software.

Microarchitecture deals with the internal design of a processor and how it implements
the ISA at the hardware level. It includes features like pipelines, execution units, and
cache memory that optimize processing speed and efficiency. While processors may
share the same ISA, their microarchitectures can differ significantly, as seen in Intel’s
Core i7 and AMD’s Ryzen processors.

5. What is the RAID system? Explain the different types of this technology.

RAID (Redundant Array of Independent Disks) is a storage technology that combines

multiple physical disk drives into a single logical unit to improve performance, enhance
data redundancy, or both. Here are the common RAID types:

• RAID 0 (Striping): Data is split across multiple disks to boost performance

through parallel access, but there’s no redundancy—if one disk fails, all data is
lost.
• RAID 1 (Mirroring): Data is duplicated on two or more disks, ensuring that an
identical copy exists on a separate disk. This provides high fault tolerance at the
cost of reduced effective storage capacity.
• RAID 5 (Striping with Distributed Parity): Data and parity information (used for
error recovery) are distributed across three or more disks. This configuration
strikes a balance between performance, effective storage capacity, and fault
tolerance by allowing recovery from a single disk failure.
• RAID 6 (Striping with Dual Parity): Similar to RAID 5, but with an additional parity
block, RAID 6 can withstand the simultaneous failure of two disks, offering
enhanced reliability especially in larger arrays.
• RAID 10 (1+0): This is a combination of mirroring and striping. Data is first mirrored,
then the mirrors are striped. RAID 10 provides both high performance and data
redundancy but requires a minimum of four disks and doubles the disk overhead.
 6. Briefly explain how the following has contributed to system execution or response time
and throughput: i. Cache Memory ii. Main Memory iii. Bus Address System
• Cache Memory: By storing frequently accessed data and instructions closer to
the processor, cache memory significantly reduces access latency. This
reduction in delay speeds up execution, improves response times, and overall
increases system throughput by minimizing the frequency of slower main memory
accesses.
• Main Memory: Main memory (RAM) serves as the working area for active
programs and data. Improvements in its speed and capacity allow a computer to
fetch and execute instructions more quickly, reducing wait times and enabling
more efficient multitasking. The direct link between main memory speed and
processor performance means that faster RAM directly translates to shorter
execution times and enhanced throughput.
• Bus Address System: The bus address system manages the communication
between the CPU, memory, and peripherals. A fast, efficient bus system with
well-organized addressing reduces data transfer delays, ensuring that the
processor spends less time waiting for data and more time executing instructions.
This efficient data routing helps maintain high throughput and responsive system
operation.

7. A common transformation required in graphics processors is square root.

Implementations of floating point (FP) square root vary significantly in performance,
especially among processors designed for graphics. Suppose FP square root (FPSQR)
is responsible for 20% of the execution time of a critical graphics benchmark. One
proposal is to enhance the FPSQR hardware and speed up this operation by a factor of
10. The other alternative is just to try to make all FP instructions in the graphics
processor run faster by a factor of 1.6; FP instructions are responsible for half of the
execution time for the application. The design team believes that they can make all FP
instructions run 1.6 times faster with the same effort as required for the fast square root.
Compare these two design alternatives

8. What is Computer Architecture? Briefly explain the following terms:

(i) Interrupts (ii) Instruction formats (iii) Multiplexers (iv) Decoders

Computer Architecture refers to the design and organization of a computer

system, including its hardware, instruction set, data flow, and control
mechanisms. It defines how components like the CPU, memory, and input/output
devices interact to execute programs efficiently.

I. Interrupts: Interrupts are signals that temporarily suspend the CPU's current
operations to address an event or condition that requires immediate attention.
 After servicing the interrupt through an appropriate routine, the CPU typically
resumes its previous task.
II. Instruction Formats: Instruction formats define the structure of the binary-
coded instructions that a CPU executes. They outline how an instruction is divided
into fields (such as the operation code, operand addresses, and control bits),
guiding the processor on the operation to perform and on which data.
III. Multiplexers: Multiplexers are digital devices that select one of several input
signals and forward the selected input to a single output line, based on control
(selection) signals. This functionality is essential for efficiently managing multiple
data sources within digital systems.
IV. Decoders: Decoders are combinational logic circuits that convert coded input
signals into a set of distinct output signals. For example, with an n-bit input, a
decoder typically activates one of 2ⁿ outputs, helping in tasks such as memory
addressing or selecting specific peripherals.

9. Consider the following quadratic equation: 2x 2 – 40x + 150 = 0. A trusted

mathematician tells us that the roots for this equation are 15 and 75. However, when
you try to solve it, the root turns out to be 15 and 5. Explain why 75 could be a solution
and while 5 is not

10. Difference between the two types of control units used to execute an instruction

Hardwired Control Unit

• Uses fixed electronic circuits (logic gates and flip-flops) to generate control
signals.
• Faster because it directly processes instructions without intermediate steps.
• Difficult to modify or update since changes require redesigning the hardware.
• Used in RISC (Reduced Instruction Set Computer) architectures due to their
simple instruction sets.

Microprogrammed Control Unit

• Uses a control memory that stores microinstructions to generate control signals.

• More flexible since modifying the microcode allows updates without hardware
changes.
• Slightly slower because it needs to fetch and decode microinstructions.
• Commonly used in CISC (Complex Instruction Set Computer) architectures
due to their complex instruction sets.

11. A processor has a five-stage pipeline. If a branch is taken, then four cycles are needed
to flush the pipeline. The branch penalty b is thus 4. The probability Pb that a particular
 instruction is a branch is 0.25. The probability Pt that the branch is taken is 0.5.
Compute the average number of cycles needed to execute an instruction, and the
execution efficiency.

12. . What are the disadvantages of increasing the number of stages in pipelined
processing?

Increasing the number of stages in pipelined processing can improve performance by

increasing instruction throughput, but it also introduces several disadvantages:

1. Increased Pipeline Hazards

a. More stages mean higher chances of data hazards (dependencies
between instructions), control hazards (branch mispredictions), and
structural hazards (resource conflicts).
b. Stalls and forwarding mechanisms become more complex.
2. Higher Branch Penalty
a. When a branch is taken, the deeper pipeline must flush more instructions,
leading to greater performance loss.
b. Branch prediction techniques must be more advanced to minimize
mispredictions.
3. Increased Complexity in Pipeline Control
a. More stages require additional control logic to handle instruction flow,
hazard resolution, and forwarding.
b. The complexity increases exponentially as more interdependencies
emerge between pipeline stages.
4. Diminishing Returns on Performance
a. As the number of pipeline stages increases, the clock cycle time gets
shorter, but the overhead from hazards and stalls reduces the actual
performance gain.
b. After a certain point, increasing stages no longer provides significant
speedup.
5. Higher Power Consumption and Heat Generation
a. More stages require more transistors and control logic, increasing power
consumption and heat dissipation.
b. This is a major concern in modern processors, especially in mobile and
embedded systems.
6. Increased Design and Manufacturing Cost
a. Deep pipelines require more complex hardware and testing, leading to
higher design and fabrication costs.
b. Debugging and optimizing a deeper pipeline is more difficult.
 13. . What are the basic differences among a branch instruction, a call subroutine and
program interrupt?
• Branch Instruction
o A branch instruction changes the normal sequence of program execution
by jumping to a different memory location based on a condition.
o It is typically used for loops, if-else conditions, and control flow changes.
o Example: BEQ (Branch if Equal), JMP (Jump), BNE (Branch if Not
Equal)
o Key Feature: No return mechanism; it just moves execution to a new
address.
• Call Subroutine
o A subroutine call temporarily transfers control to another part of the
program (function or procedure) and returns after execution.
o It saves the return address (usually in a stack) so execution can resume
after the subroutine is completed.
o Example: CALL (in x86), BL (Branch with Link in ARM)
o Key Feature: Allows modular programming and code reuse.
• Program Interrupt
o An interrupt is an event that forces the CPU to temporarily pause the
current program and execute an interrupt service routine (ISR).
o Can be triggered by hardware (I/O devices, timers, errors) or software
(system calls, exceptions).
o After handling the interrupt, the CPU resumes execution from where it was
interrupted.
o Example: Hardware interrupt (keyboard input, disk I/O), Software
interrupt (INT 21h in x86).
o Key Feature: Asynchronous; occurs independently of the program’s flow.

14. What is the major concept of RISC architecture? Discuss any five characteristics
of RISC and CISC processors.

15. . Explain the steps involved in an instruction cycle?

The instruction cycle consists of four main steps:

1. Fetch – The CPU retrieves the instruction from memory, using the Program
Counter (PC) to locate it.
2. Decode – The Control Unit (CU) interprets the instruction to determine the
required operation.
3. Execute – The CPU carries out the operation, whether it's an ALU calculation,
data transfer, or control instruction.
4. Store – If necessary, the result is stored in a register or memory for future use.
If an interrupt occurs, the CPU pauses execution to handle it before resuming normal
operations.

16. . What is Amdahl's law and why it is used?

Amdahl’s Law estimates the maximum speedup achievable by optimizing part of a

system. It shows that speedup is limited by the portion of a program that cannot be
parallelized.

S=1(1−P)+PNS = \frac{1}{(1 - P) + \frac{P}{N}}

Where P is the parallelizable portion, and N is the number of processors. It is used to

evaluate performance improvements and highlights diminishing returns when adding
more processors.

17. . Write shorts notes on the following addressing modes: Register mode, Immediate
addressing, Direct addressing mode, Indexed addressing mode, Relative addressing,
Register indirect mode, Autodecrement mode, Auto increment mode, Base register
addressing mode, Immediate mode, Indexed addressing, Displacement addressing,
Implied mode and Absolute addressing.

Short Notes on Addressing Modes

• Register Mode – The operand is stored in a CPU register, making it fast since no
memory access is needed.
• Immediate Addressing – The operand is directly provided in the instruction itself.
Example: MOV R1, #5 (stores 5 in R1).
• Direct Addressing Mode – The instruction contains the memory address where
the operand is located. Example: LOAD R1, 1000H loads data from memory
address 1000H into R1.
• Indexed Addressing Mode – The operand’s address is obtained by adding an
index register to a base address in the instruction. Useful in arrays and loops.
• Relative Addressing – The operand’s address is given as an offset relative to the
current program counter (PC). Used in branch instructions.
• Register Indirect Mode – The instruction specifies a register that holds the
memory address of the operand. Example: LOAD R1, (R2) loads data from the
address stored in R2 into R1.
• Autodecrement Mode – Before accessing the operand, the register holding the
address is decremented. Useful in stack operations.
• Auto-increment Mode – The register is accessed first, then incremented to point
to the next address. Used in looping operations.
• Base Register Addressing Mode – Similar to indexed mode, but uses a base
register instead of an index register, often for dynamic memory access.
• Immediate Mode – Same as Immediate Addressing, where the operand is part
of the instruction itself.
• Indexed Addressing – Same as Indexed Addressing Mode, where an index
register is used to modify the memory address.
• Displacement Addressing – The operand’s address is calculated using a base
address + displacement. This is a more general form of indexed addressing.
• Implied Mode – The operand is implicitly understood from the instruction.
Example: CLR (Clear Accumulator) doesn’t need an operand since it always works
on the accumulator.
• Absolute Addressing – The instruction provides the exact memory address of
the operand. Example: JMP 2000H transfers control to address 2000H.

18.