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2.3.2 Frequency response analysis
Using the pole–node association method, the frequency response of the amplifier can be analyzed.
VDD VDD VDD VDD
Vb4
M7 M8
Vb3
M5 M6
E
M10 M9
Vb2
M3 M4
Vop X A Von
CL Vip Vin CL
M1 M2
Vb1 Vcmfb Vb1
M11 M0 M12
Figure 11: Two-stage differential amplifier.
A pole is identified at node X (see Figure 11), whose location depends on the parasitic capacitances
seen from that node and the associated equivalent resistance. Since these parasitic capacitances are
typically much smaller than others in the circuit, such as the load capacitance CL , this pole usually
lies at relatively high frequencies.
gm3,4 gm3,4
ωpX ≈ ≈ (15)
CX CGS3,4 + CGD1,2
A pole is identified at node E (see Figure 11), arising primarily from the high output resistance of
the first stage, together with the contribution of various parasitic capacitances. Consequently, this
pole lies at frequencies lower than ωpX and ωpA and, in most designs, constitutes the dominant pole
of the system.
1 1
ωpE ≈ ≈ (16)
Rout1 CE Rout1 (CGS9,10 + CGD3,4 + CGD5,6 + CGD9,10 gm9,10 Rout2 )
Here, Rout1 and Rout2 denote the output resistances of the first and second stages, respectively. At
node A, due to the large load capacitance CL , a second significant pole arises. Since CL is often
substantial, this pole may reside at relatively low frequencies and, in some cases - if CL is sufficiently
large - may even become the dominant pole of the system.
1
ωpA ≈ (17)
Rout2 CL
This yields a diagram as shown in Figure 12. Although the relative positions of ωpE and ωpA de-
pend on the specific design, the impact on stability is the same: because multiple poles lie below
the unity-gain frequency, the phase margin is significantly reduced and may even become negative
(< 0°). This indicates that the amplifier is unstable and therefore unsuitable for operation within
a negative-feedback system.
To ensure system stability and achieve an adequate phase margin, Miller compensation is proposed.
This method is widely used, as it not only improves the phase margin but also enables a higher
bandwidth compared with other compensation techniques reported in the literature.
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|A(s)| [dB]
ωpX
ωpE ωpA ω [rad/s]
Figure 12: Uncompensated frequency response.
This method exploits the Miller effect to increase the effective capacitance at the input node of the
stage where the compensation capacitor is placed, by connecting Cc between the input and output
of the second stage (see Figure 13).
VDD
VDD
Rout1
Rout1 E
E M9
M9
Cc A Von
A Von
CL
CL
M12
M12
Figure 14: High-frequency Miller compensa-
Figure 13: Miller compensation. tion.
A Miller capacitance, CM , is produced and reflected at the input of that stage. The equivalent
capacitance seen from the input can be expressed as:
CM = (1 + Av2 )Cc ≈ gm9,10 Rout2 Cc (18)
The purpose of Miller compensation is to increase the effective capacitance at node E so that ωpE
becomes the dominant pole if ωpA was originally dominant or, if ωpE is already dominant, to shift
it to even lower frequencies. An additional effect also arises: as frequency increases, the impedance
of the compensation capacitor Cc decreases, causing the output of the second stage to see a lower
effective resistance than before compensation. Consequently, the pole associated with the output
shifts to higher frequencies, thereby improving the phase margin of the system.
Thus, with the addition of the capacitor Cc , the pole at node E shifts as follows:
1 1 1
ωpE ≈ → ≈ (19)
Rout1 CE Rout1 (CE + CM ) Rout1 CM
Based on the high-frequency equivalent circuit (see Figure 14), and assuming that the compensation
capacitor Cc behaves as a short circuit, the effect of this compensation on the output pole ωpA can
be analyzed. Under these conditions and within a small-signal framework, transistor M9,10 is diode-
connected and exhibits an equivalent output resistance of 1/gm9,10 .
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1 1 gm9,10
ωpA ≈ → ≈ (20)
Rout2 CL (Rout1 ||ro11,12 ||gm−1
9,10 )CL
CL
From the expressions obtained for ωpA and ωpE , before and after applying the compensation, it
follows that this technique shifts the pole wpA to higher frequencies, while the pole ωpE moves
to lower frequencies. Moreover, the pole ωpX is no longer of interest, as it lies at even higher
frequencies, as shown in Figure 15.
|A(s)| [dB]
ωpX
ωpE ωpA ω [rad/s]
ωpE ωpA
Figure 15: Frequency response after Miller compensation.
The rationale behind this compensation technique is to place the second (non-dominant) pole at a
frequency above the unity-gain frequency, thereby minimizing its phase contribution and ensuring
an adequate phase margin for system stability.
Upon examining Figure 13, the compensation capacitor Cc introduces an additional signal path
between the input and output of the second stage. This gives rise to a zero in the transfer func-
tion. Determining its location shows that this zero lies in the right-half plane (RHP), which can
compromise system stability. This zero is located at:
gm9,10 gm9,10
ωz = ≈ (21)
Cc + CGD9,10 Cc
The main drawback of a right-half-plane (RHP) zero is that it increases the gain magnitude, thereby
shifting the unity-gain bandwidth (UGBW) to higher values. At the same time, this zero introduces
additional phase lag—akin to that produced by a left-half-plane pole—which reduces the loop phase
margin and compromises system stability. This occurs because, to achieve the behavior shown in
Figure 15, the compensation capacitor Cc must be relatively large; its exact value depends on the
design.
The effect of the RHP zero can be mitigated by inserting a resistor Rc in series with the compensation
capacitor Cc , as shown in Figure 16.
Under this configuration, the zero is now located at:
gm9,10 1
ωz ≈ → (22)
Cc Cc (1/gm9,10 − Rc )
This configuration introduces a degree of freedom to control the zero: it can be shifted to higher
frequencies by using the resistor Rc as a nulling element, or even moved to the left-half plane (LHP),
which produces a phase lead. In many cases, the zero is tuned to cancel the second non-dominant
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VDD VDD VDD VDD VDD
Vb4
Rout1 M7 M8
E
M9
Vb3
M5 M6
Cc Rc
M10 M9
A Von
Vb2
CL Rc M3 M4
Cc Cc Rc
Vop Von
Vip Vin
M1 M2
M12
Vb1 Vcmfb Vb1
M11 M0 M12
Figure 16: Miller compensation with
nulling resistor. Figure 17: Two-stage differential amplifier.
pole, thereby improving the phase margin. The resulting topology is shown in Figure 17.
Consequently, the transfer function that describes the circuit’s frequency behavior is given by:
s
(1 + ωz )
A(s) = Ao · s s (23)
(1 + ωpE )(1 + ωpA )
Where Ao denotes the low-frequency small-signal gain, ωz is the zero identified in equation 22, and
ωpE and ωpA are the poles obtained in equation 19 and equation 20, respectively.
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