• Stage 2.2: Second part of intermediate stage, drives the output stage (VO3).
• Compensation Network: Two capacitive paths used:
• Inner Miller Cap (C<sub>C2</sub>): from Stage 2.2 output (VO2) back to Stage 1 output (VO1).
Ensures VO1 node is dominant pole 37 44 .
• Feed-Forward Cap (C<sub>C1</sub>) + Resistor (R<sub>f</sub>): from output node (VO3) back to
Stage 2.1 output (VO2) 45 . This introduces a zero (zc1) that cancels the output pole p3 41 46 .
R<sub>f</sub> is sized to place the zero optimally in LHP and avoid any RHP zero.
• Outcome: The cascade zero (at ω<sub>zc1</sub>) ≈ ω<sub>p3</sub> adds +90° phase lead,
negating the −90° lag of p3 42 47 . The amplifier’s open-loop transfer now effectively has 2 poles
(p1, p2) within the GBW, boosting phase margin to ~60°. Achieves high gain (~105 dB) without
oscillation 9 10 .
Speaker Notes:
This slide details how we actually implemented the cascade-zero compensation in the circuit. The key idea
was to modify the topology of the second stage to create the desired zero. Specifically, we split the
second stage into two sub-stages – you can think of it as Stage 2.1 and Stage 2.2 43 . In practice, this
means instead of one big amplifier in the middle, we have two smaller gain stages in series. By doing this,
we create an additional internal node (the interface between Stage 2.1 and Stage 2.2) that we can use for
compensation.
Our compensation network then uses two paths: 1. An “inner” Miller compensation capacitor C<sub>C2</
sub> between VO2 (the output of Stage 2.2, which is the node driving the output stage) and VO1 (output of
Stage 1) 37 . This capacitor serves to make the first pole (at VO1) dominant by effectively Miller-multiplying
the capacitance seen at VO1 44 . It’s similar to classical Miller compensation between stage2 and stage1 in
a two-stage op amp. 2. A feed-forward compensation branch consisting of a capacitor C<sub>C1</sub> in
series with a resistor R<sub>f</sub>, connected from the output node VO3 (after Stage 3) back to the node
between Stage 2.1 and 2.2 (which is VO2 in our notation) 45 . This is the crucial part that generates the
cascade zero. How does it work? C<sub>C1</sub> provides a high-frequency feed-forward path that
bypasses the high-gain Stage 2.2, effectively creating a transmission zero in the forward path. The resistor
R<sub>f</sub> is there to ensure that this zero is in the left-half-plane (for phase lead) rather than right-
half-plane. By tuning R<sub>f</sub> and C<sub>C1</sub>, we place the zero z<sub>c1</sub>
approximately at the same frequency as the output pole p3 41 . When properly aligned, the zero’s +90°
phase contribution cancels out the −90° from the p3 pole 46 . Essentially, p3 is “neutralized.”
With this scheme, the loop sees effectively only two poles (p1 and p2) significantly affecting phase within
the unity gain bandwidth. p1 is made dominant by C<sub>C2</sub>, p2 is the next pole (at VO2 or Stage 2
output), and p3’s effect is canceled by the zero. This yields a healthy phase margin ~60° as we saw in
simulation, meaning the amplifier is stable. We achieved our target of maintaining nearly the same unity-
gain frequency and phase margin as a typical two-stage design, even though we have an extra gain
stage 9 10 . And because we didn’t have to use an excessively large compensation capacitor or huge bias
currents to separate poles, the power and area overhead for compensation is modest. The actual values we
ended up using were on the order of a few picofarads for C<sub>C2</sub> and sub-pF for C<sub>C1</sub>,
and a few kilo-ohms for R<sub>f</sub>, found by iterative simulation (these ensure z<sub>c1</sub> lands
correctly and the phase bump happens where needed).
In summary, the cascade-zero approach allowed us to add that third stage to boost DC gain to ~105 dB
without paying the usual price of severe bandwidth reduction or instability. We essentially “trick” the
