roughly mid-supply (~0.6 V) so that it has maximum symmetrical swing in both directions 18 .
This
also ensures that the output stage transistors (which are driven by VO2) get enough drive voltage.
The intermediate stage provides around 20–25 dB gain 17 . Its bias current was set ~20 µA (slightly
higher than stage1’s) to be able to drive any compensation capacitors and the gates of the output
transistors without slewing issues 30 .
• Stage 3: Output Stage. The final stage is a class-AB output stage using complementary MOSFETs
(an NMOS pull-down and PMOS pull-up in push-pull) 19 . The design ensures both transistors
conduct a little in the quiescent state (a small bias through them) so that there’s no “dead zone”
crossover distortion 21 . We achieved this by generating proper bias gate voltages (often called bias
for class-AB) such that at rest both transistors are slightly on 22 . The output stage is sized large to
drive capacitive loads (like 30 pF) and to swing close to the rails. In simulation, it could drive the
output to within ~0.05 V of ground or VDD 23 , essentially rail-to-rail for practical purposes. Because
it’s class-AB, it can source or sink larger currents on demand (up to ~±100 µA into a 30 pF load in our
tests) even though the quiescent current is only a few microamps 31 . This improves the slew rate
for large output swings.
• Bias Network: All these stages are biased by a common biasing network that generates a stable
reference current (using a self-biased reference circuit) 25 . That reference current is mirrored to
provide the tail current for the input pair, bias currents for the active loads, and the bias for the
output transistors’ gates 26 . The bias network ensures each transistor is in saturation, even under
process, voltage, temperature variations 28 . We used cascode current mirrors where possible to
improve output resistance of current sources without losing much headroom 32 . The bias currents
were roughly partitioned as: ~10 µA in stage1 tail, ~20 µA in stage2, and the output stage devices
each get a few µA quiescent bias 27 . This distribution was tuned to balance gain and speed vs.
power consumption in each stage.
Overall, these three stages in cascade give the high open-loop gain we need (approximately the sum in dB:
25 + 25 + output stage gain ≈ 105 dB total). Next, we will discuss how we keep this three-stage amplifier
stable through compensation techniques.
Slide 5: Frequency Compensation in Three-Stage Op Amp
• Stability Challenge: A three-stage amplifier has three poles (p1, p2, p3) → risk of poor phase margin
or oscillation if not compensated 33 34 . Traditional Miller compensation for 3-stage can introduce
unwanted RHP zeros and often requires very large capacitors or additional buffers 10 35 .
• Nested Miller Compensation (NMC): Uses multiple Miller capacitors between stages to split poles.
Example: connect capacitors from output nodes of later stages back to earlier stages (forming
multiple feedback loops) 36 37 . NMC can stabilize a 3-stage, but may create a right-half-plane
(RHP) zero that hurts phase margin, typically counteracted by adding nulling resistors (at cost of
noise and area) 35 38 .
• Our Solution – Cascade-Zero Compensation: Instead of heavily slowing down the amplifier via pole
separation, we introduce a feed-forward zero to cancel the 3rd pole (output pole) 39 40 . Known as
a “cascade zero,” it effectively reduces the pole count seen by the loop to two, like a two-stage design
41 34 .
• Result: Phase margin is maintained (or improved) without requiring exorbitant capacitance or high
bias current. The three-stage design achieves phase margin ~60° with unity-gain bandwidth
