EXPERIMENT.
Aim : To design and verify operation of half adder and full adder.
Apparatus required : Power supply, IC’s, digital trainer kit, simulator, connecting leads.
Theory :
Half Adder
A Half Adder is a basic combinational logic circuit used for binary addition of two single-bit inputs.
Truth Table :
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Expressions
• Sum (S):
S=A⊕B(XOR gate)
• Carry (C):
C=A⋅B(AND gate)
Block Diagram
A Half Adder can be represented as:
• Inputs: A, B
• Output 1: Sum (A ⊕ B) → from XOR Gate
• Output 2: Carry (A · B) → from AND Gate
• Expression for Sum → A⊕B (XOR gate)
•Expression for Carry → A⋅B (AND gate)
Full Adder
1. Inputs and Outputs
• Inputs: A, B, Cin (carry-in)
• Outputs: Sum (S), Carry (Cout)
2. Truth Table :
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
3. Expressions
• Sum (S):
S=A⊕B⊕Cin(XOR of all three inputs)
• Carry (Cout):
Cout=AB+BCin+ACin
4. Explanation of Carry
From the K-map:
Grouped terms give:
Cout=AB+ACin+BCin
Which means carry is 1 when at least two inputs are 1.
5. Block Diagram
A Full Adder can be built from two Half Adders + one OR gate:
• First Half Adder → Inputs A, B → Outputs Sum1, Carry1
• Second Half Adder → Inputs Sum1, Cin → Outputs Final Sum, Carry2
• Final Carry (Cout) = Carry1 + Carry2 (using OR gate)
Sum = A ⊕ B ⊕ Cin
Cout = AB + BCin + ACin
Result : The half adder and full adder circuits are implemented and veri ed successfully on
simulator.
fi
Simulator output
