Introduction to VLSI ASIC Design
and Technology
Paulo Moreira
CERN - Geneva, Switzerland
Paulo Moreira Introduction 1
Outline
• Introduction – “Is there a limit?”
• Transistors – “CMOS building blocks”
• Parasitics I – “The [un]desirables”
• Parasitics II – “Building a full MOS model”
• The CMOS inverter – “A masterpiece”
• Technology scaling – “Smaller, Faster and Cooler”
• Technology – “Building an inverter”
• Gates I – “Just like LEGO”
• The pass gate – “An useful complement”
• Gates II – “A portfolio”
• Sequential circuits – “Time also counts!”
• DLLs and PLLs – “ A brief introduction”
• Storage elements – “A bit in memory”
Paulo Moreira Introduction 2
Introduction
1906
1906 1947
1947
Audion (Triode), 1906 First point contact transistor (germanium), 1947
Lee De Forest John Bardeen and Walter Brattain
Bell Laboratories
Paulo Moreira Introduction 3
Introduction
1958
1958 1997
1997
First integrated circuit (germanium), 1958
Jack S. Kilby, Texas Instruments
Intel Pentium II, 1997
Contained five components, three types: Clock: 233MHz
transistors resistors and capacitors Number of transistors: 7.5 M
Gate Length: 0.35
Paulo Moreira Introduction 4
“The world is digital…”
• Analogue looses terrain:
– Computing
– Instrumentation
– Control systems
– Telecommunications
– Consumer electronics
Paulo Moreira Introduction 5
“…analogue, alive and kicking”
• Amplification of very week signals
• A/D and D/A conversion
• RF communications
• Very high frequency amplification and signal
processing
• As digital systems become faster and
faster and circuit densities increase:
– “Analogue” phenomena are becoming
important in digital systems
Paulo Moreira Introduction 6
“Moore’s Law”
The number of transistors that can
be integrated on a single IC grows
exponentially with time.
“Integration complexity doubles
every three years”
Gordon Moore
Fairchild Corporation - 1965
Paulo Moreira Introduction 7
Trends in transistor count
42 M transistors
Number of transistors doubles every 2.3 years
(acceleration over the last 4 years: 1.5 years)
Increase: ~20K
2.25 K transistors
(From: http://www.intel.com)
Paulo Moreira Introduction 8
Trends in clock frequency
2 GHz
Intel Labs
Sub-ps switching transistor
µP clock > 20 GHz
Gate length: 20nm
Gate oxide: 3 atomic layers
In production: 2007 !
Paulo Moreira Introduction 9
Trends in feature size
Intel Labs
Sub-ps switching transistor
µP clock > 20 GHz
Gate length: 20nm 0.13 µm in
Gate oxide: 3 atomic layers production
In production: 2007 !
Paulo Moreira Introduction 10
Driving force: Economics (1)
• Traditionally, the cost/function in an IC is
reduced by 25% to 30% a year.
• To achieve this, the number of functions/IC
has to be increased. This demands for:
– Increase of the transistor count
– Decrease of the feature size (contains the
area increase and improves performance)
– Increase of the clock speed
Paulo Moreira Introduction 11
Driving force: Economics (2)
• Increase productivity:
– Increase equipment throughput
– Increase manufacturing yields
– Increase the number of chips on a wafer:
• reduce the area of the chip: smaller feature size &
redesign
– Use the largest wafer size available
Example
Exampleof ofaacost
costeffective
effectiveproduct
product(typically
(typically
DRAM):
DRAM):thetheinitial
initialIC
ICarea
areaisisreduced
reducedtoto50%
50%
after
after33years
yearsand
andto to35%
35%after
after66years.
years.
Paulo Moreira Introduction 12
2002 and beyond ?
Semiconductor Industry Association (SIA) Road Map, 1998 Update
1999 2002 2014
Technology (nm) 180 130 35
IEEE Spectrum, July
Minimum mask count 22/24 24 29/30 1999
Wafer diameter (mm) 300 300 450 Special report: “The
100-million transistor
Memory-samples (bits) 1G 4G 1T IC”
Transistors/cm2 (µP) 6.2M 18M 390M
Wiring levels (maximum) 6-7 7 10
Clock, local (MHz) 1250 2100 10000
Chip size: DRAM (mm2) 400 560 2240
Chip size: µP (mm2) 340 430 901
Power supply (V) 1.5-1.8 1.2-1.5 0.37-0.42
Maximum Power (W) 90 130 183
Number of pins (µP) 700 957 3350
These scaling trends will allow the electronics market to growth at 15% / year
Paulo Moreira Introduction 13
“Is there a limit?”
Siliconlattice
Silicon latticeconstant:
constant:5.42
5.42AA
Gateoxide:
Gate oxide:1.2
1.2nm
nm
≈≈33SiSiatomic
atomiclayers!
layers!
Paulo Moreira Introduction 14
“Is there a limit?”
Source:
Source:D.D.Frank
Franketetal.,
al.,
Proceedings
Proceedings of the IEEE,3/2001
of the IEEE, 3/2001
Paulo Moreira Introduction 15
“Is there a limit?”
• High volume factory:
– Total capacity: 40K Wafer Starts Per Month (WSPM) (180
nm)
– Total capital cost: $2.7B
• Production equipment: 80%
• Facilities: 15%
• Material handling systems: 3%
• Factory information & control: 2%
• Worldwide semiconductor market revenues in 2000:
~$180B
– Semiconductor market growth rate: ~15% / year
– Equipment market growth rate: ~19.4% / year
– By 2010 equipment spending will exceed 30% of the
semiconductor market revenues!
Paulo Moreira Introduction 16
How to cope with complexity?
• By applying:
– Rigid design Rigid Design
Methodologies
methodologies
– Design automation
Design Automation
(CAE Tools)
Successful
Design
Paulo Moreira Introduction 17
Design abstraction levels
High
System Specification
System
Level of Abstraction
Functional Module +
Gate
Circuit
Device S D
Low
Paulo Moreira Introduction 18
