DEPARTMENT OF ARTIFICIAL INTELLIGENCE AND DATA

SCIENCE

LAB MANUAL
CS3351 DIGITAL PRINCIPLE AND COMPUTER
ORGANIZATION LABORATORY

SEMESTER III /YEAR-II

(R-2021)
(ODD SEMESTER-2025-26)

Prepared by
Dr. S. CHANDRU
Assistant Professor,
Department of Electronics and Communication
Engineering,
Kingston Engineering College.
 LIST OF EXPERIMENTS

1. Study of logic gates.

2. Verification of Boolean Theorems using logic gates.
3. Design and implementation of combinational circuits using gates for arbitrary
functions.
4. Design and implementation of code converters using logic gates.
5. Design and implementation of 4-bit binary adder/ subtractor and BCD adderusing

IC 7483.
6. Design and implementation of encoder and decoder using logic gates andstudy of

IC 7445 and IC 74147.

7. Design and implementation of multiplexer and demultiplexer using logic

gates and study of IC 74150 and IC 74154.

8. Design and implementation of 3-bit synchronous up/down counter.
9. Implementation of universal shift register.
 INDEX

EXP. DATE NAME OF THE EXPERIMENT PAGE MARKS SIGNATURE

NO NO
 STUDY OF LOGIC GATES
EXPT NO. :
DATE :

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408
2. OR GATE IC 7432
3. NOT GATE IC 7404
4. NAND GATE 2 I/P IC 7400
5. NOR GATE IC 7402
6. X-OR GATE IC 7486
7. NAND GATE 3 I/P IC 7410
8. IC TRAINER KIT
9. PATCH CORD 14
THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.
OR GATE:

The OR gate performs a logical addition commonly known as OR function.

The output is high when any one of the inputs is high.The output is low level when both
the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs
are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X- OR GATE:

The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE :

Page No.
NOR GATE

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

The truth tables of all the basic logic gates were verified.
 VERIFICATION OF BOOLEAN THEOREMS USING
LOGIC GATES
EXPT NO. :
DATE :

Aim:
To verification of Boolean theorems using logic gates

Apparatus required:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 3
6. X-OR GATE IC 7486 1
7. IC TRAINER KIT - 1
8. PATCH CORD - 14

Theory:

Basic Boolean laws

1.Commutative law
The binary operator OR,AND is said to be commutative if,
1. A+B=B+a
2. A.B=B.A

2.Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)
4. Absorption Law
1. A+AB = A
2. A+AB =A+B
 5. Idempotent Law
1. A+A = A
2. A.A = A

6. Complementary Law
1. A+A' = 1
2. A.A' = 0

7. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B=A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
Design
1. Absorption Law

A+AB = A

2. Involution (or) Double complement Law

A=A

3. Idempotent Law

1. A+A = A

2. A.A = A
4.Demorgan’s Law:

A+B=A.B

5.Distributive Law:

A+(B.C)=(A+B).(A+C)

Procedure:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

Result:

Thus the above stated Boolean laws are verified.

 DESIGN OF ADDER AND SUBTRACTOR
EXPT NO. :
DATE :

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 23

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one
from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above
circuit is called as a carry signal from the addition of the less significant bits sum
from the X-OR Gate the carry out from the AND gate.
FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input;
it consists of three inputs and two outputs. A full adder is useful to add three bits at a
time
but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate,
carry output will be taken from OR Gate.
HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor
has two input and two outputs. The outputs are difference and borrow. The difference
can be applied using X-OR Gate, borrow output can be implemented using an AND
Gate and an inverter.
FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A
B. The output will be difference output of full subtractor. The expression AB assembles
the borrow output of the half subtractor and the second term is the inverted difference
output of first X-OR.

LOGIC DIAGRAM:

HALF ADDER
TRUTH TABLE:
A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:
A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC
LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference:

Difference = A’B’C + A’BC’ + AB’C’ + AB

K-Map for Borrow:

Borrow = A’B + BC + A’C

PROCEEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the design of the adder and subtractor circuits was done and their truth tables were
verified.
 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
EXPT NO. :
DATE:

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code
is a non-weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed.
 A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
K-Map for G3:

G3 = B3
K-Map for G2:

K-Map for G1:

K-Map for G0

TRUTH TABLE:
| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

.
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3:

B3 = G3
K-Map for B2:

K-Map for B1:

K-Map for B0

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E1:

K-Map for E0:

TRUTH TABLE:

` | BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1
K-Map for B:

K-Map for C:
K-Map for D:

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
 PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus, the code converters are designed and verified using the corresponding
truth table.

.
 DESIGN OF 4-BIT ADDER / SUBTRACTOR AND
BCD ADDER
EXPT.NO. :
DATE :

AIM:
To design and implement 4-bit adder / subtractor and BCD adder using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are
connected in chain through the full adder. The input carry to the adder is C 0 and it
ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry
C0 must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit
is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output
sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two
decimal digits must be represented in BCD and should appear in the form listed in the
columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4- BIT BINARY ADDER

LOGIC DIAGRAM:
4- BIT BINARY SUBTRACTOR
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

LOGIC DIAGRAM:
BCD ADDER
K MAP

Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM CARRY
S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
PROCEDURE:
(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:
Thus, the design of the 4-bit Binary adder / l subtractor and BCD adder circuit
was done and its truth table was verified.
 DESIGN AND IMPLEMENTATION OF ENCODER

AND DECODER
EXPT.NO. :
DATE :

AIM:
To design and implement encoder and decoder using logic gates and study of IC
7445 and IC 74147.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:

ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded
input into coded output where input and output codes are different. The input code
generally has fewer bits than the output code. Each input code word produces a different
output code word i.e there is one to one mapping can be expressed in truth table. In the
block diagram of decoder circuit the encoded information is present as n input
producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.

PIN DIAGRAM FOR IC 7445:

BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:

INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the design of encoder and decoder is verified using a logic diagram
and truth table.
 DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DEMULTIPLEXER
EXPT .NO. :
DATE :

AIM:
To design and implement multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be used
as demultiplexer.
 In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

.
CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER

FUNCTION TABLE:

S1 S0 INPUT
0 0 X → D0 = X S1’ S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

LOGIC DIAGRAM FOR DEMULTIPLEXER:
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

PIN DIAGRAM FOR IC 74150:

PIN DIAGRAM FOR IC 74154:

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the design of the 4x1 Multiplexer and 1x4 De multiplexer circuits
was done and their truth tables were verified.
 DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN
COUNTER

EXPT NO. :
DATE :

AIM:
To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. An up/down counter
is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter follows
reverse sequence.
K MAP

STATE DIAGRAM:
CHARACTERISTICS TABLE:
Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:
TRUTH TABLE:
Input Present State Next State A B C
Up/Down QA QB QC QA+1 Q B+1 QC+1 JA KA JB KB JC KC
0 0 0 0 1 1 1 1 X 1 X 1 X
0 1 1 1 1 1 0 X 0 X 0 X 1
0 1 1 0 1 0 1 X 0 X 1 1 X
0 1 0 1 1 0 0 X 0 0 X X 1
0 1 0 0 0 1 1 X 1 1 X 1 X
0 0 1 1 0 1 0 0 X X 0 X 1
0 0 1 0 0 0 1 0 X X 1 1 X
0 0 0 1 0 0 0 0 X 0 X X n1
1 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 0 0 X 1 X X 1
1 0 1 0 0 1 1 0 X X 0 1 X
1 0 1 1 1 0 0 1 X X 1 X 1
1 1 0 0 1 0 1 X 0 0 X 1 X
1 1 0 1 1 1 0 X 0 1 X X 1
1 1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 1 0 0 0 X 1 X 1 X 1

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the 3-bit synchronous up/down counters was implemented successfully.

 IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER

EXPT NO. :
DATE :

AIM:
To design and implement a universal shift register .
APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
 S0 and S1 are the selected pins that are used to select the mode of operation of this
register. It may be shift left operation or shift right operation or parallel mode.
 Pin-0 of first 4×1 Mux is fed to the output pin of the first flip-flop. Observe the
connections.
 Pin-1 of the first 4X1 MUX is connected to serial input for shift right. In this mode, the
register shifts the data towards the right.
 Similarly, pin-2 of 4X1 MUX is connected to the serial input for shift-left. In this mode,
the universal shift register shifts the data towards the left.
 M1 is the parallel input data given to the pin-3 of the first 4×1 MUX to provide parallel
mode operation and stores the data into the register
 Similarly, remaining individual parallel input data bits are given to the pin-3 of related
4X1MUX to provide parallel loading.
 F1, F2, F3, and F4 are the parallel outputs of Flip-flops, which are associated with the 4×1
MUX.
PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

Thus, the design of universal shift register was implemented successfully.