Test procedure file

The test procedure file is responsible for defining the stimuli required to shift data through
the scan chains in a design. This input becomes necessary particularly in designs that already
have pre-inserted scan circuitry or those that require specific test setup patterns. Essentially,
the test procedure file guides how data should be loaded, shifted, and captured during scan
operations, ensuring the test flow aligns with the scan architecture of the design.

From flow chart:

1. DFT Library: Provides reusable scan cells, mux structures.

2. Gate-Level Netlist: Your post-synthesis design without DFT.
3. Scan Insertion: Scan chains are inserted into the netlist.
4. Scan Inserted Netlist: Output of scan insertion, input to ATPG.
5. Test Procedure + Dofile/TCD: Used by ATPG to control how test vectors are generated
and applied.
6. ATPG Tool: Uses all of the above to generate test vectors that can detect stuck-at,
transition, path delay faults.
7. Test Patterns: Actual scan vectors that will be applied during silicon testing or
simulation.
8. Simulation Library: Used to simulate the effect of those test patterns.
9. Verification: Ensures the patterns work, faults are detected, and nothing is broken.
In scan-based design-for-testability (DFT), the test procedure file often supports different types of
patterns and simulations based on how the scan chains are organized and how test data is applied.
The two primary types of test patterns are serial patterns and parallel patterns. A serial pattern
shifts test data into the scan chains one bit at a time through a single scan input (scan_in) and
collects output through a single scan output (scan_out). This is simple but time-consuming,
especially for designs with long scan chains. On the other hand, parallel patterns use multiple scan
chains that are loaded and unloaded simultaneously, significantly speeding up the test process.

Correspondingly, there are two types of simulation modes to verify these patterns: serial simulation
and parallel simulation. Serial simulation mimics the actual scan shift process by simulating each
clock cycle individually, making it highly accurate but slower. In contrast, parallel simulation assumes
that the entire scan chain content is applied or captured in a single cycle, which greatly speeds up
simulation but is more abstract. The choice between these modes depends on the stage of design
verification and the level of accuracy required.

Scan-based testing involves three main procedures: Test_Setup, Load_Unload, and Capture. The
Test_Setup phase initializes the device by resetting it and preparing it for scan operations. This
includes setting control signals like System_Reset and programming the JTAG controller. The
ScanEnable signal is kept low to maintain functional mode, and ShiftClk is pulsed to stabilize the
design state before loading test data.

In the Load_Unload phase, scan data is shifted into the scan chains using the shift clock while
ScanEnable is high, enabling scan mode. Once the scan data is loaded, the Capture phase sets
ScanEnable low again, switches to functional mode, and pulses the clock to apply the test stimulus
and capture internal circuit responses. Finally, another Load_Unload cycle is used to shift out the

captured test results for analysis.

The test procedure file simply ASCII file format

The following is the various procedures example in the test procedure file

1.timeplate:
timeplate tpl =
force_pi 0 ; // Apply 0 to primary inputs
measure_po 10 ; // Measure primary outputs at 10 units
pulse Clk 20 10 ; // Generate clock pulse: rise at 20, fall at 30
period 50 ; // Each full cycle is 50 units
end;
 This defines a standard test timing template (tpl) used by other procedures.
 force_pi 0: Primary inputs are driven with 0 at the start of the cycle.
 measure_po 10: Output values are sampled 10 units after the start.
 pulse Clk 20 10: Clock goes high at 20 and low at 30.
 period 50: Total cycle length is 50 time units.
An ATE (Automatic Test Equipment) cycle is the fundamental timing unit used by the tester to
synchronize and apply stimuli to the Device Under Test (DUT) and to sample its outputs. Each ATE
cycle typically consists of a fixed period divided into precise timing windows for forcing inputs
(e.g., scan enable, clock, reset), measuring outputs, and generating pulses. Within one ATE
cycle, the tester uses programmable delays to align signal transitions with setup and hold
requirements of the DUT.

In a timeplate definition, the ATE cycle is modeled using commands like force, pulse, and
measure, which are mapped to specific moments (in picoseconds or nanoseconds) within the
ATE period. For instance, in the shift_tpl shown in the diagram, signals like bidi_en, clk, and reset
are forced or pulsed at defined offsets inside a 50-unit period. This period corresponds to one
ATE cycle. The ATE hardware uses these definitions to apply test vectors and sample results in
sync with the DUT's expected behavior, ensuring deterministic scan operations and accurate fault
detection.

Within an ATE environment, multiple timeplates can be defined to represent different

operational phases such as test setup, shift, capture, and reset. Each timeplate defines a unique
timing structure—including signal transitions, force points, pulse widths, and measurement
windows—while conforming to the maximum cycle time and resolution limits of the target ATE
hardware. The ATE imposes constraints on the number of timing edges, minimum pulse width,
and total period, so each timeplate must remain within these hardware limitations.

This flexibility allows test engineers to custom-tailor timing behavior per operation, ensuring
optimized signal delivery and accurate data sampling across scan chains. For example, a shift_tpl
may use narrow clock pulses for fast data shifting, while a capture_tpl might include setup/hold
margins for functional state evaluation. This modular timing approach enhances test coverage
while maintaining compatibility with ATE timing resources and constraints.

Note :

 A procedure file must contain atleast one time plate and all clocks must be defined in the
template
 A timeplate must and sholu have one force_pi and one force_po
 We no need to include pulse statement but
   With pulse in timeplate: You fully control the clock or signal toggle (timing,
width).
  Without pulse: The tool uses global/default scan clock definitions to
generate necessary transitions (usually for shift clocks, capture clocks, etc.).

2. procedure test setup

procedure test_setup =
timeplate tpl ; // Use the defined timeplate
cycle =
force ScanEn 0 ; // Set Scan Enable to 0 (functional mode)
pulse Clk ; // Pulse the clock
end ;
cycle =
pulse Clk ; // Another functional clock pulse
end ;
end ;
Explanation:
 This is the initialization phase.
 ScanEn is set to 0 to bring the design into functional (non-scan) mode.
 Two clock pulses are issued to stabilize the state elements before testing begins.

3.procedure load unload

procedure load_unload =
scan_group grp1 ;
timeplate shift_tplt ;
cycle =
force shift_clk 0 ;
 force in0 1 ;
force in1 1 ;
force reset 0 ;
force scan_en 1 ;
end;
apply shift 5 ;
end;

This procedure manages the loading and unloading of data into and out of the scan chains. It again
uses the same shift_tplt timeplate. Inside the cycle block, signals like shift_clk, in0, in1, reset, and
scan_en are all forced to their required values to initialize and enable the scan shifting process. The
command apply shift 5; indicates that the shift operation should be repeated for 5 cycles, which
aligns with the 5 shift clocks shown in the waveform. The scan inputs are applied and shifted in,
while the outputs are measured during unload.

4. procedure shift

procedure shift =
scan_group grp1 ;
timeplate shift_tplt ;
cycle =
force_sci ;
measure_sco ;
pulse shift_clk ;
end;
end;

This procedure is responsible for shifting scan data through the scan chains during scan testing. It
uses a scan group grp1 and a timeplate named shift_tplt. Within the cycle block:

 force_sci applies the scan input (SCI) values at the correct time.

 measure_sco samples the scan output (SCO) values after data has passed through the scan
elements.

 pulse shift_clk generates the clock pulse needed to shift the scan data through the chain.
This is repeated for each scan bit, as shown in the waveform on the right.

5.procedure capture

procedure capture =
timeplate tpl ;
cycle =
force ScanEn 0 ; // Set Scan Enable to 0 (functional mode)
force_pi ; // Apply primary input stimulus
measure_po ; // Measure outputs
pulse_capture_clock ;// Apply functional clock to capture logic value
end ;
end ;
Explanation:

 This is the capture phase after scan-in is complete.

 ScanEn = 0: sets circuit to normal mode.

 Functional inputs are applied, and after the clock pulse, the circuit's state is captured into
scan flip-flops.

 This is crucial to observe fault effects.

How to edit in test procedure file

Note :

If you want to customize the timing of when scan inputs are forced or when scan outputs
are measured, you need to explicitly define force_sci and/or measure_sco in your test
procedure file (procedure shift).
Incase u want change it then go to that test procedure file then edit accrding to u are
requirement
procedure shift =
scan_group grp1 ;
timeplate shift_tplt ;
cycle =
force_sci 5 ; // explicitly define custom timing (instead of default force_pi)
measure_sco 35 ; // explicitly define when to measure outputs (instead of default
measure_po)
pulse shift_clk ;
end;
end;

see In the above example I specified sci at time 5 and sco at time 35 other than pi and po timings