SCAN INTERVIEW QUESTIONS

Scan Insertion & ATPG Basics

1. What do we check before Scan Insertion? (DRC checks) – DFT golden rules, How do you avoid
combinational feedback loops in scan? How to use test points for it?
DRC ensures the scan chains are stitched correctly, clocks and resets are properly
handled, and the design is structurally testable. Running DRC before scan insertion is
important because it prevents scan shift failures, avoids capture issues, and helps
achieve higher fault coverage during ATPG.

Either we can use OR gate or mux. For any mux or or

gate one the signal is used either SE or TM. If we use
SE only during shift we can achieve required rules.

If we use TM during the hole testing process the we

can achieve the testing process.
Explain the scan insertion Flow, What are the inputs for Scan Insertion?
What are the outputs generated after Scan Insertion & ATPG?, What does
a Testproc (TPF) file contain
 1. Inputs Required for Scan Insertion Output files for scan
Before performing scan insertion in Tessent, you 1. Scan inserted netlist
need the following files/data: 2. TCD (tessent core description ): the TCD file contains
Gate-level Netlist
complete test architecture info — scan chains, test
clocks, resets, scan enables, test signals, and
o Synthesized Verilog netlist (post-synthesis design).
compression details — required for ATPG to generate
o Example: design.v valid test patterns.
DFT/Cell Library 3. Test procedures file :
o Library that defines scan cells, flop cells, etc. When to apply Scan Enable
o Example: dft.atpglib When to shift data
o Note: when ever our design contains pre-existing When to capture functional response
What clocking scheme to use
scan insertions in that time we use TCD and TPF
also input files. Test Setup → Initialize test mode (ScanEn=0).
Constraints File Load/Unload (Shift-In) → Shift patterns into scan chains
o Defines test-related setup (timing, clock, reset, scan (ScanEn=1).
enable). Capture → Apply functional clock to capture test response.
o Includes: Unload (Shift-Out) → Shift out captured response while
add_input_constraints (clocks, resets) loading next pattern.
add_clock (clock definitions)
Design Context Information
Note: the constraint SDC is used in the simulation
not in the scan insertion.
o Current design setup and hierarchy.
o Example commands:
set_context dft -scan
set_current_design
What are the files used in ATPG pattern generation (SDC, TPF, TCD, STIL, CTL
etc.)? hat is present in an SDC file? Do pin constraints also come under SDC?
SDC (Synopsys Design Constraints file)
 Purpose: Provides timing and test-related constraints to the ATPG tool.
 Contents:
o Clock definitions (frequency, latency, uncertainty).
o Input/output delay constraints.
o Multicycle and false paths.
o Test-specific constraints (like disabling certain paths or masking signals).
 Why needed: Ensures ATPG does not generate patterns that violate functional/timing constraints.
 yes ✅ SDC can include pin constraints.
 Example pin constraints:
o Input delay (set_input_delay)
o Output delay (set_output_delay)
o Drive strength (set_drive)
o Load capacitance (set_load)
o Clock definitions (create_clock)
So, SDC is not just for clocks/timing, but also for pin-level I/O constraint

2. TPF (Test Procedure File / Testproc file)

 Purpose: Describes test procedure for ATPG.
 Contents:
o Test modes (scan shift, capture, functional).
o Signal assignments (like scan enable, test mode pins).
o Information on scan chains, clocks, resets.
  Why needed: Guides ATPG on how to apply patterns in silicon.

3 TCD (tessent core description ): the TCD file contains complete test architecture info — scan chains, test
clocks, resets, scan enables, test signals, and compression details — required for ATPG to generate valid test
patterns.

4. STIL (Standard Test Interface Language)

 Purpose: Industry-standard format for storing ATPG patterns.
 Contents:
o Test vectors (scan-in, capture, scan-out sequences).
o Timing information (clocks, waveforms).
o Expected responses for each pattern.
 Why needed: STIL files are portable across different ATPG tools, simulators, and testers.

CTL (Core Test Language)

 Purpose: A standard language (IEEE 1450.6) used to describe core-level test information in a SoC.
 Contents:
o Core test interface details (scan chains, I/Os, clocks, resets).
o Test procedures at the core level.
o Wrapper details if IEEE 1500 is used.
o Mapping of ATPG patterns for hierarchical DFT.
 Why needed:
o Makes ATPG/test patterns portable across SoC integration.
o Ensures consistency between IP provider and SoC integrator.
o Helps in hierarchical DFT (core-based testing).
In Summary
 SDC → Timing/test constraints.
 TPF → Test procedure (modes, signals, scan info).
 TCD → Test constraint data (scan chain/clock control).
 STIL → ATPG patterns in standard portable format.
 CTL (Core Test Language) → Core-level DFT/test description for hierarchical test integration.
 What is Scan? Why is it used,What are Scan operations? (Shift-in, Capture, Shift-out) How do you
calculate test time for Scan, How do you find the scan chain length and required shift cycles?

Scan is a structured DFT (Design for Test)

methodology used to improve the testability
of sequential circuits. In scan design, the
storage elements (flip-flops/latches) are
converted into scan cells and linked together
to form scan chains. These chains allow us to
directly control (controllability) and observe
(observability) the internal states of the
circuit during test.

Why do we need Scan?

In sequential circuits, the main challenge is

that flip-flops are not directly controllable or
observable from primary inputs/outputs.

Without scan, test generation is ad-hoc

(manual, inefficient, and unpredictable),
requiring long input sequences and making
ATPG very difficult.

Scan provides a systematic (structured)

approach where:

In shift mode, we can load desired test

patterns into flip-flops.

In capture mode, we clock the circuit once to

Scan chain length which is nothing but the number scan cells presented in the capture fault effects.
scan chain the number shift cycle required for scan chain is same as number scan
In shift-out, we extract responses for
cells presented in the scan chain
comparison.
Note: because of the combinational logic present in between the scan cells some
This drastically reduces ATPG complexity,
time the data transferring of scan cells take two shift cycles which is nothing but improves fault coverage (stuck-at, transition,
the multipath path cycle, so make sure in from the sdc file whether the multipath path delay faults), and enables predictable
cycle presented in the design or not and automated testing compared to earlier
ad-hoc methods.

Test time = (No. of shift cycles + capture cycle) In sequential circuits, flip-flops are not directly controllable or
* No.of patterns * clk period observable, making sequential ATPG very difficult and ad-hoc, since
No. of shiftcycles depends no of scan cells efficient algorithms were lacking. In contrast, combinational ATPG is
easier with established methods like D-algorithm. Scan converts the
presented in the design
sequential test problem into a combinational one by allowing direct
Capture cycle loading of flip-flops in shift mode, capturing faults in capture mode,
• for stuck at one capture cycle for a pattern and unloading responses in shift-out mode. This enables the use of
• for transition either two or three capture existing combinational ATPG algorithms, reduces complexity, and
cycle because the testing takes at Atspeed improves fault coverage.
testing.
 What is Sequential Depth?
The sequential depth of a circuit is the maximum
number of clock cycles required to control and observe
values through storage elements. In ATPG, even in a
full-scan design where almost all flip-flops are scan cells
(typically >99.9% in practice), the sequential depth is
never 0 but at least 1, since a functional capture cycle is
always required to detect faults. In contrast, purely
combinational logic can have a sequential depth of 0.
When partial scan is used and some flip-flops are left as
non-scan, the sequential depth increases beyond 1, as
multiple functional cycles are needed to propagate
values through these non-scan elements before they If all FFs were scan FFs (SFFs) →
can be observed. This increase in sequential depth Sequential depth = 1 (only capture cycle needed).
complicates ATPG, lengthens pattern sequences, and ATPG is simple, using combinational algorithms.
reduces achievable fault coverage because certain faults
But here, we have grey FFs (non-scan) →
may become untestable within practical cycle limits.
This is exactly why scan design is so powerful — it Suppose ATPG wants a value in the grey FF (CK1 domain).
reduces sequential ATPG to a near-combinational The tool must forward values through SFFs + apply
ATPG problem, allowing existing efficient algorithms multiple functional CK1 cycles before it’s set/observed.
(like D-algorithm, PODEM, etc.) to be applied directly. Sequential depth > 1, which increases ATPG complexity
and reduces coverage.

Difference between DFT vectors and Functional vectors (structural vs

functional vectors)?
Functional test vectors are created by RTL designers or verification engineers with the aim of
ensuring that a design performs its intended functionality. These vectors are derived directly from
the design specifications or the RTL code. They are either written manually or generated
automatically using simulation testbenches. For example, in the case of an ALU design, applying
inputs such as A=3, B=5, and OP=ADD should result in the correct output of 8. While functional
vectors are useful in validating logical correctness, they have certain drawbacks. They cannot
guarantee the detection of all possible silicon faults, such as stuck-at faults within gates, and tend to
be lengthy and incomplete when it comes to achieving high defect coverage.

In contrast, structural test vectors are generated after the implementation of Design-for-Test (DFT)
techniques, using Automatic Test Pattern Generation (ATPG) tools like Tessent or TetraMax. The
primary goal of these vectors is to detect structural faults—such as stuck-at faults, transition faults,
path-delay faults, and bridging faults—at the gate level. They are produced automatically from the
gate-level netlist in combination with fault models, without requiring manual input from designers.
For example, if an ATPG tool models a fault like a net X stuck-at-0, it will generate an input pattern
(e.g., 1010…) to activate the fault and compare the expected output with the observed output. If the
design is faulty, the result will deviate from the expected value. Unlike functional tests, structural
vectors are shorter, more targeted, and capable of achieving high fault coverage in silicon.
Fault Models & Coverage:What are Fault Classes, What are redundant and undetectable faults in
ATPG? Where do they occur, What are detectable faults in Scan?
 What is Fault Collapsing?

What are pseudo-random patterns?

Pseudo-random test patterns are random-like sequences of 0s and

1s generated by an LFSR, used in ATPG and BIST to test digital
circuits. They give fast, cheap, and wide fault coverage, but cannot guarantee coverage of all faults.
To handle the remaining faults, designers use test points, deterministic ATPG, or hybrid testing.
How do you improve fault coverage?
Fault coverage can be improved through several methods. The most important is adding proper DFT
logic such as scan chains, on-chip clock controllers, memory BIST, and boundary scan, which enhance
controllability and observability of internal nodes. For hard-to-test areas, test point insertion is used
by adding control or observe points to make random-pattern-resistant faults detectable. Coverage
also increases when ATPG constraints are set correctly and when X-bounding or masking is applied
to handle unknown values from analog blocks or uninitialized flops. Using advanced fault models like
transition, path-delay, bridging, and cell-aware ATPG helps capture defects beyond simple stuck-at
faults. Additionally, removing redundant logic, increasing pattern count, and performing at-speed
testing further boost coverage and ensure better defect detection in silicon.

Which fault model gives higher coverage – Stuck-at or Transition? Are false paths and multicycle
paths tested during transition fault testing?

 Stuck-at model gives higher coverage (more than 95%) since it is independent of functional
frequency and ignores timing-related untestable paths.

 Transition fault model provides realistic delay testing, but coverage is reduced(80-90)
because not all paths (false path /multicycle path/clock/reset) can be validated under at-
speed capture.

Explain faults vs defects vs errors.

 Defect → physical imperfection in chip.

 Fault → logical model of defect (what ATPG works with).

 Error → wrong output observed due to fault effect propagation.

Defect causes a Fault; Fault (if activated + propagated) causes an Error

What are manufacturing defects

Manufacturing defects are physical imperfections or unintended variations introduced during the
semiconductor fabrication process. These occur due to limitations in photolithography, process
variations, contamination, or material defects. Such defects may alter the intended behavior of the
circuit and can cause faults during operation.
Shorts (Bridging Defects):
 Two wires or transistors that should be isolated end up connected.
 Example: Metal-to-metal short.

Opens (Breaks):
 A conducting path is unintentionally broken.
 Example: Open via, broken interconnect.

Stuck-at Defects:
 A line is permanently stuck at logic ‘0’ or ‘1’ due to defect.
 Delay/Resistive Defects:
 o A partial open/short that slows down a signal path, causing timing failures.

 Bridging with Crosstalk:

o Two signals interfere due to unwanted coupling.
 Process Variation Defects:
o Non-uniform doping, lithography misalignment, or variations in transistor sizes.

How increase the fault coverage

1. Ways to Improve Fault Coverage

When ATPG reports low fault coverage, you can improve it by:
 Increase controllability → Make it easier to set internal nodes to 0 or 1.
 Increase observability → Make it easier to propagate internal node values to scan outputs.
 Add more patterns → Sometimes random/pseudo-random patterns are not enough;
deterministic ATPG patterns are needed.
 Improve scan architecture → Adding more scan chains, better scan enable/reset handling, or
breaking long chains can help.
 Clock/test mode handling → Ensure clocks, resets, and enables are properly controlled in
test mode.

 Fix constraints and X-problems.

 Use advanced fault models.-IDDQ, cell awareness etc.
 Remove redundant logic.
 DFT techniques to enhance the fault coverage: If the fault coverageisnotsufficient,thenthree
approaches can be used to enhance the fault coverage: (1) test point insertion, 2) mixed-mode
BIST, and (3) hybrid BIST. The first two approaches are applicable for in-field coverage
enhancement, and the third approach is applicable for manufacturing coverage enhancement.
Why fault coverage enhancement is needed?
 In DFT (Design for Test), scan testing + ATPG already provides high coverage for stuck-at and
transition faults.
 But sometimes coverage is not sufficient because:
o Some nodes are hard-to-control (can’t easily set to 0/1).
o Some nodes are hard-to-observe (their effect doesn’t propagate to scan outputs).
o Pseudo-random BIST patterns may miss hard-to-detect faults.
 To handle this, extra DFT techniques are added to push fault coverage closer to 100%.

✅ 1. Test Point Insertion (TPI)

 Idea: Add extra logic (muxes, control signals, or observation points) in the design to make it
easier to detect faults.
 Two types of test points:
1. Control Points – force signals to 0/1 to increase controllability.
2. Observation Points – directly connect internal signals to scan chain/outputs to
increase observability.
🔸 Use case:
 Helps when ATPG cannot generate patterns for some faults.
 Used in both scan-based ATPG testing and BIST testing.
🔸 Coverage impact:
  Eliminates random-resistant faults (hard-to-control/observe).
 Improves both manufacturing test coverage and in-field coverage (especially if BIST is used
in the field).

✅ 2. Mixed-Mode BIST
 Idea: Combine pseudo-random patterns (from an LFSR) with a small number of
deterministic patterns (stored on-chip).
 Problem with plain BIST: Pure pseudo-random patterns can’t detect all faults (coverage may
plateau at 90–95%).
 Solution in Mixed-Mode BIST:
o First, run many random patterns (good for easy faults).
o Then, apply a few stored deterministic patterns (good for hard faults).
🔸 Use case:
 Primarily used for in-field testing (self-test after deployment, e.g., automotive chips).
 Ensures high coverage without needing an external tester.
🔸 Coverage impact:
 Pushes coverage from 90–95% → closer to 99%.
 Keeps on-chip hardware area low since only a small deterministic set is stored.

✅ 3. Hybrid BIST
 Idea: Combine external tester patterns (ATE/scan-ATPG) with on-chip BIST patterns.
 Unlike mixed-mode, which is fully self-contained, hybrid BIST uses both external and internal
test sources.
🔸 How it works:
 BIST generates a bulk of random patterns (fast, low-cost).
 External tester applies targeted deterministic ATPG patterns for the faults missed by BIST.
🔸 Use case:
 Mainly for manufacturing test coverage enhancement.
 Reduces tester memory and test time (since many random patterns are applied on-chip, not
loaded from ATE).
🔸 Coverage impact:
 Improves manufacturing yield testing efficiency.
 Keeps high fault coverage while reducing tester dependency and cost.

What is a Lock-up Latch? Where is it used?Why is capture signal not fed to lockup latch?How do
we remove glitches using latches? (with waveform)
he lockup latch is only for timing alignment during shift, it does not participate in capture, so
capture is not fed back to it.

Explain Muxed Flip-Flop (scan FF).

A muxed scan flip-flop is a modified version of a

normal flip-flop that helps increase fault coverage
during testing. Unlike a regular D flip-flop, which
only has a functional data input (D) and clock
(CLK), the muxed scan flip-flop includes an
additional 2:1 multiplexer at its input. This
multiplexer selects between the functional data
(D) and a scan input (SI), controlled by a scan
enable signal (SE). When SE is low, the flip-flop
behaves like a normal storage element and
captures functional data. When SE is high, the
flip-flop operates in scan mode, allowing data to
This modification provides two major benefits. First, it be shifted in serially through SI and shifted out
improves controllability, since ATPG can directly load through its output (SO).
desired values into the flip-flops through the scan chain.
Second, it improves observability, since the contents of
flip-flops can be shifted out and observed through the scan output. By making internal states both
controllable and observable, the muxed scan flip-flop overcomes sequential depth limitations and
allows ATPG to generate effective test patterns, thereby achieving much higher fault coverage—
typically above 95% for stuck-at faults and significantly better coverage for transition faults as well.

Explain clock grouping and independent clocks in scan.

 Clock grouping is a process used to identify all
independent or noninteracting clocks that can be grouped
and applied simultaneously. An example of the clock
grouping process is shown in Figure. This example shows
the results of performing a circuit analysis operation on a
testable design in order to identify all clock interactions,
marked with an arrow, where a data transfer from one
clock domain to a different clock domain occurs. As seen

domains (CD1 ∼ CD7) and five crossing-clock-domain data

in Figure the circuit in this example has seven clock

paths (CCD1 ∼CCD5). From this example, it can be seen

that CD2 and CD3 are independent from each other;
Clock Gating hence, their related clocks can be applied simultaneously
during test as CK2. Similarly, clock domains CD4 through
CD7 can also be applied simultaneously during test as CK3.
In in
Therefore digital designs, clock
this example, threegating is widely
grouped clocksused to save
instead of
power by clocks
seven individual disabling
canthebeclock when
used a block
to test theis circuit
idle.
Thecapture
during the simplest method uses an AND gate with an
operation.
enable signal and the clock, as shown. However, this
approach introduces a serious drawback: glitches. If
the enable signal changes while the clock is high, a
spurious pulse may appear at the output (circled in
the waveform). Such glitches can cause unwanted
flip-flop triggering, leading to functional failures.

To avoid this, designers use Integrated Clock Gating (ICG) cells, which include a latch-based
mechanism to synchronize the enable signal with the clock. ICG cells ensure glitch-free clock
gating, making them the industry-standard solution in low-power designs.

ICG (integrated clock gating)

In an Integrated Clock Gating (ICG) cell, a latch is placed on the enable signal so that it is sampled
only when the clock is low (inactive phase). This ensures that any change on the enable line does not
immediately affect the clock path. As a result, the gated clock only toggles in sync with safe clock
edges, thereby eliminating glitches that would otherwise occur if enable changed while the clock was
high.

CLOCK LATENCEY
How many fault sites possible for a 2-input AND gate?

A 2-input AND gate has a potential of 6

single stuck-at fault sites: two stuck-at-0 and
two stuck-at-1 faults at each of the two
inputs, plus one stuck-at-0 and one stuck-at-
1 at the output. However, through fault
collapsing, the number of unique single
faults to consider is typically reduced to 4:
one stuck-at-0 at each input, and one stuck-
at-0 and one stuck-at-1 at the output
IDDQ fault
Stitch 3 flip-flops in a scan chain and show how to send pattern 101 using scan operation.

In the shift-in phase (SE=1), the scan chain loads the

serial input bits (1,0,1) into the flip-flops over three
clock cycles. Once the pattern is loaded, the circuit
enters the capture phase (SE=0), where a functional
clock is applied so the combinational logic response
is captured into the scan flip-flops. After capture, the
circuit switches back to shift-out phase (SE=1), and
the stored responses are shifted out serially through
SO for comparison with the expected values.

. This systematic shift–capture–shift sequence makes the internal states controllable and observable,
enabling easy ATPG and high fault coverage.

How are patterns applied and validated (ATE, TDO vs expected)?

Pattern Application (ATE side):

The ATE (Automatic Test Equipment) shifts in ATPG-

generated test patterns through TDI while controlling
clocks and scan enables.

The DUT (chip) captures responses internally.

Response Capture:

The captured scan chain values are shifted out via TDO.

Validation / Comparison:

The ATE compares the actual TDO response with the

expected (golden) response generated by ATPG.

If they match → Pass, if not → Fail (fault detected).

Gate count and flip-flop count → how to get using tool command?
# Report statistics  report_statistics → gives gate count (total logic cells, combinational +
report_scan_chain sequential).
 report_design_info or report_scan_chain → gives flip-flop count (scannable,
report_design_info non-scannable, lockup latches).
📌 In Tessent manuals, after create_test_design, the report_statistics command is the
report_statistics
standard to check gate count, flop count, latch count, etc.

What are the operations of OCC (On-Chip Clock Controller)?

Clock Selection / Multiplexing

 The OCC chooses between the functional clock (system clock) and the scan clock (from
tester).
 In shift mode, it selects the slow scan clock from the ATE.
 In capture mode, it selects the at-speed functional clock(s).
 This ensures proper operation in both test and functional modes.
2. Clock Chopping / Gating
 OCC generates only the required number of clock pulses during capture (usually 1 or 2
pulses).
 For stuck-at faults, a single capture pulse is generated.
 For transition faults, two closely spaced capture pulses are generated at the functional
frequency.
 Clock chopping (gating) makes sure only the intended edges go to the scan flops, avoiding
unintended captures.
3. Clock Generation / Pulse Control (At-Speed Testing)
 OCC can generate at-speed capture pulses internally, even if the tester cannot provide such
high-frequency clocks.
 This is important for transition fault and path delay fault testing.
 OCC ensures that capture happens at the design’s
real operating frequency.
Why do we measure primary outputs before capture clock?
Primary outputs are normally the result of combinational logic that takes its inputs from flip-flop
outputs (scan or functional). When you apply a test, the current values in the flops drive that
combinational network and produce the PO values. If you then apply a capture pulse, the flops will
update (be overwritten) with the newly captured results and the combinational outputs will change
accordingly.
So we measure (or sample) the primary outputs before the next capture so we observe the
combinational response produced by the current flop state — otherwise the upcoming capture will
overwrite the flop states and the PO values you wanted to check will be lost or corrupted.

Wave from for stuck at

What are the common violations faced during Scan Insertion and how do you
fix them?

What is LOS (Launch-off-Shift)?

What is LOC (Launch-off-Capture)? Difference between LOC and LOS.

Which has higher fault coverage in industry – LOC or LOS, and why?

What are the disadvantages of LOS?

How do we overcome LOS cons? (Global SE, LOES techniques)

How are the two pulses generated in transition testing (for LOC/LOS)?