DFT-5 Batch Interview Questions

1. What is scan insertion?

In the scan insertion we add extra circuitry to providing controllability and observability.

Scan insertion is nothing but control the inputs of gates and observe the output of the pins .

2. What is OCC? Without OCC can we generate two pulses (alternative)

Occ is on chip clock controller it controls the switching between ATE low frequency and functional
frequency.

We can’t generate two pulses with out occ.

3. Explain slow to fall transition faults in circuit.

Transition faults occur when gate delay is larger than the expected delay.

Step-1:initialization the vector one(V1) is one , second vector is stuck-at one.

Step-2: launching the second vector(V2) means forcing the opposite value to vector2

Step-3: fault propagation.

4. Once we got 100% scan? Why we are facing again DRC’S in ATPG?

In scan insertion we check the clock and reset is properly connected or not.

In ATPG we check the C6- data considered as the clock, C2-set/reset considered as the clock.

5. Scan operation with diagram

Shift-in capture shiftout

6. DFT violations

1. clock rule violations: means the clock is not controllable from the primary inputs.

2.Reset rule violations: means these type of violations occur when the reset signal is not controllable
from the primary pins.

3.combinational feedback violations: means in which the faulty values is again going to the inputs .
because of this coverage is less. So control and observe the values . we can break the loops by applying
fault free value.
7. Why DFT is required?

In dft we test circuit to detect the manufacturer the faults. And also provides a controllability and
observability. Dft is the process of testing the each and every node of internal circuit before going to
production.

8. Without DFT is there any technique to use?

Yes .we can test the chip it takes much time and it generates more test patterns. Functional testing(PI
and PO)

9. Explain compression architecture? What is compression ratio?

The main objective of compression is to reduce the test cost and test data volume and also reduces the
test patterns .

Architecture of the compression is having two parts 1)decompressor 2) compactor

Compression ratio =(no of internal scan chains)/(no of external pins)

In compression ratio is mainly depands on no of internal scan chains. Y means we can not change the
external pins of chip.

10. How can you decide the number of scan channels?

Scan channels is mainly depands on external pins of chip.

11. What are the inputs for scan compression? And which technique is used and Why?

Scan inputs are the inputs to the scan compression. We are using EDT (embedded deterministic test) for
compression.

12. Explain clock skew ? How it can be controlled?

Clock skew occurs when we work on multi/lsingle clock domain. lsClock occurs in during shifting. During
shifting if we work only one clock domain we control. Another method is adding a lackup latch in scan
path it can avoid the clock skew permanently.

During capture apply one clock pulse per one pattern we can

13. What is multicycle, critical and invalid paths?

Critical path: critical path is nothingbut longest path in the design

14. What is lockup latch? What rule does it follow in scan?

Lockup latch is element which is mainly used to avoid the clock skew and also provides the half cycle
delay.

Lockup latch uses:

1)used to avoid the clock skew

2)used to avoid the hold violations

3) is used to merge the two different clock domains

15. Explain occ and opcg and their signIficance?

Both occ and opcg are same.

16. Draw D-flipflop and D- latch timing diagrams

17. Draw synchronous and asynchronous d- flip flop timing diagrams.

18. What is the difference between synchronous reset and asynchronous reset d-flip flop

19. In D-flipflop at What pin the asynchronous signal will connect?

20. Why at-speed clock is not used in shIft?

High switching activity(voltage droop and increase die temperature)

21. How to detect faults in scan chain?

Step-1: fault activation

Step-2:fault propagation

22. What are the inputs for ATPG?

Inserted netlistand technology libraries.

23. Explain D-algorithm with example?

24. Why DFT? What do you understand by DFT?

Here we are adding some extra logic to control and observe the nodes in the circuit. it provides
controllability and observability.

25. What is scan design? Which design have you used? And Why ?

We r using muxed scan design to controllability and observability. becoz there is no additional clock
routing.

26. Explain scan insertion steps and flow?

1)shift-in 2)capture 3)shift-out

Scan flow: original design

Rule check and repair

Testable design

Scan synthesis 1)scan configuration

2)scan replacement

3)scan reordering

4)scan stiching

Scan design

Scan extraction----------------------------------------------- [ATPG]

Scan verification<<-------------------------------------------------- |

27. How can you solve the clock skew problem while shIfting?

In two ways 1)using same clock domain for all scan cells

2)adding lockup latch

28. Why ATPG? ATPG flow?

ATPG-----automatic test pattern generation means it generates a test pattern for given fault.

Flow

1)build-model

2)build test mode

3)verify test structures

4)build fault model

5)test generation

6)write vectors

29. Explain build model, build test mode, verIfy test structures and build fault model?
Build model: In the build model it gives the statistics of how many of blocks are following hierarchical
model and how many of you following flattened model.it also consists of how many cells are connected
to tied and how many are dotted nets.

Build test mode: this s known as a configurational mode y means it includes how many external pins as a
inputs and how many are outputs and how many scan chains and clock definition and reset clock
definition.

Verify test structures: here we check the DRC violations.

Build fault model: it provides a statistics like these much faults are stuck at , these much faults are
transition like that only.

30. What are the issues you faced in scan insertion and ATPG?

SCAN : Clock violations, reset violations , combinational feedback loops ---------------like that.

ATPG: any clocking issues and scan chain issues and reset issues.

31. Initially If you have 30% fault coverage, How you will improve for 99%

1)First providing the controllability and observability.

2)check clock, reset pins whether we defined properly r not.

3) then check the transition fauls

4)increasing the sequential depth

32. Explain LOC and LOS?

Los:in the los both shift-in and shift-out can be done lower frequencis at SE=1 at the last shift

Launching the value. and capturing is done At higher frequencies and here the SE is routed as the
CLK to capturing and it takes very less time to Capturing the data

Here the value is launching at low freaquency at the last shift .

Loc: here the both shift-in and shift-out can be done at lower frequency and launching and capturing

Done at high speed frequencies. Here two high speed frequencies are needed one for launching the

Data and another one for capturing the data.

33. difference between stuck at and transition faults?

Stuck-at fault are related to functionality where as transition faults are related to timing

1) Test coverage is more than 99% in stuck at , test coverage is less.

2) In stuck at we use only one vector to fault propagation , in transition we use two test vectors.

3)These vectors are occur when one of its ip/op connected to stuck at0 or 1, these faults are occur

When gate delay is larger than the expected delay.

4) in the single stuck at we will have either stuck at zero or stuckat one, but in the transition fault

At each node will have have both slow-fall or slow to raise

34. What are the inputs for simulation?

Test patterns are the inputs to the simulation

35. How you will do simulation? What you observed in simulation?

It will mention total number of test patterns and it will give how many are matched and how many are
mismatched. It will also give the where the mis-compare occurs.

36. What are the types of simulation?

1. serial simulation 2)parallel simulation

37. How to decide the number of scan chains?

The scan chains are decided by the no of external I/O pins

38. Why we need to do shifting in scan chain?

To load the data in flip flops. after loading the values it will capture tha all data and then shift out.

39. at What stage the loaded values will go to the combinational logic?

capturing

40. If compression is failed? How you will find it?

41. where the compression fit into the process?

In the scan path only we will insert the compression logic.

42. How can you decide the compression ratio?

Compression ratio=(NO of internal scan chains)/(no of external scan channels)

43. Explain the sr-flip flop?

If s==0 and r==0 ; output is previous state

If s==0 and r==1 ; output is reset state

 If s==1 and r==0 ; output is set state

If s==1 and r==1 ; output is inderminate state

44. What is the difference between latch and a flip flop?

Both latch and flip flops are the memory elements these are mainly used to store the one bit data

Latch: latch is a sequential circuit y means output is not only depands on present input it also depands
upon the previous outputs

Latch is level sensitive, output = high when the enable is high.

Flip flop: is a sequential circuit y means output is not only depands on present input it also depands
upon the previous outputs

Flop is a edge triggered means , output is high one positive clk (negative) to another positive clk.

45. What is latency?can measured from

Clock latency is the amout of clock that can measured from source of the clock to sink

46. Which tools are used for ATPG, scan, simulation?

Scan insertin- cadence tool

ATPG, SIMULATION- nc SimS

47. What is chain balancing?

Scan balancing Is nothing but divide the equal no of scan chains based on the number of input and
output pins . Tool will automatically divides the number of scan chains in that.

Advantage:1) reduces the number of clock pulses

2)Reduces the number of pattens

3)reduces the number of locations where skew occurs.

48. What is a logic test and scan chain test in ATPG?

In scan test we generate the test patterns for scan test.

In logic test we generate patterns fot stuck-at faults

49. What is scan reordering?

The main objective of the scan reordering is to reduce the wire length . scan reordering includes
placement and routing. Change the order of the scan cells in order to reduce the wire length is known as
the scan reordering.

50. What is scan stitching?

Scan stiching is nothing but Connect all the scan cells after placement and routing.

51. How the lockup latch are connected in the scan chain?

Lockup latch is inserted positive flop and latch in connected to one clock domain, second positive flop is
connected to another another clock domain

52. What is clock skew?

If we use multiple/single clock domains in the design there may be a chance occurring clock skew. Clock
skew can be avoid permanently by adding lokup latch.

53. What is setup and hold time?

Setup time: setup time is the amount of time , how much the data signal is stable before the rising edge
of the clock. y means the propagation delay of the data signal is greater than the propagation delay of
the clock.

Setup time violations are avoided by increasing the frequency of clock.

Hold time: hold time is the amount of time , how much the data signal is stable after the rising edge of
clock. Y means propagation delay of data signal is less than the propagation delay of the clock signal

Hold violations are avoided by the adding buffers and lockup latch.

54. What is glitches? How to overcome these glitches?

Glitch is nothing but small output clock is produced in the output signal. Adding latch we can overcome
the glitch.

55. How to fix setup and hold time violations?

Setup time: setup time is the amount of time , how much the data signal is stable before the rising edge
of the clock.y means the propagation delay of the data signal is greater than the propagation delay of
the clock.

Setup time violations are avoided by increasing the frequency of clock.

Hold time: hold time is the amount of time , how much the data signal is stable after the rising edge of
clock. Y means propagation delay of data signal is less than the propagation delay of the clock signal
Hold violations are avoided by the adding buffers and lockup latch.

56. What is clock gaters?

Clock gaters are mainly used in the design is to reduce the power consumption which occurs due to
switching. For eg. Shifting should be activated only during SE=1 and at remaining times it is disabled
through this clock gaters.

57. What is the purpose of compression? Explain its use? Dat avolume

The main objective of the compression is to

1)reduce the test cost

2)reduce the test Data volume

3)reduce the test patterns

58. Why jtag? Explain its architecture?

JTAG: joint test action group

It follows a standard architecture , that can be be helpful to test the device easily.

It is having

1)TAP

2)TAP controller

3)registers

4)instruction set

59. Explain the boundary scan cells 1, 2, 4?

Boundary scan cell-1: normal boundary scan cell what we wer used in the jtag.

Bounadary scan cell-2: output is connected to the input as the data path to capturing the faulty value.

Boundary scan cell -4: it doesnot having the update operation.

60. Explain the use of occ?

Occ is mainly used to control the switching between ATE low frequency and functional frequency of the
pll.

61. Why ATE limit higher frequencies?

Because of high test cost only ATE limited to the higher frequencies.
62. Explain D- algorithm with example?

D-algoritham is mainly used to generate test patterns for given faults. D-algorithamd having 3 steps

Step-1:singular cover means(generate the excitation table to determine the non-controlling value)

Step-2:primitive d cube failure

S-0 repredented as D

S-1 represented as the D’

Step3:propagation of d cubes

Propate the fault by using non controlling values.

63. How scan chain works? Explain the modes of operation?

Scan operation is nothing but serial connection of the scan cells . it can be done in 3 steps 1)shift-in

2)capture 3)shift-out

64. What type of pattern generation is ATPG?

Deterministic test patterns. Y means it generates test pattens for intended design. Where we want
patterns for requiring.

65. What are the inputs and outputs of scan compression?

Scan inputs are inputs to the scan compression and outputs of scan compression is nothing but scan
outputs

66. Is DFT has any impact on technology shrinking?

Yes.

67. What is delay? Types of delay test?

Delays are occurs when it is fails to operate within the specified time limit

1)path delay test

2)transition delay test

68. What is transition delay testing?

these faults are occurs when the gate delay is is larger than the expected delay. At each node it will have
both slow-rise and slow-fall.

69. What is path delay testing?

These faults are occurs when the path delay is larger than expected delay. In which every path having
both rising and falling.

70. Why stuck at fault coverage is more than transition faut coverage?

In every circuit has more than 95% fault coverage is achieved by stuck at faults y means stuck faults are
placed a major role getting more coverage .means first we will go to testing the stuck-at faults. Every
have more stuck-at faults.

71. What is transparent latch? How we lose coverage from them?

It is a storage element. It has input, output and gate or enable signal. When enable is high,
output transparently follows the input. When enable is low, output freezes.

It is not recommended bcoz it creates glitches sometimes. So edge triggered D type ff is

recommended.

72. How to decide the sequential ATPG and Combinational ATPG?

Sequential atpg has 2 pulses and in loc after the last shift it has to store the state of the circuit
and the first clock pulse of the capture in order to know what is expected after the second
capture pulse.

Whereas in combinational atpg it has one pulse in capture and it does not have to store as to
how it will react after the second clock pulse.

73. What is the difference between verIfication and testing?

Verification :it verifies the correctness of the Functionality

Testing: it verifies the correctness of the design

74. Explain DFT flow?

1. Idea(need)
2. Specification
3. Design architecture(circuit diagram)
4. RTL (dia is converted into coding using Verilog)
5. Simulation (verification using testbench)
6. Synthesis (RTL is converted to netlist)
7. DFT (boundary scan, scan insertion)
8. Floor planning, placement and routing, STA
9. DFT – ATPG (test pattern generation)
10. Fabrication
75. Are the faults on the resets of the flops are detected? How?

Yes.

76. What is full scan design and partial scan design? And their difference?

Full scan design:

1. All ff are converted into scan ff.

2. Test time is high
3. Test coverage is high

Partial scan design:

1. Some flops are not converted into scan ff

2. Test time is low
3. Test coverage is low

77. Why scan chain patterns fail?

If scan enable is tied to x or 1 or 0, scan chain pattern fails. It fails to get the manufacturing
defect.

1. Defect in the scan flop

2. Defect in the net
3. Defect in the SE
4. Defect in the connection between ATE and scan chain

78. How tap fsm works?

It is a 16 state finite state machine which works under the control of TCK and TMS. The
transition from one state to another state occurs under the positive edge of TCK with the help
of TMS and during negative edge it is updated in the TDO.

1. Test logic reset

2. Run idle
3. Select DR scan
4. Select IR scan
5. Capture
6. Shift
7. Exit 1
8. Pause
9. Exit 2
 10. Update

79. How you will initialize the tap fsm?

By making TAP to wake up in Test_logic_reset state, it can be initialized properly.

But if it wakes up in some other state, then by giving continuous 5 ones it will go to the
test_logic_reset state and it is initialized properly.

80. What are the data registers in jtag?

1. Boundary scan
2. Bypass register
3. Identification register

81. What is bridging fault?

Short between two nets in the circuit.

The two signals are connected when they are not supposed to be. Depending on the logic
employed, they are divided into

1. Wired and/or
2. Dominant
3. Dominant and/or

82. What is iddq fault?

Measuring the supply current (Idd) in the quiescent state (hibernate state).

Quiescent- when the circuit is not switching and the inputs are held at a static state.

Test patterns are used to place the DUT under different selected states. By performing current
measurements at each of these static states, the presence of defect that draws excess current
can be detected.

Adv:

Many types of faults are detected with very few patterns

Disadv:

Additional test time to perform current measurement

83. Implement xor using 2*1 mux?

84. What is controllability and observability?

Controllability: Ability to place the node, net, gate with a known logic value.

Observability: Ability to observe the node, net, gate after they have been driven to a known
value.

85. How can you convert rtl file to gate level netlist?

RTL is converted into gate level netlist through Xilinx by using testbench. It is nothing but the
conversion of Verilog or VHDL to gate level.

86. How can you convert normal flop to scan flop? Why is it necessary?

1. Normal flop is converted into scan flop by adding mux in front of normal flop.
2. The output of one flop is connected to the input of next flop forming a shift register.
3. It is necessary because it provides controllability and observability to each and every
node in the logic

87. can reset pin be used as clock?

Reset is used to initialize the hardware. In simulation, it is used in the beginning. In hardware, it
is used to power up the circuit.

If reset acts as clock, then it is nothing but similar to asynchronous reset ff (it does not depend
on clock) which is not recommended as it may produce glitch and metastability.

To understand the metastability issues consider that the clock rising edge comes right after the
reset edge. The d ff must have certain minimum time between reset edge and clock edge,
called reset recovery time. If this time duration is violated, the output is not guaranteed.

88. Explain clock driving data?

Clock derived data.

89. who takes the responsibility of converting flop to scan flop?

DFT engineers are responsible for converting flop to scan flop in order to make each and every
node controllable and observable.

(Scan chain based testing is a standard DfT (Design for Testability) due to its simple design and low cost.
But this method can act as back door, through which the hacker can retrieve the sensitive information
through side channel attack. Therefore we developed an efficient and inexpensive LFSR (linear feedback
shift register) based secured architecture through which it provides predominant security without
effecting testability. The experimental result leads to a low area and power overhead with a secure
methodology.)

90. Explain design rule checks?

It is used to check the violation in the design which prevents design from working properly.

1. Bidirectional I/O port

2. Clock violation
3. Aysync set/reset violation
4. Derived clock
5. Clock gating
6. Combinational feedback

91. How to improve coverage analysis?

1. Stuck at fault
2. Transition fault
3. Other faults

92. Why cant we use functional patterns as test patterns to detect the faults?

The functional test patterns are longer and time consuming

Eg. For 2 input nand gate, possible combinations are 4. So all 4 patterns will be provided to test.

As number of pins increases, the number of patterns will increase dramatically. So using atpg, in
structural testing the number of patterns are reduced using DTPG method.

93. What is bypass register?

It is a kind of data register which is used to reduce the distance between tdi and tdo when the
chip is idle. Instead of passing all the way through boundary registers, it provides the shortet
pathway to pass the data.It reduces the number of clock pulses.

94. How you will fix the combinational feedback loop?

By providing mux in the feedback loop in order provide controllability and observability.

1. If TM=0, it selects the functional mode, so the ouput of comb logic is connected to the
feedbck.
2. If TM=1, it selects scan mode, so ouput of scan mode is connected to the mux input (it
maybe either capture or shifted value based on SE)

95. where you will find the bus contention problems?

If two bus drivers force opposite logic values onto a tristate bus, bus contention occurs.

It should be made in such a way that only one driver should be connected to bus at a time.

So when SE=1, the enable of intended tristate is connected to OR gate whereas others are all
connected to AND gate via inverter which makes them in off state.

And also bus keeper is included to preserve the value prior to floating.

96. How you will fix the asynchronous rule violation?

By adding a mux to the enable signal

When TM=0, the output of flop is connected to the reset enable, so depending on that it resets.

When TM=1, logic 1 is connected to the enable signal which disables the reset during scan
mode.

97. can we fix the asynchronous rule violation without using mux ?

Yes. Using OR gate to the enable signal

When TM=0,functional mode, so it resets.

When TM=1, scan mode, it cannot reset as it is enable low.

98. can we fix the asynchronous rule violation for active high reset ?

Yes. The same way but if mux is used during TM=1, logic 0 is given as input to enable.

If inverter followed by AND gate should be used instead of OR gate.

99. What are the uses of boundary scan cells?

It is used for shifting between from one cell to another.

It lets the device to check the interconnection without using physical probe.

Minitiaturisation of device

100. What are the uses of bc-7?

It uses bidirection I/O pins

101. What is the fsm used in tap?

16 state synchronous fsm is used in tap which is controlled by TCK and TMS

102. How many scan clocks are used in scan?

It is based on scan type.

1. For mux type, one scan clock is used

2. For clock type, two san clocks are used
3. For LSSD, three scan clocks are used

103. What is scan chain shIfting? Why we need to shIft and Why we need to capture? What
do you do in capture?

Scan_in, capture and scan_out are the three main operations of scan chain.

1. Scan_in is used to shift in the pattern to the ff when SE=1

2. Capture is used to capture the manufacturing defects in the combinational logic to the
next flop when SE=0
3. Scan_out is used to shift out those manufacturing defects to the output.

The process of shifting will cover all parts of device and test coverage will be more

(Typical scan frequency is the frequency that most of the ATE's use when scaning in the data to
the scan flops. it is typically around 1-10 Mhz.)

104. states in tap controller? Why data registers come before instruction register?

16 states are in TAP controller. To flush out some patters which are already present in it.

105. In TAP, If TMS is not toggling What happens?

Then it will go to the reset state of TAP ie. Test_logic_reset.

106. What is test coverage and fault coverage? Its difference and which is mostly considered?

The ratio of num of detected faults to the total num of faults is called fault coverage.

The ratio of num of detected faults to the total num detectable faults is called test coverage.

Detectable faults= total faults-undetectable faults

Test coverage is mostly considered as it excludes the undetectable faults and its coverage is
higher.

107. How did you increase your test coverage in ATPG and What are the dIfferent violations?

1. 100% scan design

2. Use sequential patterns
3. No x in the design
4. More num of test points
5. Completely defined netlist ie. No floating input and output pins
6. Avoid contention
7. Avoid bus floating

108. How transition faults are detected?

Two vectors are used to detect transition fault.

1. To initialize the node

2. To launch and propagate the value from the node to the output

109. What is at-speed testing?

It is nothing but transition test. This test model uses test pattern that creates a transition
stimulus to change from logic value from either 0 to 1 or 1 to 0. The time allowed for transition
is specified. If it doesn’t happen, then ffault occurred.

110. How many at-speed clocks can be generated ?

Based on the transition technique selected by the engg, the number of at_speed clock pulse is
generated.

1. If LOC, two at_speed clock pulse is needed.

2. If LOS, one at_speed clock pulse is needed.

111. What is launch and capture? What do you do during launch and capture?

Launch - The value or pattern which makes transition at the particular node.
Capture – The value which is captured after the transition is made.

During launching, the value or pattern which makes transition at the node will be provided to
the flop and during capturing, the value produced after transition will be captured by the
output flop. They happen at functional speed.

112. Explain mandatory instructions?

1. Extest – The selected DR is boundary scan. It is used to check the interconnection

between two boundary scan.
2. Bypass – The selected DR is bypass reg. It provides the shortest path to pass the value
between tdi and tdo.
3. Sample – The selected DR is boundary scan reg. It is used to examine or snapshot the
input and output pins.
4. Preload – The selected DR is boundary scan reg. It is used to preload the value and
observe the value at the output.

113. What is undetectable faults. How to detect faults and is test point insertion is enough
to make it controllable?

1. Blocked pins – tied to gnd/vcc

2. Tied pins – here the designer has purposefully tied the pin to logic high or logic low
3. Unused pins – q’
4. Redundant pins

Faults that cannot be tested are called undetectable/untested faults.

114. which approach is used for scan insertion?

DFT approach

115. What is adhoc approach? Explain with one example?

The test point insertion is used where there is more difficulty in testing.

116. How you can reduce the test time using DFT?

Without DFT, it ll take more time. For eg , if there are 1 million pins, testing will take 10s for
each pin. In such way, it ll take 3 and half months to finish testing for all pins without using DFT.

Whereas by using DFT this test time is reduced by 3 and half days as we are using compression
technique, atpg .

117. If the compression ratio is increased, What are the issues?

118. What are the ouput files for scan and ATPG?

For scan, the scan out which is nothing but the manufacturing defects are output. It is stored in
GDS or SDF file.

For atpg, the effective test pattern is the output. It is stored in ATE in the form of STIL or WGL
file.

119. What is ATE? What it does?

Automatic Test Equipment.

1. It stores the Test patterns

2. It has comparator which compares the available result with the golden result
3. It has pin electronics which maintains the input and output pins of IC

120. What are test procedure files?

Sdc files.

The test procedure file contains all the scan information of your test ready netlist.

1. The number of the scan chains

2. The number of scan cells in each scan chain.

3. The shift clocks.

4. The capture clocks

5. Any test setup procedure required before starting the test pattern generation

6. The timing of the different clocks.

7. The time for forcing the Primary input , bidi inputs , scan inputs etc

8. The time to measure the primary outputs, scan outputs , etc ..

9. The pins which have to be held at some state in the different procedure as load_unload, shift
etc ..

121. Explain cross coupled gates scan design rules?

122. What is serial and parallel simulation? Explain its difference?

Serial simulation – It takes the clock pulse equal to the num of ff for loading and it is used for
loading value from ATPG to ICs input and output pins.

Parallel simulation – It takes only one clock pulse for loading and so it is preferred as it takes
less time.

123. What are the inputs for serial and parallel simulation?

testpatterns

124. How do you place test points after scan stitching?

125. What are the issues you faced when your design is not controllable and observable?

Fault coverage of the design is less.

Complexity in generating test vectors.

Testing of design in terms of manufacturing defects is difficulty.

126. What is test mode? Explain?

Test mode is the control pin and which selects mode of operation between functional mode and test
mode.

TE =0 functional or normal mode

TE=1 test mode.

127. Explain scan methodology?

Scan-in capture scan-out

128. What is scan frequency?

10 to 50mhz

129. What is the tester memory capacity in your design?

32gb.

130. What is lfsr?

Linear feedback shift reg.

131. What is masking logic? Its purpose?

132. How many flops are used in your project? ( complete project analysis)

300 flops.

133. What if I cannot able to provide capture pulse? What are the issues?

Faults will not be detected if we don’t provide capture pulse. And location of faults in the design cant be
happen.

134. Explain the commands related to tcl file?

135. Why scan chain contain first negedge scan flop then posedge scan flop?

To avoid hold time violation. And to get output at the 2 nd active edge of pulse.

136. Is lockup latch DFT friendly?

No.

137. What is fault collapsing, equivalence and dominance?

Refer notes.

138. How many test patterns you have generated in your project?

30 patterns

139. Types of fault models?

Stuck at

Bridging , transition, delay, transistor stuck open \short faults, iddq faults, memory faults.

140. How can you decide the number of test patterns in your design?

Based upon inputs, if n no of inputs there will be 2^n test patterns (exhaustive)

141. Why DFT require? Can we achieve DFT goals by any other method?

Requirement of dft in design to enhance the testability by introducing the controllability and
observability of each node, wires, sequential and combo logic in the design. we can’t achieve dft goals
by other method.

142. Where DFT part fit in ASIC design flow?

At the gate level netlist.

143. What is yield and dppm? Its difference?

Yield= (no of acceptable faults ) /(total number of faults manfactured)

Dppm=

144. How to detect stuck at faults? Explain with diagram?

Fault excitation

Fault propagation methods.

145. What could be the possible reasons for scan chain failures during gate level simulation?

Hold time violation between two different clock domains.

Improper stitching of scan flops, that is configuration –ve followed by +ve flops may not be used.

No proper initialization of input sequence that may fail to put scan chain into test mode

Hold time violation within clock domain between the flops bcz of improper cts.

Bcz of scan rule violations.

146. Can we improve the capture cycles?

no

147. What is sequential depth?

Sequential depth is an phenomena to increase test coverage of design by generating test patterns for
the non- scanned flops. We will assign seq depth to non- scan flop, by default it has range of 0 to 255. So
that atpg will recognize the those flops and generate test patterns .

148. How do you test at-speed faults for inter clock domains?

By using loc and los metods.

149. What is integrated clock gating?

150. How ATPG pattern are useful to accelerate burn-in testing?

151. What is meant by scan chain pattern? Why it require?

Scan chain pattern is flush pattern used to verify scan chain during shift operation. The pattern is 110011
,contains all the combinations of 0’s and 1’s.

152. What is the difference between vector and pattern?

Vector term used for logic simulation.

Pattern term used for fault simulation.

153. which scan style is preferred for scan insertion?

Muxed based scan stle.

154. What are the dIfferent untestable faults?

1.Redundant faults.

155. How to fix black box violation?

156. What are the reasons for scan chain broken?

Pvt variations during manufacturing.

157. How to debug faults in fault simulation?

158. Explain complete test procedure for fault simulation?

159. Explain sample and preload instruction?

Li vedio.

160. Applications of boundary scan?

Pcb testing: provides fault diagnosis and debugging

Scan path infrastructure testing.

Device io pins testing

chip interconnection testing.

Internal logic testing

161. What is the importance of sequential depth?

Sequential depth invokes non scanned flops in the combo logic for atpg to generate the test patterns. To
increase the test and fault coverage of the design.

162. How to decide capture cycles and shift cycles?

Shift cycles: based upon the length of the scan chain, no. of flops on scan chains. Based upon the test
patterns length.

Capture cycle: usually we one pulse for stuck at faults and for transition faults 2 pulses required.

163. Why we test transition faults at at-speed?

Transition faults are related to timing behavior of the design. so we want to check the failure of the
timing behavior of each component and each node at at-speed only to ensure the correct operation the
design.
164. What is terminal lockup latch?

Lock up latch is level sensitive device ,used in scan design where hold timing violations are occur in the
design , which provide half time delay for capture flop so that data can be arrives after the 2 nd pulse.

165. What are redundant faults?

A combo logic ckt contains an undetectable stuck at fault is said to be redundant Faults. It can be
simplified by removing at least gate or gate input.

166. What is compression ratio? where do compressed scan chains come from?

No. of external scan channels to no. of internal full scan chains.

167. What is the difference between LOC and LOS? Which is mostly used?

Los : launching will be done at last shift of scan

During capture, single at speed clock pulse required to capture the faults to flops.

combinational atpg is used to generate test patterns

high fault coverage

less testing time bcz less no of patterns

Scan enable can routed as a scan clock so there will routing problem at the design implementation.

Loc: launching and capturing will be done at at speed clocks only

Scan enable will not be routed at scan clock so there is not problem at design side during routing.

Requires seq atpg

Patterns are more , complexity in generation of patterns

Fault coverage is less, more testing time.

168. Is there any need of pll when functional frequency equals to scan frequency?

No need

169. What is the format for test vectors?

Zeroes and ones patterns or vice versa.

170. Why scan clock is slow frequency? What if we give high frequency for scan chains?

We need to shift scan data at slower freq bcz to avoid higher dynamic switching activities which intern
reduces power dissipation.
During shift mode, there is toggling at the output of the each flop, also within the combo logic, which is
more than functional mode. Usage of high freq cause the following problems

Volage drooping

Increase in the temperature die cause the damaging of chip.

171. What is shadow logic?

It is the logic to increase testability of the logic around the modules for which the atpg can’t generate
test patterns. This adds the ability to observe the data on the nets connected to inputs of the untestable
logic.

And control the nets connected to the output of the untestable logic

172. Why multi clock domains is used? Does it have any problem in design?

Ip reuse

Ability to reduce functional power by turning off clocks for unused blocks at any time

Difficulties in clock tree synthesis for a single clock domain in a large soc

Problem with having multi clock domains is that skew problem. Hold time violation.

173. What logic we see in test point insertion?

Control -1 and control-0 test point insertion logic.

174. What is named capture procedures?

These are behavioral modules. Provides relationships between the internal and external clocks when we
used on chip clock generation systems.

175. How iddq test vectors are different from stuck at test?

Iddq test patterns on the base of current measurements

Stuck at on the base of voltage measurements.

176. Explain the decompression logic?

Refer notes.

177. why reset is optional in jtag? When reset state occurs?

Designed is made in such a way that there is consecutive ones on TMS on rising edge of clock resets the
jtag. Hence reset pin optional from external.
178. Explain architecture for compression?

Refer notes.

179. why we do scan chain balancing?

To reduce testing time. And to reduce the test patterns counts.

180. Explain tap controller working? On what edge tap works?

Refer notes. On Positive edge the tap will works.

181. what is the minimum bits for instruction?

2bits. 01

182. Advantages and disadvantages of LOC and LOS?

Refer previous question.

183. What are the tools used for scan, ATPG, simulation? What is the library file name?

Scan :genus legacy, library file name –

Atpg: encounter test, library file name-

Simulation: nc-sim library file name-

184. What did you do in simulation? Explain the procedure? Difference between serial and parallel
loading?

Simulates the design in the presence of faults called simulation.

Procedure:

Differences.

Serial loading is applying test patterns from ate to cut

Parallel loading is to capturing the fault effects from combo to flops concurrently.

185. Difference between normal mode, functional mode and scan enable?

In functional mode : TE =0 ckt performs functional operations.

Scan enable : TE=1 SE =1 shift operation

TE =1 SE=0 capture operation\normal opertaion

186. Tell me stuck at faults other than sa1 and sa0?

Slow to rise and slow to fall faults.

187. what is the difference between gate level faults and transistion level faults?

Gate level faults such as sa1 and sa0 faults. which are not delay constrained and timing constraints
faults.

Occurs bcz of permanent shorts to vdd or gnd.

Transition faults faults are slow to rise and slow to fall faults, which are delay and timing constrained
faults.

Occurs bcz of variation in propogation delay

188. Why you need burn-in test?

Performs on every hardware devices,

They enable detection of any problems before releasing to market.

Burn in test determines the maximum temperature the device can sustain and also checks the product
reliability.

189. what do you know about cell aware test?

Transistor level atpg based test methodology that achives significant quality and efficiency
improvements by directly targeting specific shorts, opens and transistor defects internal to each
standard cell.

Method to determine defects inside the library cells

190. why you need to test critical paths?

We have to test the critical path to ensure that its under timing constraints or not.