CMOS Digital Logic Design - Detailed
Notes
1. Introduction
Digital Logic Design deals with designing circuits that process binary signals (0 and 1).
CMOS technology is the most widely used for implementing digital circuits due to low
power dissipation, high noise immunity, and high packing density.
All modern microprocessors, memories, and ASICs are built using CMOS digital logic.
2. CMOS Logic Basics
A logic gate is formed using a Pull-Up Network (PUN) and Pull-Down Network (PDN).
PUN is made of PMOS transistors (connect output to VDD when ON).
PDN is made of NMOS transistors (connect output to GND when ON).
Rules: PUN and PDN are complementary. Both should not conduct simultaneously.
Insert Figure 1: General CMOS logic gate structure.
3. CMOS Inverter (NOT Gate)
Simplest CMOS logic gate consisting of 1 PMOS and 1 NMOS.
Output = complement of input.
Truth Table:
A=0 → Y=1
A=1 → Y=0.
4. CMOS NAND Gate
For N-input NAND: PDN uses NMOS transistors in series, PUN uses PMOS in parallel.
Example: 2-input NAND gate.
Truth Table:
00→1, 01→1, 10→1, 11→0.
Insert Figure 2: 2-input CMOS NAND circuit.
5. CMOS NOR Gate
For N-input NOR: PDN uses NMOS in parallel, PUN uses PMOS in series.
Example: 2-input NOR gate.
Truth Table:
00→1, 01→0, 10→0, 11→0.
Insert Figure 3: 2-input CMOS NOR circuit.
6. Complex CMOS Logic Gates
NAND and NOR are universal gates and can form any Boolean function.
Examples include AOI/OAI gates (AND-OR-Invert, OR-AND-Invert).
XOR gates require more transistors than NAND/NOR.
7. Logic Design Rules
Ensure no direct path from VDD to GND.
Maintain complementarity of PMOS/NMOS networks.
Use minimum number of transistors for efficiency.
8. Switching Characteristics
Propagation delay (tp): Time between input change and output response.
Depends on load capacitance (CL), transistor sizes (W/L ratio), and supply voltage (VDD).
Equation: tp ≈ (CL × VDD) / Idrive.
9. Power Dissipation in CMOS Logic
Static Power: Ideally zero but leakage currents exist.
Dynamic Power: Due to charging/discharging of capacitances.
Equation: Pdynamic = α CL VDD² f.
Short-Circuit Power: When both NMOS and PMOS conduct during switching (very small).
10. Noise Margins in Logic Gates
High noise margin = tolerance against electrical noise.
CMOS logic has better noise margin than NMOS/PMOS-only logic.
11. Fan-In and Fan-Out
Fan-in: Maximum number of inputs a gate can handle.
Fan-out: Maximum number of gates an output can drive.
Both depend on transistor sizing and capacitance.
12. Advantages of CMOS Digital Logic
Very low static power consumption.
High integration density.
High noise immunity.
Suitable for high-speed and low-power design.
13. Limitations
Fabrication complexity compared to NMOS-only logic.
Leakage currents increase in deep submicron technologies.
Delay increases with large fan-in gates.
14. Applications
Used in microprocessors, memory (SRAM, DRAM), DSPs, ASICs, FPGAs.
Foundation of all digital IC design.
Used in low-power applications (wearables, IoT devices).
