Design Of 1-Bit Full Adder Using CMOS Mirror Logic
Yajnesh K, Mangalore Institute Of Technology & Engineering
April 17, 2022
Abstract
This paper presents a 1-bit full adder cell designed by using 2. Circuit
the CMOS mirror technique. The full adder circuit is one of
the most widely used building blocks in all arithmetic and
digital data processing systems. This circuit accepts two 1-
bit inputs and produces two 1-bit outputs i.e. sum and
carry. We use the property of inversion and self-duality to
design this circuit. Because nowadays we have to deal with
huge bits of data, we can switch to more advanced adder
architectures like RIPPLE CARRY, CARRY SKIP, CARRY
SELECT, CARRY LOOK AHEAD, etc. The major drawback of
the CMOS mirror circuit is that it consumes more power
and occupies more area due to the greater number of
transistors used.
1. Reference Circuit Details
3. Waveform
Transistor level implementation of full adder using CMOS
mirror logic uses 28 transistors out of which 14 are nmos
and 14 are pmos. By using CMOS mirror design we can save
an area of 12 transistors as compared to the conventional
CMOS approach. If a function obeys both inversion and self-
duality properties then we can mirror the nmos stack to
pmos i.e. pull-up stack is symmetrical to pull-down, unlike
the opposite to pull-down stack in conventional CMOS. By
this approach, we can reduce pmos stack size and can have
equal rise and fall delays. Instead of realizing two functions
independently, we will use cout signal to generate sum
signal. The full adder circuit presented in this paper can be
further used as a building block to generate an N-bit adder, References
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