Heritage Institute of Technology

(An Autonomous Institute)

Department of
Electronics and Communication Engineering

FULL ADDER IMPLEMENTATION AND LAYOUT USING CMOS

Affiliated
to
Maulana Abul Kalam Azad University of Technology
(Formerly WBUT), 2022

Name : Arjaita Aditya

Roll No : 2152065
Roll No : 12621003032
Registration No : 211260100310127

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 ACKNOWLEDGEMENTS

The achievement that is associated with the successful completion of any task would
be incomplete without mentioning the names of those people whose endless
cooperation made it possible. Their constant guidance and encouragement made all
our efforts successful.
I take this opportunity to express my deep gratitude towards my project mentor,
Shouvik Sarkar for giving such valuable suggestions, guidance and encouragement
during the development of this project work.
Last but not the least I am grateful to all the faculty members of Ardent Computech
Pvt. Ltd. for their support.

Signature of the Student: (Arjaita Aditya)

Abstract

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Designing a full adder project offers numerous educational benefits that bridge
theoretical understanding and practical application. The exploration of 10T and 8T
full adder designs using CMOS technology, along with layout development via
Microwind and simulation through DSCH, presents a comprehensive learning
experience. Implementing full adders using 10T (10-transistor) and 8T (8-transistor)
CMOS structures underscores the importance of power efficiency and speed in
modern digital circuits. Further, the practical applications of full adders in various
fields, such as computer architecture, digital communications, and embedded
systems, highlight their relevance in contemporary technology. Overall, this project
fosters a robust foundation in digital design principles that are essential for future
electronics and communication engineering endeavors.

CONTENTS

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 Title Page No.

1. Introduction 6

2. Problem definition 7

3. Objectives of Full Adder 8

4. Full Adder design using Logic Gates 9

5. Full Adder implementation through CMOS gates

5.1 10T Model of Full Adder 9

5.2 8T Model of Full Adder 14

6. Layout of Full Adder 15

7. Voltage VS Time Curve of Full Adder 15

8. Theory of Full Adder using Microwind and DSC 16

9. Implementation 17

10. Applications 17

11. Conclusion 18

12. References 19

INTRODUCTION

A full adder is a fundamental digital circuit used in arithmetic operations, particularly

in binary addition. It takes three inputs: two significant bits (A and B) and a carry-in
bit (Cin), and produces two outputs: the sum (S) and a carry-out bit (Cout). Full

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adders are essential components in constructing more complex arithmetic circuits,
such as adders in arithmetic logic units (ALUs).
The implementation of a full adder using CMOS (Complementary Metal-Oxide-
Semiconductor) technology is particularly advantageous due to its low power
consumption and high noise immunity, making it suitable for modern VLSI (Very
Large Scale Integration) applications. CMOS technology employs both PMOS and
NMOS transistors to achieve efficient logic designs with minimized static power
dissipation.
This project involves designing a full adder circuit with a focus on the logic
implementation, creating a schematic using VLSI design tools, and developing a
physical layout that adheres to design rules. Performance analysis, including power
consumption and propagation delay, will ensure the circuit meets operational
requirements, making it an integral part of digital system design. Through this work,
we aim to enhance our understanding of digital circuit design, layout techniques, and
the practical applications of CMOS technology in modern electronics.

PROBLEM DEFINITION

FULL ADDER IMPLEMENTATION AND LAYOUT USING CMOS

The objective is to design and implement a full adder using CMOS technology for
VLSI applications. A full adder computes the sum and carry outputs from three
binary inputs: A, B, and Cin. This project involves creating a CMOS schematic that

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effectively combines PMOS and NMOS transistors to achieve desired logic
functions.
Following the schematic design, a physical layout will be developed, adhering to
specific design rules for a chosen technology node (e.g., 180 nm, 65 nm).
Performance metrics such as power consumption, propagation delay, and silicon area
must be analyzed through simulations to ensure functionality and efficiency.
Deliverables include schematic diagrams, layout files, simulation results, and a
comprehensive report documenting the design process and findings. Challenges
include balancing power and speed while addressing design complexity and process
variations.

DETAILS OF THE TRAINING PROGRAME

OBJECTIVES OF FULL ADDER:

The objective of a full adder circuit is to perform the arithmetic sum of three input bits: two
significant bits and an incoming carry bit from a previous addition. Specifically, a full adder
calculates the sum and carry outputs for these three inputs, which are typically
denoted as:
𝐴: The first input bit

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𝐵: The second input bit.
𝐶𝑖𝑛: The carry-in bit, which is the carry from the previous less significant bit addition.

The full adder produces two outputs:

Sum (S): This is the bit-wise sum of the three inputs.
Carry-out (𝐶𝑜𝑢𝑡): This is the carry-out bit that will be passed to the next more significant bit
position in a multi-bit addition.
The relationships between the inputs and outputs are given by the following equations: Sum (𝑆:)=
A⊕𝐵⊕𝐶𝑖𝑛: A⊕B⊕C in
Carry-out (𝐶𝑜𝑢𝑡) = (𝐴⋅𝐵) +(𝐵⋅𝐶𝑖𝑛) +
(𝐴⋅𝐶𝑖𝑛) Where:
⊕ denotes the XOR (exclusive OR) operation.
⋅ denotes the AND operation.
The full adder is a fundamental building block in digital electronics, particularly in arithmetic logic
units (ALUs) and in the design of binary adder circuits used in calculators, computers, and other
digital systems requiring binary addition.

FULL ADDER DESIGN USING LOGIC GATE

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It takes three inputs (in1-A), (in2 – B), (in3- C_in) and produces two outputs: the sum (S) and the
carry-out.
FULL ADDER IMPLEMENTATION THROUGH CMOS GATES
The literature review demonstrates that there has been an extremely broad range of adder design
options available during the past few decades. There are a few different designs for low power and
high-speed adder cells that may be found in the published literature. Full Adder circuits can be
designed using various number of transistors. But this will be focused on the designs that take lesser
number of transistors thereby pinpointing towards low-power, faster and simpler circuitry models.
10 T MODEL OF FULL ADDER
A traditional full adder with 28 transistors has been devised with 10 transistors of an equal amount
of PMOS and NMOS, guaranteeing the proper switching activity. It consists of five CMOS
inverters connected in a specific arrangement. Input A is connected to the first inverter directly
while Input B connects to the second and third inverters.

This is the 10T model of Full adder that uses pass transistor logic.
Now we will check whether the designed 10T model of full adder executes the original Full adder
truth table.

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A=0, B=0, C_in=0 gives Sum =0, C_out=0

A=0, B=0, C_in=1 gives Sum=1, C_out=0

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A=0, B=1, C_in=0 gives Sum=1, C_out=0

A=0,B=1,C_in=1 gives Sum=0, C_out=1

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A=1, B=0, C_in= 0 gives Sum=1 and C_out=0

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 A=1, B=0, C_in=1 gives Sum= 0 and C_out=1

A=1,B=1 and C_in=0 gives Sum=0 and C_out=1

A=1,B=1,C_in=1 gives Sum=1 and C_out=1

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 So as per above results, the 10T model designed in DSCH executes the truth table of FULL
ADDER.

8T model of FULL ADDER

This 8T model is another energy efficient model that uses 3T XOR gates to generate the Sum and
carry output and optimize power.

These 2 models are extensively used because of low transistor count, less power consumption and
high efficiency.

LAYOUT OF A FULL ADDER

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VOLTAGE VS TIME CURVE OF A FULL ADDER

THEORY OF FULL ADDER USING MICROWIND AND DSC:

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 Designing a full adder using Microwind and DSC (Digital System Design)
involves understanding the theoretical concepts of a full adder circuit and then
implementing it using a digital design CAD tool like Microwind. Here’s a
comprehensive overview of the theory and practical steps involved:

Theory of Full Adder

A full adder is a digital circuit that adds three input bits (A, B, and Cin) and
produces two output bits: the sum (S) and the carry-out (Cout).

Truth Table:

 Inputs: A (input bit), B (input bit), Cin (carry input)

 Outputs: S (sum), Cout (carry-out)

Boolean Equations:

 Sum (S)=A⊕B⊕CinS
 Carry-out (Cout) =(A⋅B) +(Cin⋅(A⊕B)) C_{out}

Designing a full adder using Microwind and DSC (Digital System Design) involves
understanding the theoretical concepts of a full adder circuit and then implementing
it using a digital design CAD tool like Microwind. Here’s a comprehensive
overview of the theory and practical steps involved:

Implementation:

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 A full adder can be implemented using logic gates such as XOR gates,
AND gates, and OR gates. In integrated circuit design, it's typically
implemented using transistor-level logic to achieve efficient operation and
compact size

Applications:

 Arithmetic Operations: Full adders are essential components in

processors and calculators for performing addition operations on binary
numbers.
 Data Processing: Used in digital signal processing, communications, and
encryption algorithms where binary addition is required.
 Sequential Logic: Building blocks for more complex circuits like adders
with larger word lengths, multipliers, and accumulators

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 CONCLUSION

The full adder circuit, despite its simplicity, has a broad and impactful future
scope. As technology evolves, the need for efficient, reliable, and high-
performance arithmetic units will drive continued innovation and research in full
adder design and implementation. By staying at the forefront of these
advancements, engineers and researchers can contribute significantly to the next
generation of computational and electronic systems

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 REFERENCES

REFERENCES FOR THE PROJECT:

Books:

 "Digital Design: With an Introduction to the Verilog HDL, VHDL, and

System Verilog" by M. Morris Mano and Michael D. Ciletti:
 This book covers the fundamentals of digital design, including detailed
chapters on combinational circuits like the full adder, and provides
practical insights into hardware description languages.
 "Digital Logic and Computer Design" by M. Morris Mano:

Web Resources:
 All About Circuits - Full Adder
 This online resource provides a detailed explanation of the full adder
circuit, including its truth table, Boolean expressions, and logic gate
implementation. All About Circuits
 Khan Academy – Adders
 Coursera - Digital Systems: From Logic Gates to Processors
 edX

These references provide a comprehensive understanding of full adder circuits,

from basic theory and design principles to advanced applications and
optimizations. They are valuable resources for students, researchers, and
practitioners in the field of digital electronics and computer engineering.

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